lima_pp.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR MIT
  2. /* Copyright 2017-2019 Qiang Yu <[email protected]> */
  3. #include <linux/interrupt.h>
  4. #include <linux/io.h>
  5. #include <linux/device.h>
  6. #include <linux/slab.h>
  7. #include <drm/lima_drm.h>
  8. #include "lima_device.h"
  9. #include "lima_pp.h"
  10. #include "lima_dlbu.h"
  11. #include "lima_bcast.h"
  12. #include "lima_vm.h"
  13. #include "lima_regs.h"
  14. #define pp_write(reg, data) writel(data, ip->iomem + reg)
  15. #define pp_read(reg) readl(ip->iomem + reg)
  16. static void lima_pp_handle_irq(struct lima_ip *ip, u32 state)
  17. {
  18. struct lima_device *dev = ip->dev;
  19. struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
  20. if (state & LIMA_PP_IRQ_MASK_ERROR) {
  21. u32 status = pp_read(LIMA_PP_STATUS);
  22. dev_err(dev->dev, "pp error irq state=%x status=%x\n",
  23. state, status);
  24. pipe->error = true;
  25. /* mask all interrupts before hard reset */
  26. pp_write(LIMA_PP_INT_MASK, 0);
  27. }
  28. pp_write(LIMA_PP_INT_CLEAR, state);
  29. }
  30. static irqreturn_t lima_pp_irq_handler(int irq, void *data)
  31. {
  32. struct lima_ip *ip = data;
  33. struct lima_device *dev = ip->dev;
  34. struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
  35. u32 state = pp_read(LIMA_PP_INT_STATUS);
  36. /* for shared irq case */
  37. if (!state)
  38. return IRQ_NONE;
  39. lima_pp_handle_irq(ip, state);
  40. if (atomic_dec_and_test(&pipe->task))
  41. lima_sched_pipe_task_done(pipe);
  42. return IRQ_HANDLED;
  43. }
  44. static irqreturn_t lima_pp_bcast_irq_handler(int irq, void *data)
  45. {
  46. int i;
  47. irqreturn_t ret = IRQ_NONE;
  48. struct lima_ip *pp_bcast = data;
  49. struct lima_device *dev = pp_bcast->dev;
  50. struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
  51. struct drm_lima_m450_pp_frame *frame;
  52. /* for shared irq case */
  53. if (!pipe->current_task)
  54. return IRQ_NONE;
  55. frame = pipe->current_task->frame;
  56. for (i = 0; i < frame->num_pp; i++) {
  57. struct lima_ip *ip = pipe->processor[i];
  58. u32 status, state;
  59. if (pipe->done & (1 << i))
  60. continue;
  61. /* status read first in case int state change in the middle
  62. * which may miss the interrupt handling
  63. */
  64. status = pp_read(LIMA_PP_STATUS);
  65. state = pp_read(LIMA_PP_INT_STATUS);
  66. if (state) {
  67. lima_pp_handle_irq(ip, state);
  68. ret = IRQ_HANDLED;
  69. } else {
  70. if (status & LIMA_PP_STATUS_RENDERING_ACTIVE)
  71. continue;
  72. }
  73. pipe->done |= (1 << i);
  74. if (atomic_dec_and_test(&pipe->task))
  75. lima_sched_pipe_task_done(pipe);
  76. }
  77. return ret;
  78. }
  79. static void lima_pp_soft_reset_async(struct lima_ip *ip)
  80. {
  81. if (ip->data.async_reset)
  82. return;
  83. pp_write(LIMA_PP_INT_MASK, 0);
  84. pp_write(LIMA_PP_INT_RAWSTAT, LIMA_PP_IRQ_MASK_ALL);
  85. pp_write(LIMA_PP_CTRL, LIMA_PP_CTRL_SOFT_RESET);
  86. ip->data.async_reset = true;
  87. }
  88. static int lima_pp_soft_reset_poll(struct lima_ip *ip)
  89. {
  90. return !(pp_read(LIMA_PP_STATUS) & LIMA_PP_STATUS_RENDERING_ACTIVE) &&
  91. pp_read(LIMA_PP_INT_RAWSTAT) == LIMA_PP_IRQ_RESET_COMPLETED;
  92. }
  93. static int lima_pp_soft_reset_async_wait_one(struct lima_ip *ip)
  94. {
  95. struct lima_device *dev = ip->dev;
  96. int ret;
  97. ret = lima_poll_timeout(ip, lima_pp_soft_reset_poll, 0, 100);
  98. if (ret) {
  99. dev_err(dev->dev, "pp %s reset time out\n", lima_ip_name(ip));
  100. return ret;
  101. }
  102. pp_write(LIMA_PP_INT_CLEAR, LIMA_PP_IRQ_MASK_ALL);
  103. pp_write(LIMA_PP_INT_MASK, LIMA_PP_IRQ_MASK_USED);
  104. return 0;
  105. }
  106. static int lima_pp_soft_reset_async_wait(struct lima_ip *ip)
  107. {
  108. int i, err = 0;
  109. if (!ip->data.async_reset)
  110. return 0;
  111. if (ip->id == lima_ip_pp_bcast) {
  112. struct lima_device *dev = ip->dev;
  113. struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
  114. struct drm_lima_m450_pp_frame *frame = pipe->current_task->frame;
  115. for (i = 0; i < frame->num_pp; i++)
  116. err |= lima_pp_soft_reset_async_wait_one(pipe->processor[i]);
  117. } else
  118. err = lima_pp_soft_reset_async_wait_one(ip);
  119. ip->data.async_reset = false;
  120. return err;
  121. }
  122. static void lima_pp_write_frame(struct lima_ip *ip, u32 *frame, u32 *wb)
  123. {
  124. int i, j, n = 0;
  125. for (i = 0; i < LIMA_PP_FRAME_REG_NUM; i++)
  126. writel(frame[i], ip->iomem + LIMA_PP_FRAME + i * 4);
  127. for (i = 0; i < 3; i++) {
  128. for (j = 0; j < LIMA_PP_WB_REG_NUM; j++)
  129. writel(wb[n++], ip->iomem + LIMA_PP_WB(i) + j * 4);
  130. }
  131. }
  132. static int lima_pp_hard_reset_poll(struct lima_ip *ip)
  133. {
  134. pp_write(LIMA_PP_PERF_CNT_0_LIMIT, 0xC01A0000);
  135. return pp_read(LIMA_PP_PERF_CNT_0_LIMIT) == 0xC01A0000;
  136. }
  137. static int lima_pp_hard_reset(struct lima_ip *ip)
  138. {
  139. struct lima_device *dev = ip->dev;
  140. int ret;
  141. pp_write(LIMA_PP_PERF_CNT_0_LIMIT, 0xC0FFE000);
  142. pp_write(LIMA_PP_INT_MASK, 0);
  143. pp_write(LIMA_PP_CTRL, LIMA_PP_CTRL_FORCE_RESET);
  144. ret = lima_poll_timeout(ip, lima_pp_hard_reset_poll, 10, 100);
  145. if (ret) {
  146. dev_err(dev->dev, "pp hard reset timeout\n");
  147. return ret;
  148. }
  149. pp_write(LIMA_PP_PERF_CNT_0_LIMIT, 0);
  150. pp_write(LIMA_PP_INT_CLEAR, LIMA_PP_IRQ_MASK_ALL);
  151. pp_write(LIMA_PP_INT_MASK, LIMA_PP_IRQ_MASK_USED);
  152. return 0;
  153. }
  154. static void lima_pp_print_version(struct lima_ip *ip)
  155. {
  156. u32 version, major, minor;
  157. char *name;
  158. version = pp_read(LIMA_PP_VERSION);
  159. major = (version >> 8) & 0xFF;
  160. minor = version & 0xFF;
  161. switch (version >> 16) {
  162. case 0xC807:
  163. name = "mali200";
  164. break;
  165. case 0xCE07:
  166. name = "mali300";
  167. break;
  168. case 0xCD07:
  169. name = "mali400";
  170. break;
  171. case 0xCF07:
  172. name = "mali450";
  173. break;
  174. default:
  175. name = "unknown";
  176. break;
  177. }
  178. dev_info(ip->dev->dev, "%s - %s version major %d minor %d\n",
  179. lima_ip_name(ip), name, major, minor);
  180. }
  181. static int lima_pp_hw_init(struct lima_ip *ip)
  182. {
  183. ip->data.async_reset = false;
  184. lima_pp_soft_reset_async(ip);
  185. return lima_pp_soft_reset_async_wait(ip);
  186. }
  187. int lima_pp_resume(struct lima_ip *ip)
  188. {
  189. return lima_pp_hw_init(ip);
  190. }
  191. void lima_pp_suspend(struct lima_ip *ip)
  192. {
  193. }
  194. int lima_pp_init(struct lima_ip *ip)
  195. {
  196. struct lima_device *dev = ip->dev;
  197. int err;
  198. lima_pp_print_version(ip);
  199. err = lima_pp_hw_init(ip);
  200. if (err)
  201. return err;
  202. err = devm_request_irq(dev->dev, ip->irq, lima_pp_irq_handler,
  203. IRQF_SHARED, lima_ip_name(ip), ip);
  204. if (err) {
  205. dev_err(dev->dev, "pp %s fail to request irq\n",
  206. lima_ip_name(ip));
  207. return err;
  208. }
  209. dev->pp_version = pp_read(LIMA_PP_VERSION);
  210. return 0;
  211. }
  212. void lima_pp_fini(struct lima_ip *ip)
  213. {
  214. }
  215. int lima_pp_bcast_resume(struct lima_ip *ip)
  216. {
  217. /* PP has been reset by individual PP resume */
  218. ip->data.async_reset = false;
  219. return 0;
  220. }
  221. void lima_pp_bcast_suspend(struct lima_ip *ip)
  222. {
  223. }
  224. int lima_pp_bcast_init(struct lima_ip *ip)
  225. {
  226. struct lima_device *dev = ip->dev;
  227. int err;
  228. err = devm_request_irq(dev->dev, ip->irq, lima_pp_bcast_irq_handler,
  229. IRQF_SHARED, lima_ip_name(ip), ip);
  230. if (err) {
  231. dev_err(dev->dev, "pp %s fail to request irq\n",
  232. lima_ip_name(ip));
  233. return err;
  234. }
  235. return 0;
  236. }
  237. void lima_pp_bcast_fini(struct lima_ip *ip)
  238. {
  239. }
  240. static int lima_pp_task_validate(struct lima_sched_pipe *pipe,
  241. struct lima_sched_task *task)
  242. {
  243. u32 num_pp;
  244. if (pipe->bcast_processor) {
  245. struct drm_lima_m450_pp_frame *f = task->frame;
  246. num_pp = f->num_pp;
  247. if (f->_pad)
  248. return -EINVAL;
  249. } else {
  250. struct drm_lima_m400_pp_frame *f = task->frame;
  251. num_pp = f->num_pp;
  252. }
  253. if (num_pp == 0 || num_pp > pipe->num_processor)
  254. return -EINVAL;
  255. return 0;
  256. }
  257. static void lima_pp_task_run(struct lima_sched_pipe *pipe,
  258. struct lima_sched_task *task)
  259. {
  260. if (pipe->bcast_processor) {
  261. struct drm_lima_m450_pp_frame *frame = task->frame;
  262. struct lima_device *dev = pipe->bcast_processor->dev;
  263. struct lima_ip *ip = pipe->bcast_processor;
  264. int i;
  265. pipe->done = 0;
  266. atomic_set(&pipe->task, frame->num_pp);
  267. if (frame->use_dlbu) {
  268. lima_dlbu_enable(dev, frame->num_pp);
  269. frame->frame[LIMA_PP_FRAME >> 2] = LIMA_VA_RESERVE_DLBU;
  270. lima_dlbu_set_reg(dev->ip + lima_ip_dlbu, frame->dlbu_regs);
  271. } else
  272. lima_dlbu_disable(dev);
  273. lima_bcast_enable(dev, frame->num_pp);
  274. lima_pp_soft_reset_async_wait(ip);
  275. lima_pp_write_frame(ip, frame->frame, frame->wb);
  276. for (i = 0; i < frame->num_pp; i++) {
  277. struct lima_ip *ip = pipe->processor[i];
  278. pp_write(LIMA_PP_STACK, frame->fragment_stack_address[i]);
  279. if (!frame->use_dlbu)
  280. pp_write(LIMA_PP_FRAME, frame->plbu_array_address[i]);
  281. }
  282. pp_write(LIMA_PP_CTRL, LIMA_PP_CTRL_START_RENDERING);
  283. } else {
  284. struct drm_lima_m400_pp_frame *frame = task->frame;
  285. int i;
  286. atomic_set(&pipe->task, frame->num_pp);
  287. for (i = 0; i < frame->num_pp; i++) {
  288. struct lima_ip *ip = pipe->processor[i];
  289. frame->frame[LIMA_PP_FRAME >> 2] =
  290. frame->plbu_array_address[i];
  291. frame->frame[LIMA_PP_STACK >> 2] =
  292. frame->fragment_stack_address[i];
  293. lima_pp_soft_reset_async_wait(ip);
  294. lima_pp_write_frame(ip, frame->frame, frame->wb);
  295. pp_write(LIMA_PP_CTRL, LIMA_PP_CTRL_START_RENDERING);
  296. }
  297. }
  298. }
  299. static void lima_pp_task_fini(struct lima_sched_pipe *pipe)
  300. {
  301. if (pipe->bcast_processor)
  302. lima_pp_soft_reset_async(pipe->bcast_processor);
  303. else {
  304. int i;
  305. for (i = 0; i < pipe->num_processor; i++)
  306. lima_pp_soft_reset_async(pipe->processor[i]);
  307. }
  308. }
  309. static void lima_pp_task_error(struct lima_sched_pipe *pipe)
  310. {
  311. int i;
  312. for (i = 0; i < pipe->num_processor; i++) {
  313. struct lima_ip *ip = pipe->processor[i];
  314. dev_err(ip->dev->dev, "pp task error %d int_state=%x status=%x\n",
  315. i, pp_read(LIMA_PP_INT_STATUS), pp_read(LIMA_PP_STATUS));
  316. lima_pp_hard_reset(ip);
  317. }
  318. }
  319. static void lima_pp_task_mmu_error(struct lima_sched_pipe *pipe)
  320. {
  321. if (atomic_dec_and_test(&pipe->task))
  322. lima_sched_pipe_task_done(pipe);
  323. }
  324. static struct kmem_cache *lima_pp_task_slab;
  325. static int lima_pp_task_slab_refcnt;
  326. int lima_pp_pipe_init(struct lima_device *dev)
  327. {
  328. int frame_size;
  329. struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
  330. if (dev->id == lima_gpu_mali400)
  331. frame_size = sizeof(struct drm_lima_m400_pp_frame);
  332. else
  333. frame_size = sizeof(struct drm_lima_m450_pp_frame);
  334. if (!lima_pp_task_slab) {
  335. lima_pp_task_slab = kmem_cache_create_usercopy(
  336. "lima_pp_task", sizeof(struct lima_sched_task) + frame_size,
  337. 0, SLAB_HWCACHE_ALIGN, sizeof(struct lima_sched_task),
  338. frame_size, NULL);
  339. if (!lima_pp_task_slab)
  340. return -ENOMEM;
  341. }
  342. lima_pp_task_slab_refcnt++;
  343. pipe->frame_size = frame_size;
  344. pipe->task_slab = lima_pp_task_slab;
  345. pipe->task_validate = lima_pp_task_validate;
  346. pipe->task_run = lima_pp_task_run;
  347. pipe->task_fini = lima_pp_task_fini;
  348. pipe->task_error = lima_pp_task_error;
  349. pipe->task_mmu_error = lima_pp_task_mmu_error;
  350. return 0;
  351. }
  352. void lima_pp_pipe_fini(struct lima_device *dev)
  353. {
  354. if (!--lima_pp_task_slab_refcnt) {
  355. kmem_cache_destroy(lima_pp_task_slab);
  356. lima_pp_task_slab = NULL;
  357. }
  358. }