i915_pmu.h 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165
  1. /*
  2. * SPDX-License-Identifier: MIT
  3. *
  4. * Copyright © 2017-2018 Intel Corporation
  5. */
  6. #ifndef __I915_PMU_H__
  7. #define __I915_PMU_H__
  8. #include <linux/hrtimer.h>
  9. #include <linux/perf_event.h>
  10. #include <linux/spinlock_types.h>
  11. #include <uapi/drm/i915_drm.h>
  12. struct drm_i915_private;
  13. /**
  14. * Non-engine events that we need to track enabled-disabled transition and
  15. * current state.
  16. */
  17. enum i915_pmu_tracked_events {
  18. __I915_PMU_ACTUAL_FREQUENCY_ENABLED = 0,
  19. __I915_PMU_REQUESTED_FREQUENCY_ENABLED,
  20. __I915_PMU_RC6_RESIDENCY_ENABLED,
  21. __I915_PMU_TRACKED_EVENT_COUNT, /* count marker */
  22. };
  23. /**
  24. * Slots used from the sampling timer (non-engine events) with some extras for
  25. * convenience.
  26. */
  27. enum {
  28. __I915_SAMPLE_FREQ_ACT = 0,
  29. __I915_SAMPLE_FREQ_REQ,
  30. __I915_SAMPLE_RC6,
  31. __I915_SAMPLE_RC6_LAST_REPORTED,
  32. __I915_NUM_PMU_SAMPLERS
  33. };
  34. /**
  35. * How many different events we track in the global PMU mask.
  36. *
  37. * It is also used to know to needed number of event reference counters.
  38. */
  39. #define I915_PMU_MASK_BITS \
  40. (I915_ENGINE_SAMPLE_COUNT + __I915_PMU_TRACKED_EVENT_COUNT)
  41. #define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
  42. struct i915_pmu_sample {
  43. u64 cur;
  44. };
  45. struct i915_pmu {
  46. /**
  47. * @cpuhp: Struct used for CPU hotplug handling.
  48. */
  49. struct {
  50. struct hlist_node node;
  51. unsigned int cpu;
  52. } cpuhp;
  53. /**
  54. * @base: PMU base.
  55. */
  56. struct pmu base;
  57. /**
  58. * @closed: i915 is unregistering.
  59. */
  60. bool closed;
  61. /**
  62. * @name: Name as registered with perf core.
  63. */
  64. const char *name;
  65. /**
  66. * @lock: Lock protecting enable mask and ref count handling.
  67. */
  68. spinlock_t lock;
  69. /**
  70. * @timer: Timer for internal i915 PMU sampling.
  71. */
  72. struct hrtimer timer;
  73. /**
  74. * @enable: Bitmask of specific enabled events.
  75. *
  76. * For some events we need to track their state and do some internal
  77. * house keeping.
  78. *
  79. * Each engine event sampler type and event listed in enum
  80. * i915_pmu_tracked_events gets a bit in this field.
  81. *
  82. * Low bits are engine samplers and other events continue from there.
  83. */
  84. u32 enable;
  85. /**
  86. * @timer_last:
  87. *
  88. * Timestmap of the previous timer invocation.
  89. */
  90. ktime_t timer_last;
  91. /**
  92. * @enable_count: Reference counts for the enabled events.
  93. *
  94. * Array indices are mapped in the same way as bits in the @enable field
  95. * and they are used to control sampling on/off when multiple clients
  96. * are using the PMU API.
  97. */
  98. unsigned int enable_count[I915_PMU_MASK_BITS];
  99. /**
  100. * @timer_enabled: Should the internal sampling timer be running.
  101. */
  102. bool timer_enabled;
  103. /**
  104. * @sample: Current and previous (raw) counters for sampling events.
  105. *
  106. * These counters are updated from the i915 PMU sampling timer.
  107. *
  108. * Only global counters are held here, while the per-engine ones are in
  109. * struct intel_engine_cs.
  110. */
  111. struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
  112. /**
  113. * @sleep_last: Last time GT parked for RC6 estimation.
  114. */
  115. ktime_t sleep_last;
  116. /**
  117. * @irq_count: Number of interrupts
  118. *
  119. * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
  120. * 4e9 interrupts are a lot and postprocessing can really deal with an
  121. * occasional wraparound easily. It's 32bit after all.
  122. */
  123. unsigned long irq_count;
  124. /**
  125. * @events_attr_group: Device events attribute group.
  126. */
  127. struct attribute_group events_attr_group;
  128. /**
  129. * @i915_attr: Memory block holding device attributes.
  130. */
  131. void *i915_attr;
  132. /**
  133. * @pmu_attr: Memory block holding device attributes.
  134. */
  135. void *pmu_attr;
  136. };
  137. #ifdef CONFIG_PERF_EVENTS
  138. int i915_pmu_init(void);
  139. void i915_pmu_exit(void);
  140. void i915_pmu_register(struct drm_i915_private *i915);
  141. void i915_pmu_unregister(struct drm_i915_private *i915);
  142. void i915_pmu_gt_parked(struct drm_i915_private *i915);
  143. void i915_pmu_gt_unparked(struct drm_i915_private *i915);
  144. #else
  145. static inline int i915_pmu_init(void) { return 0; }
  146. static inline void i915_pmu_exit(void) {}
  147. static inline void i915_pmu_register(struct drm_i915_private *i915) {}
  148. static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
  149. static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
  150. static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
  151. #endif
  152. #endif