oaktrail_lvds.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright © 2006-2009 Intel Corporation
  4. *
  5. * Authors:
  6. * Eric Anholt <[email protected]>
  7. * Dave Airlie <[email protected]>
  8. * Jesse Barnes <[email protected]>
  9. */
  10. #include <linux/i2c.h>
  11. #include <linux/pm_runtime.h>
  12. #include <asm/intel-mid.h>
  13. #include <drm/drm_edid.h>
  14. #include <drm/drm_simple_kms_helper.h>
  15. #include "intel_bios.h"
  16. #include "power.h"
  17. #include "psb_drv.h"
  18. #include "psb_intel_drv.h"
  19. #include "psb_intel_reg.h"
  20. /* The max/min PWM frequency in BPCR[31:17] - */
  21. /* The smallest number is 1 (not 0) that can fit in the
  22. * 15-bit field of the and then*/
  23. /* shifts to the left by one bit to get the actual 16-bit
  24. * value that the 15-bits correspond to.*/
  25. #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
  26. #define BRIGHTNESS_MAX_LEVEL 100
  27. /*
  28. * Sets the power state for the panel.
  29. */
  30. static void oaktrail_lvds_set_power(struct drm_device *dev,
  31. struct gma_encoder *gma_encoder,
  32. bool on)
  33. {
  34. u32 pp_status;
  35. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  36. if (!gma_power_begin(dev, true))
  37. return;
  38. if (on) {
  39. REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
  40. POWER_TARGET_ON);
  41. do {
  42. pp_status = REG_READ(PP_STATUS);
  43. } while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
  44. dev_priv->is_lvds_on = true;
  45. if (dev_priv->ops->lvds_bl_power)
  46. dev_priv->ops->lvds_bl_power(dev, true);
  47. } else {
  48. if (dev_priv->ops->lvds_bl_power)
  49. dev_priv->ops->lvds_bl_power(dev, false);
  50. REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
  51. ~POWER_TARGET_ON);
  52. do {
  53. pp_status = REG_READ(PP_STATUS);
  54. } while (pp_status & PP_ON);
  55. dev_priv->is_lvds_on = false;
  56. }
  57. gma_power_end(dev);
  58. }
  59. static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode)
  60. {
  61. struct drm_device *dev = encoder->dev;
  62. struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
  63. if (mode == DRM_MODE_DPMS_ON)
  64. oaktrail_lvds_set_power(dev, gma_encoder, true);
  65. else
  66. oaktrail_lvds_set_power(dev, gma_encoder, false);
  67. /* XXX: We never power down the LVDS pairs. */
  68. }
  69. static void oaktrail_lvds_mode_set(struct drm_encoder *encoder,
  70. struct drm_display_mode *mode,
  71. struct drm_display_mode *adjusted_mode)
  72. {
  73. struct drm_device *dev = encoder->dev;
  74. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  75. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  76. struct drm_connector_list_iter conn_iter;
  77. struct drm_connector *connector = NULL;
  78. struct drm_crtc *crtc = encoder->crtc;
  79. u32 lvds_port;
  80. uint64_t v = DRM_MODE_SCALE_FULLSCREEN;
  81. if (!gma_power_begin(dev, true))
  82. return;
  83. /*
  84. * The LVDS pin pair will already have been turned on in the
  85. * psb_intel_crtc_mode_set since it has a large impact on the DPLL
  86. * settings.
  87. */
  88. lvds_port = (REG_READ(LVDS) &
  89. (~LVDS_PIPEB_SELECT)) |
  90. LVDS_PORT_EN |
  91. LVDS_BORDER_EN;
  92. /* If the firmware says dither on Moorestown, or the BIOS does
  93. on Oaktrail then enable dithering */
  94. if (mode_dev->panel_wants_dither || dev_priv->lvds_dither)
  95. lvds_port |= MRST_PANEL_8TO6_DITHER_ENABLE;
  96. REG_WRITE(LVDS, lvds_port);
  97. /* Find the connector we're trying to set up */
  98. drm_connector_list_iter_begin(dev, &conn_iter);
  99. drm_for_each_connector_iter(connector, &conn_iter) {
  100. if (connector->encoder && connector->encoder->crtc == crtc)
  101. break;
  102. }
  103. if (!connector) {
  104. drm_connector_list_iter_end(&conn_iter);
  105. DRM_ERROR("Couldn't find connector when setting mode");
  106. gma_power_end(dev);
  107. return;
  108. }
  109. drm_object_property_get_value( &connector->base,
  110. dev->mode_config.scaling_mode_property, &v);
  111. drm_connector_list_iter_end(&conn_iter);
  112. if (v == DRM_MODE_SCALE_NO_SCALE)
  113. REG_WRITE(PFIT_CONTROL, 0);
  114. else if (v == DRM_MODE_SCALE_ASPECT) {
  115. if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) ||
  116. (mode->hdisplay != adjusted_mode->crtc_hdisplay)) {
  117. if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) ==
  118. (mode->hdisplay * adjusted_mode->crtc_vdisplay))
  119. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
  120. else if ((adjusted_mode->crtc_hdisplay *
  121. mode->vdisplay) > (mode->hdisplay *
  122. adjusted_mode->crtc_vdisplay))
  123. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
  124. PFIT_SCALING_MODE_PILLARBOX);
  125. else
  126. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
  127. PFIT_SCALING_MODE_LETTERBOX);
  128. } else
  129. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
  130. } else /*(v == DRM_MODE_SCALE_FULLSCREEN)*/
  131. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
  132. gma_power_end(dev);
  133. }
  134. static void oaktrail_lvds_prepare(struct drm_encoder *encoder)
  135. {
  136. struct drm_device *dev = encoder->dev;
  137. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  138. struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
  139. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  140. if (!gma_power_begin(dev, true))
  141. return;
  142. mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
  143. mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL &
  144. BACKLIGHT_DUTY_CYCLE_MASK);
  145. oaktrail_lvds_set_power(dev, gma_encoder, false);
  146. gma_power_end(dev);
  147. }
  148. static u32 oaktrail_lvds_get_max_backlight(struct drm_device *dev)
  149. {
  150. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  151. u32 ret;
  152. if (gma_power_begin(dev, false)) {
  153. ret = ((REG_READ(BLC_PWM_CTL) &
  154. BACKLIGHT_MODULATION_FREQ_MASK) >>
  155. BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
  156. gma_power_end(dev);
  157. } else
  158. ret = ((dev_priv->regs.saveBLC_PWM_CTL &
  159. BACKLIGHT_MODULATION_FREQ_MASK) >>
  160. BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
  161. return ret;
  162. }
  163. static void oaktrail_lvds_commit(struct drm_encoder *encoder)
  164. {
  165. struct drm_device *dev = encoder->dev;
  166. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  167. struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
  168. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  169. if (mode_dev->backlight_duty_cycle == 0)
  170. mode_dev->backlight_duty_cycle =
  171. oaktrail_lvds_get_max_backlight(dev);
  172. oaktrail_lvds_set_power(dev, gma_encoder, true);
  173. }
  174. static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = {
  175. .dpms = oaktrail_lvds_dpms,
  176. .mode_fixup = psb_intel_lvds_mode_fixup,
  177. .prepare = oaktrail_lvds_prepare,
  178. .mode_set = oaktrail_lvds_mode_set,
  179. .commit = oaktrail_lvds_commit,
  180. };
  181. /* Returns the panel fixed mode from configuration. */
  182. static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev,
  183. struct psb_intel_mode_device *mode_dev)
  184. {
  185. struct drm_display_mode *mode = NULL;
  186. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  187. struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;
  188. mode_dev->panel_fixed_mode = NULL;
  189. /* Use the firmware provided data on Moorestown */
  190. if (dev_priv->has_gct) {
  191. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  192. if (!mode)
  193. return;
  194. mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
  195. mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
  196. mode->hsync_start = mode->hdisplay + \
  197. ((ti->hsync_offset_hi << 8) | \
  198. ti->hsync_offset_lo);
  199. mode->hsync_end = mode->hsync_start + \
  200. ((ti->hsync_pulse_width_hi << 8) | \
  201. ti->hsync_pulse_width_lo);
  202. mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
  203. ti->hblank_lo);
  204. mode->vsync_start = \
  205. mode->vdisplay + ((ti->vsync_offset_hi << 4) | \
  206. ti->vsync_offset_lo);
  207. mode->vsync_end = \
  208. mode->vsync_start + ((ti->vsync_pulse_width_hi << 4) | \
  209. ti->vsync_pulse_width_lo);
  210. mode->vtotal = mode->vdisplay + \
  211. ((ti->vblank_hi << 8) | ti->vblank_lo);
  212. mode->clock = ti->pixel_clock * 10;
  213. #if 0
  214. pr_info("hdisplay is %d\n", mode->hdisplay);
  215. pr_info("vdisplay is %d\n", mode->vdisplay);
  216. pr_info("HSS is %d\n", mode->hsync_start);
  217. pr_info("HSE is %d\n", mode->hsync_end);
  218. pr_info("htotal is %d\n", mode->htotal);
  219. pr_info("VSS is %d\n", mode->vsync_start);
  220. pr_info("VSE is %d\n", mode->vsync_end);
  221. pr_info("vtotal is %d\n", mode->vtotal);
  222. pr_info("clock is %d\n", mode->clock);
  223. #endif
  224. mode_dev->panel_fixed_mode = mode;
  225. }
  226. /* Use the BIOS VBT mode if available */
  227. if (mode_dev->panel_fixed_mode == NULL && mode_dev->vbt_mode)
  228. mode_dev->panel_fixed_mode = drm_mode_duplicate(dev,
  229. mode_dev->vbt_mode);
  230. /* Then try the LVDS VBT mode */
  231. if (mode_dev->panel_fixed_mode == NULL)
  232. if (dev_priv->lfp_lvds_vbt_mode)
  233. mode_dev->panel_fixed_mode =
  234. drm_mode_duplicate(dev,
  235. dev_priv->lfp_lvds_vbt_mode);
  236. /* If we still got no mode then bail */
  237. if (mode_dev->panel_fixed_mode == NULL)
  238. return;
  239. drm_mode_set_name(mode_dev->panel_fixed_mode);
  240. drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0);
  241. }
  242. /**
  243. * oaktrail_lvds_init - setup LVDS connectors on this device
  244. * @dev: drm device
  245. * @mode_dev: PSB mode device
  246. *
  247. * Create the connector, register the LVDS DDC bus, and try to figure out what
  248. * modes we can display on the LVDS panel (if present).
  249. */
  250. void oaktrail_lvds_init(struct drm_device *dev,
  251. struct psb_intel_mode_device *mode_dev)
  252. {
  253. struct gma_encoder *gma_encoder;
  254. struct gma_connector *gma_connector;
  255. struct gma_i2c_chan *ddc_bus;
  256. struct drm_connector *connector;
  257. struct drm_encoder *encoder;
  258. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  259. struct edid *edid;
  260. struct i2c_adapter *i2c_adap;
  261. struct drm_display_mode *scan; /* *modes, *bios_mode; */
  262. int ret;
  263. gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
  264. if (!gma_encoder)
  265. return;
  266. gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
  267. if (!gma_connector)
  268. goto err_free_encoder;
  269. connector = &gma_connector->base;
  270. encoder = &gma_encoder->base;
  271. dev_priv->is_lvds_on = true;
  272. ret = drm_connector_init(dev, connector,
  273. &psb_intel_lvds_connector_funcs,
  274. DRM_MODE_CONNECTOR_LVDS);
  275. if (ret)
  276. goto err_free_connector;
  277. ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_LVDS);
  278. if (ret)
  279. goto err_connector_cleanup;
  280. gma_connector_attach_encoder(gma_connector, gma_encoder);
  281. gma_encoder->type = INTEL_OUTPUT_LVDS;
  282. drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs);
  283. drm_connector_helper_add(connector,
  284. &psb_intel_lvds_connector_helper_funcs);
  285. connector->display_info.subpixel_order = SubPixelHorizontalRGB;
  286. connector->interlace_allowed = false;
  287. connector->doublescan_allowed = false;
  288. drm_object_attach_property(&connector->base,
  289. dev->mode_config.scaling_mode_property,
  290. DRM_MODE_SCALE_FULLSCREEN);
  291. drm_object_attach_property(&connector->base,
  292. dev_priv->backlight_property,
  293. BRIGHTNESS_MAX_LEVEL);
  294. mode_dev->panel_wants_dither = false;
  295. if (dev_priv->has_gct)
  296. mode_dev->panel_wants_dither = (dev_priv->gct_data.
  297. Panel_Port_Control & MRST_PANEL_8TO6_DITHER_ENABLE);
  298. if (dev_priv->lvds_dither)
  299. mode_dev->panel_wants_dither = 1;
  300. /*
  301. * LVDS discovery:
  302. * 1) check for EDID on DDC
  303. * 2) check for VBT data
  304. * 3) check to see if LVDS is already on
  305. * if none of the above, no panel
  306. * 4) make sure lid is open
  307. * if closed, act like it's not there for now
  308. */
  309. edid = NULL;
  310. mutex_lock(&dev->mode_config.mutex);
  311. i2c_adap = i2c_get_adapter(dev_priv->ops->i2c_bus);
  312. if (i2c_adap)
  313. edid = drm_get_edid(connector, i2c_adap);
  314. if (edid == NULL && dev_priv->lpc_gpio_base) {
  315. ddc_bus = oaktrail_lvds_i2c_init(dev);
  316. if (!IS_ERR(ddc_bus)) {
  317. i2c_adap = &ddc_bus->base;
  318. edid = drm_get_edid(connector, i2c_adap);
  319. }
  320. }
  321. /*
  322. * Due to the logic in probing for i2c buses above we do not know the
  323. * i2c_adap until now. Hence we cannot use drm_connector_init_with_ddc()
  324. * but must instead set connector->ddc manually here.
  325. */
  326. connector->ddc = i2c_adap;
  327. /*
  328. * Attempt to get the fixed panel mode from DDC. Assume that the
  329. * preferred mode is the right one.
  330. */
  331. if (edid) {
  332. drm_connector_update_edid_property(connector, edid);
  333. drm_add_edid_modes(connector, edid);
  334. kfree(edid);
  335. list_for_each_entry(scan, &connector->probed_modes, head) {
  336. if (scan->type & DRM_MODE_TYPE_PREFERRED) {
  337. mode_dev->panel_fixed_mode =
  338. drm_mode_duplicate(dev, scan);
  339. goto out; /* FIXME: check for quirks */
  340. }
  341. }
  342. } else
  343. dev_err(dev->dev, "No ddc adapter available!\n");
  344. /*
  345. * If we didn't get EDID, try geting panel timing
  346. * from configuration data
  347. */
  348. oaktrail_lvds_get_configuration_mode(dev, mode_dev);
  349. if (mode_dev->panel_fixed_mode) {
  350. mode_dev->panel_fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
  351. goto out; /* FIXME: check for quirks */
  352. }
  353. /* If we still don't have a mode after all that, give up. */
  354. if (!mode_dev->panel_fixed_mode) {
  355. dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n");
  356. goto err_unlock;
  357. }
  358. out:
  359. mutex_unlock(&dev->mode_config.mutex);
  360. return;
  361. err_unlock:
  362. mutex_unlock(&dev->mode_config.mutex);
  363. gma_i2c_destroy(to_gma_i2c_chan(connector->ddc));
  364. drm_encoder_cleanup(encoder);
  365. err_connector_cleanup:
  366. drm_connector_cleanup(connector);
  367. err_free_connector:
  368. kfree(gma_connector);
  369. err_free_encoder:
  370. kfree(gma_encoder);
  371. }