ast_drv.h 13 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the
  6. * "Software"), to deal in the Software without restriction, including
  7. * without limitation the rights to use, copy, modify, merge, publish,
  8. * distribute, sub license, and/or sell copies of the Software, and to
  9. * permit persons to whom the Software is furnished to do so, subject to
  10. * the following conditions:
  11. *
  12. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  15. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  16. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  17. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  18. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  19. *
  20. * The above copyright notice and this permission notice (including the
  21. * next paragraph) shall be included in all copies or substantial portions
  22. * of the Software.
  23. *
  24. */
  25. /*
  26. * Authors: Dave Airlie <[email protected]>
  27. */
  28. #ifndef __AST_DRV_H__
  29. #define __AST_DRV_H__
  30. #include <linux/i2c.h>
  31. #include <linux/i2c-algo-bit.h>
  32. #include <linux/io.h>
  33. #include <linux/types.h>
  34. #include <drm/drm_connector.h>
  35. #include <drm/drm_crtc.h>
  36. #include <drm/drm_encoder.h>
  37. #include <drm/drm_mode.h>
  38. #include <drm/drm_framebuffer.h>
  39. #include <drm/drm_fb_helper.h>
  40. #define DRIVER_AUTHOR "Dave Airlie"
  41. #define DRIVER_NAME "ast"
  42. #define DRIVER_DESC "AST"
  43. #define DRIVER_DATE "20120228"
  44. #define DRIVER_MAJOR 0
  45. #define DRIVER_MINOR 1
  46. #define DRIVER_PATCHLEVEL 0
  47. #define PCI_CHIP_AST2000 0x2000
  48. #define PCI_CHIP_AST2100 0x2010
  49. enum ast_chip {
  50. AST2000,
  51. AST2100,
  52. AST1100,
  53. AST2200,
  54. AST2150,
  55. AST2300,
  56. AST2400,
  57. AST2500,
  58. AST2600,
  59. };
  60. enum ast_tx_chip {
  61. AST_TX_NONE,
  62. AST_TX_SIL164,
  63. AST_TX_DP501,
  64. AST_TX_ASTDP,
  65. };
  66. #define AST_TX_NONE_BIT BIT(AST_TX_NONE)
  67. #define AST_TX_SIL164_BIT BIT(AST_TX_SIL164)
  68. #define AST_TX_DP501_BIT BIT(AST_TX_DP501)
  69. #define AST_TX_ASTDP_BIT BIT(AST_TX_ASTDP)
  70. #define AST_DRAM_512Mx16 0
  71. #define AST_DRAM_1Gx16 1
  72. #define AST_DRAM_512Mx32 2
  73. #define AST_DRAM_1Gx32 3
  74. #define AST_DRAM_2Gx16 6
  75. #define AST_DRAM_4Gx16 7
  76. #define AST_DRAM_8Gx16 8
  77. /*
  78. * Cursor plane
  79. */
  80. #define AST_MAX_HWC_WIDTH 64
  81. #define AST_MAX_HWC_HEIGHT 64
  82. #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
  83. #define AST_HWC_SIGNATURE_SIZE 32
  84. #define AST_DEFAULT_HWC_NUM 2
  85. /* define for signature structure */
  86. #define AST_HWC_SIGNATURE_CHECKSUM 0x00
  87. #define AST_HWC_SIGNATURE_SizeX 0x04
  88. #define AST_HWC_SIGNATURE_SizeY 0x08
  89. #define AST_HWC_SIGNATURE_X 0x0C
  90. #define AST_HWC_SIGNATURE_Y 0x10
  91. #define AST_HWC_SIGNATURE_HOTSPOTX 0x14
  92. #define AST_HWC_SIGNATURE_HOTSPOTY 0x18
  93. struct ast_cursor_plane {
  94. struct drm_plane base;
  95. struct {
  96. struct drm_gem_vram_object *gbo;
  97. struct iosys_map map;
  98. u64 off;
  99. } hwc[AST_DEFAULT_HWC_NUM];
  100. unsigned int next_hwc_index;
  101. };
  102. static inline struct ast_cursor_plane *
  103. to_ast_cursor_plane(struct drm_plane *plane)
  104. {
  105. return container_of(plane, struct ast_cursor_plane, base);
  106. }
  107. /*
  108. * Connector with i2c channel
  109. */
  110. struct ast_i2c_chan {
  111. struct i2c_adapter adapter;
  112. struct drm_device *dev;
  113. struct i2c_algo_bit_data bit;
  114. };
  115. struct ast_vga_connector {
  116. struct drm_connector base;
  117. struct ast_i2c_chan *i2c;
  118. };
  119. static inline struct ast_vga_connector *
  120. to_ast_vga_connector(struct drm_connector *connector)
  121. {
  122. return container_of(connector, struct ast_vga_connector, base);
  123. }
  124. struct ast_sil164_connector {
  125. struct drm_connector base;
  126. struct ast_i2c_chan *i2c;
  127. };
  128. static inline struct ast_sil164_connector *
  129. to_ast_sil164_connector(struct drm_connector *connector)
  130. {
  131. return container_of(connector, struct ast_sil164_connector, base);
  132. }
  133. /*
  134. * Device
  135. */
  136. struct ast_private {
  137. struct drm_device base;
  138. struct mutex ioregs_lock; /* Protects access to I/O registers in ioregs */
  139. void __iomem *regs;
  140. void __iomem *ioregs;
  141. void __iomem *dp501_fw_buf;
  142. enum ast_chip chip;
  143. bool vga2_clone;
  144. uint32_t dram_bus_width;
  145. uint32_t dram_type;
  146. uint32_t mclk;
  147. struct drm_plane primary_plane;
  148. struct ast_cursor_plane cursor_plane;
  149. struct drm_crtc crtc;
  150. struct {
  151. struct {
  152. struct drm_encoder encoder;
  153. struct ast_vga_connector vga_connector;
  154. } vga;
  155. struct {
  156. struct drm_encoder encoder;
  157. struct ast_sil164_connector sil164_connector;
  158. } sil164;
  159. struct {
  160. struct drm_encoder encoder;
  161. struct drm_connector connector;
  162. } dp501;
  163. struct {
  164. struct drm_encoder encoder;
  165. struct drm_connector connector;
  166. } astdp;
  167. } output;
  168. bool support_wide_screen;
  169. enum {
  170. ast_use_p2a,
  171. ast_use_dt,
  172. ast_use_defaults
  173. } config_mode;
  174. unsigned long tx_chip_types; /* bitfield of enum ast_chip_type */
  175. u8 *dp501_fw_addr;
  176. const struct firmware *dp501_fw; /* dp501 fw */
  177. };
  178. static inline struct ast_private *to_ast_private(struct drm_device *dev)
  179. {
  180. return container_of(dev, struct ast_private, base);
  181. }
  182. struct ast_private *ast_device_create(const struct drm_driver *drv,
  183. struct pci_dev *pdev,
  184. unsigned long flags);
  185. #define AST_IO_AR_PORT_WRITE (0x40)
  186. #define AST_IO_MISC_PORT_WRITE (0x42)
  187. #define AST_IO_VGA_ENABLE_PORT (0x43)
  188. #define AST_IO_SEQ_PORT (0x44)
  189. #define AST_IO_DAC_INDEX_READ (0x47)
  190. #define AST_IO_DAC_INDEX_WRITE (0x48)
  191. #define AST_IO_DAC_DATA (0x49)
  192. #define AST_IO_GR_PORT (0x4E)
  193. #define AST_IO_CRTC_PORT (0x54)
  194. #define AST_IO_INPUT_STATUS1_READ (0x5A)
  195. #define AST_IO_MISC_PORT_READ (0x4C)
  196. #define AST_IO_MM_OFFSET (0x380)
  197. #define AST_IO_VGAIR1_VREFRESH BIT(3)
  198. #define AST_IO_VGACRCB_HWC_ENABLED BIT(1)
  199. #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
  200. #define __ast_read(x) \
  201. static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
  202. u##x val = 0;\
  203. val = ioread##x(ast->regs + reg); \
  204. return val;\
  205. }
  206. __ast_read(8);
  207. __ast_read(16);
  208. __ast_read(32)
  209. #define __ast_io_read(x) \
  210. static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
  211. u##x val = 0;\
  212. val = ioread##x(ast->ioregs + reg); \
  213. return val;\
  214. }
  215. __ast_io_read(8);
  216. __ast_io_read(16);
  217. __ast_io_read(32);
  218. #define __ast_write(x) \
  219. static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
  220. iowrite##x(val, ast->regs + reg);\
  221. }
  222. __ast_write(8);
  223. __ast_write(16);
  224. __ast_write(32);
  225. #define __ast_io_write(x) \
  226. static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
  227. iowrite##x(val, ast->ioregs + reg);\
  228. }
  229. __ast_io_write(8);
  230. __ast_io_write(16);
  231. #undef __ast_io_write
  232. static inline void ast_set_index_reg(struct ast_private *ast,
  233. uint32_t base, uint8_t index,
  234. uint8_t val)
  235. {
  236. ast_io_write16(ast, base, ((u16)val << 8) | index);
  237. }
  238. void ast_set_index_reg_mask(struct ast_private *ast,
  239. uint32_t base, uint8_t index,
  240. uint8_t mask, uint8_t val);
  241. uint8_t ast_get_index_reg(struct ast_private *ast,
  242. uint32_t base, uint8_t index);
  243. uint8_t ast_get_index_reg_mask(struct ast_private *ast,
  244. uint32_t base, uint8_t index, uint8_t mask);
  245. static inline void ast_open_key(struct ast_private *ast)
  246. {
  247. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
  248. }
  249. #define AST_VIDMEM_SIZE_8M 0x00800000
  250. #define AST_VIDMEM_SIZE_16M 0x01000000
  251. #define AST_VIDMEM_SIZE_32M 0x02000000
  252. #define AST_VIDMEM_SIZE_64M 0x04000000
  253. #define AST_VIDMEM_SIZE_128M 0x08000000
  254. #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
  255. struct ast_vbios_stdtable {
  256. u8 misc;
  257. u8 seq[4];
  258. u8 crtc[25];
  259. u8 ar[20];
  260. u8 gr[9];
  261. };
  262. struct ast_vbios_enhtable {
  263. u32 ht;
  264. u32 hde;
  265. u32 hfp;
  266. u32 hsync;
  267. u32 vt;
  268. u32 vde;
  269. u32 vfp;
  270. u32 vsync;
  271. u32 dclk_index;
  272. u32 flags;
  273. u32 refresh_rate;
  274. u32 refresh_rate_index;
  275. u32 mode_id;
  276. };
  277. struct ast_vbios_dclk_info {
  278. u8 param1;
  279. u8 param2;
  280. u8 param3;
  281. };
  282. struct ast_vbios_mode_info {
  283. const struct ast_vbios_stdtable *std_table;
  284. const struct ast_vbios_enhtable *enh_table;
  285. };
  286. struct ast_crtc_state {
  287. struct drm_crtc_state base;
  288. /* Last known format of primary plane */
  289. const struct drm_format_info *format;
  290. struct ast_vbios_mode_info vbios_mode_info;
  291. };
  292. #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
  293. int ast_mode_config_init(struct ast_private *ast);
  294. #define AST_MM_ALIGN_SHIFT 4
  295. #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
  296. #define AST_DP501_FW_VERSION_MASK GENMASK(7, 4)
  297. #define AST_DP501_FW_VERSION_1 BIT(4)
  298. #define AST_DP501_PNP_CONNECTED BIT(1)
  299. #define AST_DP501_DEFAULT_DCLK 65
  300. #define AST_DP501_GBL_VERSION 0xf000
  301. #define AST_DP501_PNPMONITOR 0xf010
  302. #define AST_DP501_LINKRATE 0xf014
  303. #define AST_DP501_EDID_DATA 0xf020
  304. /* Define for Soc scratched reg */
  305. #define COPROCESSOR_LAUNCH BIT(5)
  306. /*
  307. * Display Transmitter Type:
  308. */
  309. #define TX_TYPE_MASK GENMASK(3, 1)
  310. #define NO_TX (0 << 1)
  311. #define ITE66121_VBIOS_TX (1 << 1)
  312. #define SI164_VBIOS_TX (2 << 1)
  313. #define CH7003_VBIOS_TX (3 << 1)
  314. #define DP501_VBIOS_TX (4 << 1)
  315. #define ANX9807_VBIOS_TX (5 << 1)
  316. #define TX_FW_EMBEDDED_FW_TX (6 << 1)
  317. #define ASTDP_DPMCU_TX (7 << 1)
  318. #define AST_VRAM_INIT_STATUS_MASK GENMASK(7, 6)
  319. //#define AST_VRAM_INIT_BY_BMC BIT(7)
  320. //#define AST_VRAM_INIT_READY BIT(6)
  321. /* Define for Soc scratched reg used on ASTDP */
  322. #define AST_DP_PHY_SLEEP BIT(4)
  323. #define AST_DP_VIDEO_ENABLE BIT(0)
  324. #define AST_DP_POWER_ON true
  325. #define AST_DP_POWER_OFF false
  326. /*
  327. * CRD1[b5]: DP MCU FW is executing
  328. * CRDC[b0]: DP link success
  329. * CRDF[b0]: DP HPD
  330. * CRE5[b0]: Host reading EDID process is done
  331. */
  332. #define ASTDP_MCU_FW_EXECUTING BIT(5)
  333. #define ASTDP_LINK_SUCCESS BIT(0)
  334. #define ASTDP_HPD BIT(0)
  335. #define ASTDP_HOST_EDID_READ_DONE BIT(0)
  336. #define ASTDP_HOST_EDID_READ_DONE_MASK GENMASK(0, 0)
  337. /*
  338. * CRB8[b1]: Enable VSYNC off
  339. * CRB8[b0]: Enable HSYNC off
  340. */
  341. #define AST_DPMS_VSYNC_OFF BIT(1)
  342. #define AST_DPMS_HSYNC_OFF BIT(0)
  343. /*
  344. * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE
  345. * Precondition: A. ~AST_DP_PHY_SLEEP &&
  346. * B. DP_HPD &&
  347. * C. DP_LINK_SUCCESS
  348. */
  349. #define ASTDP_MIRROR_VIDEO_ENABLE BIT(4)
  350. #define ASTDP_EDID_READ_POINTER_MASK GENMASK(7, 0)
  351. #define ASTDP_EDID_VALID_FLAG_MASK GENMASK(0, 0)
  352. #define ASTDP_EDID_READ_DATA_MASK GENMASK(7, 0)
  353. /*
  354. * ASTDP setmode registers:
  355. * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
  356. * CRE1[7:0]: MISC1 (default: 0x00)
  357. * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50)
  358. */
  359. #define ASTDP_MISC0_24bpp BIT(5)
  360. #define ASTDP_MISC1 0
  361. #define ASTDP_AND_CLEAR_MASK 0x00
  362. /*
  363. * ASTDP resoultion table:
  364. * EX: ASTDP_A_B_C:
  365. * A: Resolution
  366. * B: Refresh Rate
  367. * C: Misc information, such as CVT, Reduce Blanked
  368. */
  369. #define ASTDP_640x480_60 0x00
  370. #define ASTDP_640x480_72 0x01
  371. #define ASTDP_640x480_75 0x02
  372. #define ASTDP_640x480_85 0x03
  373. #define ASTDP_800x600_56 0x04
  374. #define ASTDP_800x600_60 0x05
  375. #define ASTDP_800x600_72 0x06
  376. #define ASTDP_800x600_75 0x07
  377. #define ASTDP_800x600_85 0x08
  378. #define ASTDP_1024x768_60 0x09
  379. #define ASTDP_1024x768_70 0x0A
  380. #define ASTDP_1024x768_75 0x0B
  381. #define ASTDP_1024x768_85 0x0C
  382. #define ASTDP_1280x1024_60 0x0D
  383. #define ASTDP_1280x1024_75 0x0E
  384. #define ASTDP_1280x1024_85 0x0F
  385. #define ASTDP_1600x1200_60 0x10
  386. #define ASTDP_320x240_60 0x11
  387. #define ASTDP_400x300_60 0x12
  388. #define ASTDP_512x384_60 0x13
  389. #define ASTDP_1920x1200_60 0x14
  390. #define ASTDP_1920x1080_60 0x15
  391. #define ASTDP_1280x800_60 0x16
  392. #define ASTDP_1280x800_60_RB 0x17
  393. #define ASTDP_1440x900_60 0x18
  394. #define ASTDP_1440x900_60_RB 0x19
  395. #define ASTDP_1680x1050_60 0x1A
  396. #define ASTDP_1680x1050_60_RB 0x1B
  397. #define ASTDP_1600x900_60 0x1C
  398. #define ASTDP_1600x900_60_RB 0x1D
  399. #define ASTDP_1366x768_60 0x1E
  400. #define ASTDP_1152x864_75 0x1F
  401. int ast_mm_init(struct ast_private *ast);
  402. /* ast post */
  403. void ast_enable_vga(struct drm_device *dev);
  404. void ast_enable_mmio(struct drm_device *dev);
  405. bool ast_is_vga_enabled(struct drm_device *dev);
  406. void ast_post_gpu(struct drm_device *dev);
  407. u32 ast_mindwm(struct ast_private *ast, u32 r);
  408. void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
  409. void ast_patch_ahb_2500(struct ast_private *ast);
  410. /* ast dp501 */
  411. void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
  412. bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
  413. bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
  414. u8 ast_get_dp501_max_clk(struct drm_device *dev);
  415. void ast_init_3rdtx(struct drm_device *dev);
  416. /* ast_i2c.c */
  417. struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
  418. /* aspeed DP */
  419. int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata);
  420. void ast_dp_launch(struct drm_device *dev, u8 bPower);
  421. void ast_dp_power_on_off(struct drm_device *dev, bool no);
  422. void ast_dp_set_on_off(struct drm_device *dev, bool no);
  423. void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode);
  424. #endif