acpi.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright(c) 2021 Intel Corporation. All rights reserved. */
  3. #include <linux/platform_device.h>
  4. #include <linux/module.h>
  5. #include <linux/device.h>
  6. #include <linux/kernel.h>
  7. #include <linux/acpi.h>
  8. #include <linux/pci.h>
  9. #include "cxlpci.h"
  10. #include "cxl.h"
  11. static unsigned long cfmws_to_decoder_flags(int restrictions)
  12. {
  13. unsigned long flags = CXL_DECODER_F_ENABLE;
  14. if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)
  15. flags |= CXL_DECODER_F_TYPE2;
  16. if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)
  17. flags |= CXL_DECODER_F_TYPE3;
  18. if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
  19. flags |= CXL_DECODER_F_RAM;
  20. if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
  21. flags |= CXL_DECODER_F_PMEM;
  22. if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
  23. flags |= CXL_DECODER_F_LOCK;
  24. return flags;
  25. }
  26. static int cxl_acpi_cfmws_verify(struct device *dev,
  27. struct acpi_cedt_cfmws *cfmws)
  28. {
  29. int rc, expected_len;
  30. unsigned int ways;
  31. if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) {
  32. dev_err(dev, "CFMWS Unsupported Interleave Arithmetic\n");
  33. return -EINVAL;
  34. }
  35. if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
  36. dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
  37. return -EINVAL;
  38. }
  39. if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
  40. dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
  41. return -EINVAL;
  42. }
  43. rc = cxl_to_ways(cfmws->interleave_ways, &ways);
  44. if (rc) {
  45. dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
  46. cfmws->interleave_ways);
  47. return -EINVAL;
  48. }
  49. expected_len = struct_size(cfmws, interleave_targets, ways);
  50. if (cfmws->header.length < expected_len) {
  51. dev_err(dev, "CFMWS length %d less than expected %d\n",
  52. cfmws->header.length, expected_len);
  53. return -EINVAL;
  54. }
  55. if (cfmws->header.length > expected_len)
  56. dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
  57. cfmws->header.length, expected_len);
  58. return 0;
  59. }
  60. struct cxl_cfmws_context {
  61. struct device *dev;
  62. struct cxl_port *root_port;
  63. struct resource *cxl_res;
  64. int id;
  65. };
  66. static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
  67. const unsigned long end)
  68. {
  69. int target_map[CXL_DECODER_MAX_INTERLEAVE];
  70. struct cxl_cfmws_context *ctx = arg;
  71. struct cxl_port *root_port = ctx->root_port;
  72. struct resource *cxl_res = ctx->cxl_res;
  73. struct cxl_root_decoder *cxlrd;
  74. struct device *dev = ctx->dev;
  75. struct acpi_cedt_cfmws *cfmws;
  76. struct cxl_decoder *cxld;
  77. unsigned int ways, i, ig;
  78. struct resource *res;
  79. int rc;
  80. cfmws = (struct acpi_cedt_cfmws *) header;
  81. rc = cxl_acpi_cfmws_verify(dev, cfmws);
  82. if (rc) {
  83. dev_err(dev, "CFMWS range %#llx-%#llx not registered\n",
  84. cfmws->base_hpa,
  85. cfmws->base_hpa + cfmws->window_size - 1);
  86. return 0;
  87. }
  88. rc = cxl_to_ways(cfmws->interleave_ways, &ways);
  89. if (rc)
  90. return rc;
  91. rc = cxl_to_granularity(cfmws->granularity, &ig);
  92. if (rc)
  93. return rc;
  94. for (i = 0; i < ways; i++)
  95. target_map[i] = cfmws->interleave_targets[i];
  96. res = kzalloc(sizeof(*res), GFP_KERNEL);
  97. if (!res)
  98. return -ENOMEM;
  99. res->name = kasprintf(GFP_KERNEL, "CXL Window %d", ctx->id++);
  100. if (!res->name)
  101. goto err_name;
  102. res->start = cfmws->base_hpa;
  103. res->end = cfmws->base_hpa + cfmws->window_size - 1;
  104. res->flags = IORESOURCE_MEM;
  105. /* add to the local resource tracking to establish a sort order */
  106. rc = insert_resource(cxl_res, res);
  107. if (rc)
  108. goto err_insert;
  109. cxlrd = cxl_root_decoder_alloc(root_port, ways);
  110. if (IS_ERR(cxlrd))
  111. return 0;
  112. cxld = &cxlrd->cxlsd.cxld;
  113. cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
  114. cxld->target_type = CXL_DECODER_EXPANDER;
  115. cxld->hpa_range = (struct range) {
  116. .start = res->start,
  117. .end = res->end,
  118. };
  119. cxld->interleave_ways = ways;
  120. /*
  121. * Minimize the x1 granularity to advertise support for any
  122. * valid region granularity
  123. */
  124. if (ways == 1)
  125. ig = CXL_DECODER_MIN_GRANULARITY;
  126. cxld->interleave_granularity = ig;
  127. rc = cxl_decoder_add(cxld, target_map);
  128. if (rc)
  129. put_device(&cxld->dev);
  130. else
  131. rc = cxl_decoder_autoremove(dev, cxld);
  132. if (rc) {
  133. dev_err(dev, "Failed to add decode range: %pr", res);
  134. return rc;
  135. }
  136. dev_dbg(dev, "add: %s node: %d range [%#llx - %#llx]\n",
  137. dev_name(&cxld->dev),
  138. phys_to_target_node(cxld->hpa_range.start),
  139. cxld->hpa_range.start, cxld->hpa_range.end);
  140. return 0;
  141. err_insert:
  142. kfree(res->name);
  143. err_name:
  144. kfree(res);
  145. return -ENOMEM;
  146. }
  147. __mock struct acpi_device *to_cxl_host_bridge(struct device *host,
  148. struct device *dev)
  149. {
  150. struct acpi_device *adev = to_acpi_device(dev);
  151. if (!acpi_pci_find_root(adev->handle))
  152. return NULL;
  153. if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
  154. return adev;
  155. return NULL;
  156. }
  157. /*
  158. * A host bridge is a dport to a CFMWS decode and it is a uport to the
  159. * dport (PCIe Root Ports) in the host bridge.
  160. */
  161. static int add_host_bridge_uport(struct device *match, void *arg)
  162. {
  163. struct cxl_port *root_port = arg;
  164. struct device *host = root_port->dev.parent;
  165. struct acpi_device *bridge = to_cxl_host_bridge(host, match);
  166. struct acpi_pci_root *pci_root;
  167. struct cxl_dport *dport;
  168. struct cxl_port *port;
  169. int rc;
  170. if (!bridge)
  171. return 0;
  172. dport = cxl_find_dport_by_dev(root_port, match);
  173. if (!dport) {
  174. dev_dbg(host, "host bridge expected and not found\n");
  175. return 0;
  176. }
  177. /*
  178. * Note that this lookup already succeeded in
  179. * to_cxl_host_bridge(), so no need to check for failure here
  180. */
  181. pci_root = acpi_pci_find_root(bridge->handle);
  182. rc = devm_cxl_register_pci_bus(host, match, pci_root->bus);
  183. if (rc)
  184. return rc;
  185. port = devm_cxl_add_port(host, match, dport->component_reg_phys, dport);
  186. if (IS_ERR(port))
  187. return PTR_ERR(port);
  188. return 0;
  189. }
  190. struct cxl_chbs_context {
  191. struct device *dev;
  192. unsigned long long uid;
  193. resource_size_t chbcr;
  194. };
  195. static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg,
  196. const unsigned long end)
  197. {
  198. struct cxl_chbs_context *ctx = arg;
  199. struct acpi_cedt_chbs *chbs;
  200. if (ctx->chbcr)
  201. return 0;
  202. chbs = (struct acpi_cedt_chbs *) header;
  203. if (ctx->uid != chbs->uid)
  204. return 0;
  205. ctx->chbcr = chbs->base;
  206. return 0;
  207. }
  208. static int add_host_bridge_dport(struct device *match, void *arg)
  209. {
  210. acpi_status status;
  211. unsigned long long uid;
  212. struct cxl_dport *dport;
  213. struct cxl_chbs_context ctx;
  214. struct cxl_port *root_port = arg;
  215. struct device *host = root_port->dev.parent;
  216. struct acpi_device *bridge = to_cxl_host_bridge(host, match);
  217. if (!bridge)
  218. return 0;
  219. status = acpi_evaluate_integer(bridge->handle, METHOD_NAME__UID, NULL,
  220. &uid);
  221. if (status != AE_OK) {
  222. dev_err(host, "unable to retrieve _UID of %s\n",
  223. dev_name(match));
  224. return -ENODEV;
  225. }
  226. ctx = (struct cxl_chbs_context) {
  227. .dev = host,
  228. .uid = uid,
  229. };
  230. acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbcr, &ctx);
  231. if (ctx.chbcr == 0) {
  232. dev_warn(host, "No CHBS found for Host Bridge: %s\n",
  233. dev_name(match));
  234. return 0;
  235. }
  236. dport = devm_cxl_add_dport(root_port, match, uid, ctx.chbcr);
  237. if (IS_ERR(dport)) {
  238. dev_err(host, "failed to add downstream port: %s\n",
  239. dev_name(match));
  240. return PTR_ERR(dport);
  241. }
  242. dev_dbg(host, "add dport%llu: %s\n", uid, dev_name(match));
  243. return 0;
  244. }
  245. static int add_root_nvdimm_bridge(struct device *match, void *data)
  246. {
  247. struct cxl_decoder *cxld;
  248. struct cxl_port *root_port = data;
  249. struct cxl_nvdimm_bridge *cxl_nvb;
  250. struct device *host = root_port->dev.parent;
  251. if (!is_root_decoder(match))
  252. return 0;
  253. cxld = to_cxl_decoder(match);
  254. if (!(cxld->flags & CXL_DECODER_F_PMEM))
  255. return 0;
  256. cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
  257. if (IS_ERR(cxl_nvb)) {
  258. dev_dbg(host, "failed to register pmem\n");
  259. return PTR_ERR(cxl_nvb);
  260. }
  261. dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
  262. dev_name(&cxl_nvb->dev));
  263. return 1;
  264. }
  265. static struct lock_class_key cxl_root_key;
  266. static void cxl_acpi_lock_reset_class(void *dev)
  267. {
  268. device_lock_reset_class(dev);
  269. }
  270. static void del_cxl_resource(struct resource *res)
  271. {
  272. kfree(res->name);
  273. kfree(res);
  274. }
  275. static void cxl_set_public_resource(struct resource *priv, struct resource *pub)
  276. {
  277. priv->desc = (unsigned long) pub;
  278. }
  279. static struct resource *cxl_get_public_resource(struct resource *priv)
  280. {
  281. return (struct resource *) priv->desc;
  282. }
  283. static void remove_cxl_resources(void *data)
  284. {
  285. struct resource *res, *next, *cxl = data;
  286. for (res = cxl->child; res; res = next) {
  287. struct resource *victim = cxl_get_public_resource(res);
  288. next = res->sibling;
  289. remove_resource(res);
  290. if (victim) {
  291. remove_resource(victim);
  292. kfree(victim);
  293. }
  294. del_cxl_resource(res);
  295. }
  296. }
  297. /**
  298. * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
  299. * @cxl_res: A standalone resource tree where each CXL window is a sibling
  300. *
  301. * Walk each CXL window in @cxl_res and add it to iomem_resource potentially
  302. * expanding its boundaries to ensure that any conflicting resources become
  303. * children. If a window is expanded it may then conflict with a another window
  304. * entry and require the window to be truncated or trimmed. Consider this
  305. * situation:
  306. *
  307. * |-- "CXL Window 0" --||----- "CXL Window 1" -----|
  308. * |--------------- "System RAM" -------------|
  309. *
  310. * ...where platform firmware has established as System RAM resource across 2
  311. * windows, but has left some portion of window 1 for dynamic CXL region
  312. * provisioning. In this case "Window 0" will span the entirety of the "System
  313. * RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end
  314. * of that "System RAM" resource.
  315. */
  316. static int add_cxl_resources(struct resource *cxl_res)
  317. {
  318. struct resource *res, *new, *next;
  319. for (res = cxl_res->child; res; res = next) {
  320. new = kzalloc(sizeof(*new), GFP_KERNEL);
  321. if (!new)
  322. return -ENOMEM;
  323. new->name = res->name;
  324. new->start = res->start;
  325. new->end = res->end;
  326. new->flags = IORESOURCE_MEM;
  327. new->desc = IORES_DESC_CXL;
  328. /*
  329. * Record the public resource in the private cxl_res tree for
  330. * later removal.
  331. */
  332. cxl_set_public_resource(res, new);
  333. insert_resource_expand_to_fit(&iomem_resource, new);
  334. next = res->sibling;
  335. while (next && resource_overlaps(new, next)) {
  336. if (resource_contains(new, next)) {
  337. struct resource *_next = next->sibling;
  338. remove_resource(next);
  339. del_cxl_resource(next);
  340. next = _next;
  341. } else
  342. next->start = new->end + 1;
  343. }
  344. }
  345. return 0;
  346. }
  347. static int pair_cxl_resource(struct device *dev, void *data)
  348. {
  349. struct resource *cxl_res = data;
  350. struct resource *p;
  351. if (!is_root_decoder(dev))
  352. return 0;
  353. for (p = cxl_res->child; p; p = p->sibling) {
  354. struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
  355. struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
  356. struct resource res = {
  357. .start = cxld->hpa_range.start,
  358. .end = cxld->hpa_range.end,
  359. .flags = IORESOURCE_MEM,
  360. };
  361. if (resource_contains(p, &res)) {
  362. cxlrd->res = cxl_get_public_resource(p);
  363. break;
  364. }
  365. }
  366. return 0;
  367. }
  368. static int cxl_acpi_probe(struct platform_device *pdev)
  369. {
  370. int rc;
  371. struct resource *cxl_res;
  372. struct cxl_port *root_port;
  373. struct device *host = &pdev->dev;
  374. struct acpi_device *adev = ACPI_COMPANION(host);
  375. struct cxl_cfmws_context ctx;
  376. device_lock_set_class(&pdev->dev, &cxl_root_key);
  377. rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,
  378. &pdev->dev);
  379. if (rc)
  380. return rc;
  381. cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);
  382. if (!cxl_res)
  383. return -ENOMEM;
  384. cxl_res->name = "CXL mem";
  385. cxl_res->start = 0;
  386. cxl_res->end = -1;
  387. cxl_res->flags = IORESOURCE_MEM;
  388. root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
  389. if (IS_ERR(root_port))
  390. return PTR_ERR(root_port);
  391. rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
  392. add_host_bridge_dport);
  393. if (rc < 0)
  394. return rc;
  395. rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);
  396. if (rc)
  397. return rc;
  398. ctx = (struct cxl_cfmws_context) {
  399. .dev = host,
  400. .root_port = root_port,
  401. .cxl_res = cxl_res,
  402. };
  403. rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
  404. if (rc < 0)
  405. return -ENXIO;
  406. rc = add_cxl_resources(cxl_res);
  407. if (rc)
  408. return rc;
  409. /*
  410. * Populate the root decoders with their related iomem resource,
  411. * if present
  412. */
  413. device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource);
  414. /*
  415. * Root level scanned with host-bridge as dports, now scan host-bridges
  416. * for their role as CXL uports to their CXL-capable PCIe Root Ports.
  417. */
  418. rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
  419. add_host_bridge_uport);
  420. if (rc < 0)
  421. return rc;
  422. if (IS_ENABLED(CONFIG_CXL_PMEM))
  423. rc = device_for_each_child(&root_port->dev, root_port,
  424. add_root_nvdimm_bridge);
  425. if (rc < 0)
  426. return rc;
  427. /* In case PCI is scanned before ACPI re-trigger memdev attach */
  428. return cxl_bus_rescan();
  429. }
  430. static const struct acpi_device_id cxl_acpi_ids[] = {
  431. { "ACPI0017" },
  432. { },
  433. };
  434. MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
  435. static const struct platform_device_id cxl_test_ids[] = {
  436. { "cxl_acpi" },
  437. { },
  438. };
  439. MODULE_DEVICE_TABLE(platform, cxl_test_ids);
  440. static struct platform_driver cxl_acpi_driver = {
  441. .probe = cxl_acpi_probe,
  442. .driver = {
  443. .name = KBUILD_MODNAME,
  444. .acpi_match_table = cxl_acpi_ids,
  445. },
  446. .id_table = cxl_test_ids,
  447. };
  448. module_platform_driver(cxl_acpi_driver);
  449. MODULE_LICENSE("GPL v2");
  450. MODULE_IMPORT_NS(CXL);
  451. MODULE_IMPORT_NS(ACPI);