rk3288_crypto.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Crypto acceleration support for Rockchip RK3288
  4. *
  5. * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
  6. *
  7. * Author: Zain Wang <[email protected]>
  8. *
  9. * Some ideas are from marvell-cesa.c and s5p-sss.c driver.
  10. */
  11. #include "rk3288_crypto.h"
  12. #include <linux/dma-mapping.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/of.h>
  16. #include <linux/clk.h>
  17. #include <linux/crypto.h>
  18. #include <linux/reset.h>
  19. static int rk_crypto_enable_clk(struct rk_crypto_info *dev)
  20. {
  21. int err;
  22. err = clk_prepare_enable(dev->sclk);
  23. if (err) {
  24. dev_err(dev->dev, "[%s:%d], Couldn't enable clock sclk\n",
  25. __func__, __LINE__);
  26. goto err_return;
  27. }
  28. err = clk_prepare_enable(dev->aclk);
  29. if (err) {
  30. dev_err(dev->dev, "[%s:%d], Couldn't enable clock aclk\n",
  31. __func__, __LINE__);
  32. goto err_aclk;
  33. }
  34. err = clk_prepare_enable(dev->hclk);
  35. if (err) {
  36. dev_err(dev->dev, "[%s:%d], Couldn't enable clock hclk\n",
  37. __func__, __LINE__);
  38. goto err_hclk;
  39. }
  40. err = clk_prepare_enable(dev->dmaclk);
  41. if (err) {
  42. dev_err(dev->dev, "[%s:%d], Couldn't enable clock dmaclk\n",
  43. __func__, __LINE__);
  44. goto err_dmaclk;
  45. }
  46. return err;
  47. err_dmaclk:
  48. clk_disable_unprepare(dev->hclk);
  49. err_hclk:
  50. clk_disable_unprepare(dev->aclk);
  51. err_aclk:
  52. clk_disable_unprepare(dev->sclk);
  53. err_return:
  54. return err;
  55. }
  56. static void rk_crypto_disable_clk(struct rk_crypto_info *dev)
  57. {
  58. clk_disable_unprepare(dev->dmaclk);
  59. clk_disable_unprepare(dev->hclk);
  60. clk_disable_unprepare(dev->aclk);
  61. clk_disable_unprepare(dev->sclk);
  62. }
  63. static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id)
  64. {
  65. struct rk_crypto_info *dev = platform_get_drvdata(dev_id);
  66. u32 interrupt_status;
  67. interrupt_status = CRYPTO_READ(dev, RK_CRYPTO_INTSTS);
  68. CRYPTO_WRITE(dev, RK_CRYPTO_INTSTS, interrupt_status);
  69. dev->status = 1;
  70. if (interrupt_status & 0x0a) {
  71. dev_warn(dev->dev, "DMA Error\n");
  72. dev->status = 0;
  73. }
  74. complete(&dev->complete);
  75. return IRQ_HANDLED;
  76. }
  77. static struct rk_crypto_tmp *rk_cipher_algs[] = {
  78. &rk_ecb_aes_alg,
  79. &rk_cbc_aes_alg,
  80. &rk_ecb_des_alg,
  81. &rk_cbc_des_alg,
  82. &rk_ecb_des3_ede_alg,
  83. &rk_cbc_des3_ede_alg,
  84. &rk_ahash_sha1,
  85. &rk_ahash_sha256,
  86. &rk_ahash_md5,
  87. };
  88. static int rk_crypto_register(struct rk_crypto_info *crypto_info)
  89. {
  90. unsigned int i, k;
  91. int err = 0;
  92. for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) {
  93. rk_cipher_algs[i]->dev = crypto_info;
  94. if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER)
  95. err = crypto_register_skcipher(
  96. &rk_cipher_algs[i]->alg.skcipher);
  97. else
  98. err = crypto_register_ahash(
  99. &rk_cipher_algs[i]->alg.hash);
  100. if (err)
  101. goto err_cipher_algs;
  102. }
  103. return 0;
  104. err_cipher_algs:
  105. for (k = 0; k < i; k++) {
  106. if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER)
  107. crypto_unregister_skcipher(&rk_cipher_algs[k]->alg.skcipher);
  108. else
  109. crypto_unregister_ahash(&rk_cipher_algs[i]->alg.hash);
  110. }
  111. return err;
  112. }
  113. static void rk_crypto_unregister(void)
  114. {
  115. unsigned int i;
  116. for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) {
  117. if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER)
  118. crypto_unregister_skcipher(&rk_cipher_algs[i]->alg.skcipher);
  119. else
  120. crypto_unregister_ahash(&rk_cipher_algs[i]->alg.hash);
  121. }
  122. }
  123. static void rk_crypto_action(void *data)
  124. {
  125. struct rk_crypto_info *crypto_info = data;
  126. reset_control_assert(crypto_info->rst);
  127. }
  128. static const struct of_device_id crypto_of_id_table[] = {
  129. { .compatible = "rockchip,rk3288-crypto" },
  130. {}
  131. };
  132. MODULE_DEVICE_TABLE(of, crypto_of_id_table);
  133. static int rk_crypto_probe(struct platform_device *pdev)
  134. {
  135. struct device *dev = &pdev->dev;
  136. struct rk_crypto_info *crypto_info;
  137. int err = 0;
  138. crypto_info = devm_kzalloc(&pdev->dev,
  139. sizeof(*crypto_info), GFP_KERNEL);
  140. if (!crypto_info) {
  141. err = -ENOMEM;
  142. goto err_crypto;
  143. }
  144. crypto_info->rst = devm_reset_control_get(dev, "crypto-rst");
  145. if (IS_ERR(crypto_info->rst)) {
  146. err = PTR_ERR(crypto_info->rst);
  147. goto err_crypto;
  148. }
  149. reset_control_assert(crypto_info->rst);
  150. usleep_range(10, 20);
  151. reset_control_deassert(crypto_info->rst);
  152. err = devm_add_action_or_reset(dev, rk_crypto_action, crypto_info);
  153. if (err)
  154. goto err_crypto;
  155. crypto_info->reg = devm_platform_ioremap_resource(pdev, 0);
  156. if (IS_ERR(crypto_info->reg)) {
  157. err = PTR_ERR(crypto_info->reg);
  158. goto err_crypto;
  159. }
  160. crypto_info->aclk = devm_clk_get(&pdev->dev, "aclk");
  161. if (IS_ERR(crypto_info->aclk)) {
  162. err = PTR_ERR(crypto_info->aclk);
  163. goto err_crypto;
  164. }
  165. crypto_info->hclk = devm_clk_get(&pdev->dev, "hclk");
  166. if (IS_ERR(crypto_info->hclk)) {
  167. err = PTR_ERR(crypto_info->hclk);
  168. goto err_crypto;
  169. }
  170. crypto_info->sclk = devm_clk_get(&pdev->dev, "sclk");
  171. if (IS_ERR(crypto_info->sclk)) {
  172. err = PTR_ERR(crypto_info->sclk);
  173. goto err_crypto;
  174. }
  175. crypto_info->dmaclk = devm_clk_get(&pdev->dev, "apb_pclk");
  176. if (IS_ERR(crypto_info->dmaclk)) {
  177. err = PTR_ERR(crypto_info->dmaclk);
  178. goto err_crypto;
  179. }
  180. crypto_info->irq = platform_get_irq(pdev, 0);
  181. if (crypto_info->irq < 0) {
  182. dev_warn(crypto_info->dev,
  183. "control Interrupt is not available.\n");
  184. err = crypto_info->irq;
  185. goto err_crypto;
  186. }
  187. err = devm_request_irq(&pdev->dev, crypto_info->irq,
  188. rk_crypto_irq_handle, IRQF_SHARED,
  189. "rk-crypto", pdev);
  190. if (err) {
  191. dev_err(crypto_info->dev, "irq request failed.\n");
  192. goto err_crypto;
  193. }
  194. crypto_info->dev = &pdev->dev;
  195. platform_set_drvdata(pdev, crypto_info);
  196. crypto_info->engine = crypto_engine_alloc_init(&pdev->dev, true);
  197. crypto_engine_start(crypto_info->engine);
  198. init_completion(&crypto_info->complete);
  199. rk_crypto_enable_clk(crypto_info);
  200. err = rk_crypto_register(crypto_info);
  201. if (err) {
  202. dev_err(dev, "err in register alg");
  203. goto err_register_alg;
  204. }
  205. dev_info(dev, "Crypto Accelerator successfully registered\n");
  206. return 0;
  207. err_register_alg:
  208. crypto_engine_exit(crypto_info->engine);
  209. err_crypto:
  210. dev_err(dev, "Crypto Accelerator not successfully registered\n");
  211. return err;
  212. }
  213. static int rk_crypto_remove(struct platform_device *pdev)
  214. {
  215. struct rk_crypto_info *crypto_tmp = platform_get_drvdata(pdev);
  216. rk_crypto_unregister();
  217. rk_crypto_disable_clk(crypto_tmp);
  218. crypto_engine_exit(crypto_tmp->engine);
  219. return 0;
  220. }
  221. static struct platform_driver crypto_driver = {
  222. .probe = rk_crypto_probe,
  223. .remove = rk_crypto_remove,
  224. .driver = {
  225. .name = "rk3288-crypto",
  226. .of_match_table = crypto_of_id_table,
  227. },
  228. };
  229. module_platform_driver(crypto_driver);
  230. MODULE_AUTHOR("Zain Wang <[email protected]>");
  231. MODULE_DESCRIPTION("Support for Rockchip's cryptographic engine");
  232. MODULE_LICENSE("GPL");