sha.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/device.h>
  6. #include <linux/dma-mapping.h>
  7. #include <linux/interrupt.h>
  8. #include <crypto/internal/hash.h>
  9. #include "common.h"
  10. #include "core.h"
  11. #include "sha.h"
  12. struct qce_sha_saved_state {
  13. u8 pending_buf[QCE_SHA_MAX_BLOCKSIZE];
  14. u8 partial_digest[QCE_SHA_MAX_DIGESTSIZE];
  15. __be32 byte_count[2];
  16. unsigned int pending_buflen;
  17. unsigned int flags;
  18. u64 count;
  19. bool first_blk;
  20. };
  21. static LIST_HEAD(ahash_algs);
  22. static const u32 std_iv_sha1[SHA256_DIGEST_SIZE / sizeof(u32)] = {
  23. SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4, 0, 0, 0
  24. };
  25. static const u32 std_iv_sha256[SHA256_DIGEST_SIZE / sizeof(u32)] = {
  26. SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3,
  27. SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7
  28. };
  29. static void qce_ahash_done(void *data)
  30. {
  31. struct crypto_async_request *async_req = data;
  32. struct ahash_request *req = ahash_request_cast(async_req);
  33. struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
  34. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  35. struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
  36. struct qce_device *qce = tmpl->qce;
  37. struct qce_result_dump *result = qce->dma.result_buf;
  38. unsigned int digestsize = crypto_ahash_digestsize(ahash);
  39. int error;
  40. u32 status;
  41. error = qce_dma_terminate_all(&qce->dma);
  42. if (error)
  43. dev_dbg(qce->dev, "ahash dma termination error (%d)\n", error);
  44. dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
  45. dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
  46. memcpy(rctx->digest, result->auth_iv, digestsize);
  47. if (req->result && rctx->last_blk)
  48. memcpy(req->result, result->auth_iv, digestsize);
  49. rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]);
  50. rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]);
  51. error = qce_check_status(qce, &status);
  52. if (error < 0)
  53. dev_dbg(qce->dev, "ahash operation error (%x)\n", status);
  54. req->src = rctx->src_orig;
  55. req->nbytes = rctx->nbytes_orig;
  56. rctx->last_blk = false;
  57. rctx->first_blk = false;
  58. qce->async_req_done(tmpl->qce, error);
  59. }
  60. static int qce_ahash_async_req_handle(struct crypto_async_request *async_req)
  61. {
  62. struct ahash_request *req = ahash_request_cast(async_req);
  63. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  64. struct qce_sha_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
  65. struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
  66. struct qce_device *qce = tmpl->qce;
  67. unsigned long flags = rctx->flags;
  68. int ret;
  69. if (IS_SHA_HMAC(flags)) {
  70. rctx->authkey = ctx->authkey;
  71. rctx->authklen = QCE_SHA_HMAC_KEY_SIZE;
  72. } else if (IS_CMAC(flags)) {
  73. rctx->authkey = ctx->authkey;
  74. rctx->authklen = AES_KEYSIZE_128;
  75. }
  76. rctx->src_nents = sg_nents_for_len(req->src, req->nbytes);
  77. if (rctx->src_nents < 0) {
  78. dev_err(qce->dev, "Invalid numbers of src SG.\n");
  79. return rctx->src_nents;
  80. }
  81. ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
  82. if (!ret)
  83. return -EIO;
  84. sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
  85. ret = dma_map_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
  86. if (!ret) {
  87. ret = -EIO;
  88. goto error_unmap_src;
  89. }
  90. ret = qce_dma_prep_sgs(&qce->dma, req->src, rctx->src_nents,
  91. &rctx->result_sg, 1, qce_ahash_done, async_req);
  92. if (ret)
  93. goto error_unmap_dst;
  94. qce_dma_issue_pending(&qce->dma);
  95. ret = qce_start(async_req, tmpl->crypto_alg_type);
  96. if (ret)
  97. goto error_terminate;
  98. return 0;
  99. error_terminate:
  100. qce_dma_terminate_all(&qce->dma);
  101. error_unmap_dst:
  102. dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
  103. error_unmap_src:
  104. dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
  105. return ret;
  106. }
  107. static int qce_ahash_init(struct ahash_request *req)
  108. {
  109. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  110. struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
  111. const u32 *std_iv = tmpl->std_iv;
  112. memset(rctx, 0, sizeof(*rctx));
  113. rctx->first_blk = true;
  114. rctx->last_blk = false;
  115. rctx->flags = tmpl->alg_flags;
  116. memcpy(rctx->digest, std_iv, sizeof(rctx->digest));
  117. return 0;
  118. }
  119. static int qce_ahash_export(struct ahash_request *req, void *out)
  120. {
  121. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  122. struct qce_sha_saved_state *export_state = out;
  123. memcpy(export_state->pending_buf, rctx->buf, rctx->buflen);
  124. memcpy(export_state->partial_digest, rctx->digest, sizeof(rctx->digest));
  125. export_state->byte_count[0] = rctx->byte_count[0];
  126. export_state->byte_count[1] = rctx->byte_count[1];
  127. export_state->pending_buflen = rctx->buflen;
  128. export_state->count = rctx->count;
  129. export_state->first_blk = rctx->first_blk;
  130. export_state->flags = rctx->flags;
  131. return 0;
  132. }
  133. static int qce_ahash_import(struct ahash_request *req, const void *in)
  134. {
  135. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  136. const struct qce_sha_saved_state *import_state = in;
  137. memset(rctx, 0, sizeof(*rctx));
  138. rctx->count = import_state->count;
  139. rctx->buflen = import_state->pending_buflen;
  140. rctx->first_blk = import_state->first_blk;
  141. rctx->flags = import_state->flags;
  142. rctx->byte_count[0] = import_state->byte_count[0];
  143. rctx->byte_count[1] = import_state->byte_count[1];
  144. memcpy(rctx->buf, import_state->pending_buf, rctx->buflen);
  145. memcpy(rctx->digest, import_state->partial_digest, sizeof(rctx->digest));
  146. return 0;
  147. }
  148. static int qce_ahash_update(struct ahash_request *req)
  149. {
  150. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  151. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  152. struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
  153. struct qce_device *qce = tmpl->qce;
  154. struct scatterlist *sg_last, *sg;
  155. unsigned int total, len;
  156. unsigned int hash_later;
  157. unsigned int nbytes;
  158. unsigned int blocksize;
  159. blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
  160. rctx->count += req->nbytes;
  161. /* check for buffer from previous updates and append it */
  162. total = req->nbytes + rctx->buflen;
  163. if (total <= blocksize) {
  164. scatterwalk_map_and_copy(rctx->buf + rctx->buflen, req->src,
  165. 0, req->nbytes, 0);
  166. rctx->buflen += req->nbytes;
  167. return 0;
  168. }
  169. /* save the original req structure fields */
  170. rctx->src_orig = req->src;
  171. rctx->nbytes_orig = req->nbytes;
  172. /*
  173. * if we have data from previous update copy them on buffer. The old
  174. * data will be combined with current request bytes.
  175. */
  176. if (rctx->buflen)
  177. memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen);
  178. /* calculate how many bytes will be hashed later */
  179. hash_later = total % blocksize;
  180. /*
  181. * At this point, there is more than one block size of data. If
  182. * the available data to transfer is exactly a multiple of block
  183. * size, save the last block to be transferred in qce_ahash_final
  184. * (with the last block bit set) if this is indeed the end of data
  185. * stream. If not this saved block will be transferred as part of
  186. * next update. If this block is not held back and if this is
  187. * indeed the end of data stream, the digest obtained will be wrong
  188. * since qce_ahash_final will see that rctx->buflen is 0 and return
  189. * doing nothing which in turn means that a digest will not be
  190. * copied to the destination result buffer. qce_ahash_final cannot
  191. * be made to alter this behavior and allowed to proceed if
  192. * rctx->buflen is 0 because the crypto engine BAM does not allow
  193. * for zero length transfers.
  194. */
  195. if (!hash_later)
  196. hash_later = blocksize;
  197. if (hash_later) {
  198. unsigned int src_offset = req->nbytes - hash_later;
  199. scatterwalk_map_and_copy(rctx->buf, req->src, src_offset,
  200. hash_later, 0);
  201. }
  202. /* here nbytes is multiple of blocksize */
  203. nbytes = total - hash_later;
  204. len = rctx->buflen;
  205. sg = sg_last = req->src;
  206. while (len < nbytes && sg) {
  207. if (len + sg_dma_len(sg) > nbytes)
  208. break;
  209. len += sg_dma_len(sg);
  210. sg_last = sg;
  211. sg = sg_next(sg);
  212. }
  213. if (!sg_last)
  214. return -EINVAL;
  215. if (rctx->buflen) {
  216. sg_init_table(rctx->sg, 2);
  217. sg_set_buf(rctx->sg, rctx->tmpbuf, rctx->buflen);
  218. sg_chain(rctx->sg, 2, req->src);
  219. req->src = rctx->sg;
  220. }
  221. req->nbytes = nbytes;
  222. rctx->buflen = hash_later;
  223. return qce->async_req_enqueue(tmpl->qce, &req->base);
  224. }
  225. static int qce_ahash_final(struct ahash_request *req)
  226. {
  227. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  228. struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
  229. struct qce_device *qce = tmpl->qce;
  230. if (!rctx->buflen) {
  231. if (tmpl->hash_zero)
  232. memcpy(req->result, tmpl->hash_zero,
  233. tmpl->alg.ahash.halg.digestsize);
  234. return 0;
  235. }
  236. rctx->last_blk = true;
  237. rctx->src_orig = req->src;
  238. rctx->nbytes_orig = req->nbytes;
  239. memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen);
  240. sg_init_one(rctx->sg, rctx->tmpbuf, rctx->buflen);
  241. req->src = rctx->sg;
  242. req->nbytes = rctx->buflen;
  243. return qce->async_req_enqueue(tmpl->qce, &req->base);
  244. }
  245. static int qce_ahash_digest(struct ahash_request *req)
  246. {
  247. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  248. struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
  249. struct qce_device *qce = tmpl->qce;
  250. int ret;
  251. ret = qce_ahash_init(req);
  252. if (ret)
  253. return ret;
  254. rctx->src_orig = req->src;
  255. rctx->nbytes_orig = req->nbytes;
  256. rctx->first_blk = true;
  257. rctx->last_blk = true;
  258. if (!rctx->nbytes_orig) {
  259. if (tmpl->hash_zero)
  260. memcpy(req->result, tmpl->hash_zero,
  261. tmpl->alg.ahash.halg.digestsize);
  262. return 0;
  263. }
  264. return qce->async_req_enqueue(tmpl->qce, &req->base);
  265. }
  266. static int qce_ahash_hmac_setkey(struct crypto_ahash *tfm, const u8 *key,
  267. unsigned int keylen)
  268. {
  269. unsigned int digestsize = crypto_ahash_digestsize(tfm);
  270. struct qce_sha_ctx *ctx = crypto_tfm_ctx(&tfm->base);
  271. struct crypto_wait wait;
  272. struct ahash_request *req;
  273. struct scatterlist sg;
  274. unsigned int blocksize;
  275. struct crypto_ahash *ahash_tfm;
  276. u8 *buf;
  277. int ret;
  278. const char *alg_name;
  279. blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
  280. memset(ctx->authkey, 0, sizeof(ctx->authkey));
  281. if (keylen <= blocksize) {
  282. memcpy(ctx->authkey, key, keylen);
  283. return 0;
  284. }
  285. if (digestsize == SHA1_DIGEST_SIZE)
  286. alg_name = "sha1-qce";
  287. else if (digestsize == SHA256_DIGEST_SIZE)
  288. alg_name = "sha256-qce";
  289. else
  290. return -EINVAL;
  291. ahash_tfm = crypto_alloc_ahash(alg_name, 0, 0);
  292. if (IS_ERR(ahash_tfm))
  293. return PTR_ERR(ahash_tfm);
  294. req = ahash_request_alloc(ahash_tfm, GFP_KERNEL);
  295. if (!req) {
  296. ret = -ENOMEM;
  297. goto err_free_ahash;
  298. }
  299. crypto_init_wait(&wait);
  300. ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
  301. crypto_req_done, &wait);
  302. crypto_ahash_clear_flags(ahash_tfm, ~0);
  303. buf = kzalloc(keylen + QCE_MAX_ALIGN_SIZE, GFP_KERNEL);
  304. if (!buf) {
  305. ret = -ENOMEM;
  306. goto err_free_req;
  307. }
  308. memcpy(buf, key, keylen);
  309. sg_init_one(&sg, buf, keylen);
  310. ahash_request_set_crypt(req, &sg, ctx->authkey, keylen);
  311. ret = crypto_wait_req(crypto_ahash_digest(req), &wait);
  312. kfree(buf);
  313. err_free_req:
  314. ahash_request_free(req);
  315. err_free_ahash:
  316. crypto_free_ahash(ahash_tfm);
  317. return ret;
  318. }
  319. static int qce_ahash_cra_init(struct crypto_tfm *tfm)
  320. {
  321. struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
  322. struct qce_sha_ctx *ctx = crypto_tfm_ctx(tfm);
  323. crypto_ahash_set_reqsize(ahash, sizeof(struct qce_sha_reqctx));
  324. memset(ctx, 0, sizeof(*ctx));
  325. return 0;
  326. }
  327. struct qce_ahash_def {
  328. unsigned long flags;
  329. const char *name;
  330. const char *drv_name;
  331. unsigned int digestsize;
  332. unsigned int blocksize;
  333. unsigned int statesize;
  334. const u32 *std_iv;
  335. };
  336. static const struct qce_ahash_def ahash_def[] = {
  337. {
  338. .flags = QCE_HASH_SHA1,
  339. .name = "sha1",
  340. .drv_name = "sha1-qce",
  341. .digestsize = SHA1_DIGEST_SIZE,
  342. .blocksize = SHA1_BLOCK_SIZE,
  343. .statesize = sizeof(struct qce_sha_saved_state),
  344. .std_iv = std_iv_sha1,
  345. },
  346. {
  347. .flags = QCE_HASH_SHA256,
  348. .name = "sha256",
  349. .drv_name = "sha256-qce",
  350. .digestsize = SHA256_DIGEST_SIZE,
  351. .blocksize = SHA256_BLOCK_SIZE,
  352. .statesize = sizeof(struct qce_sha_saved_state),
  353. .std_iv = std_iv_sha256,
  354. },
  355. {
  356. .flags = QCE_HASH_SHA1_HMAC,
  357. .name = "hmac(sha1)",
  358. .drv_name = "hmac-sha1-qce",
  359. .digestsize = SHA1_DIGEST_SIZE,
  360. .blocksize = SHA1_BLOCK_SIZE,
  361. .statesize = sizeof(struct qce_sha_saved_state),
  362. .std_iv = std_iv_sha1,
  363. },
  364. {
  365. .flags = QCE_HASH_SHA256_HMAC,
  366. .name = "hmac(sha256)",
  367. .drv_name = "hmac-sha256-qce",
  368. .digestsize = SHA256_DIGEST_SIZE,
  369. .blocksize = SHA256_BLOCK_SIZE,
  370. .statesize = sizeof(struct qce_sha_saved_state),
  371. .std_iv = std_iv_sha256,
  372. },
  373. };
  374. static int qce_ahash_register_one(const struct qce_ahash_def *def,
  375. struct qce_device *qce)
  376. {
  377. struct qce_alg_template *tmpl;
  378. struct ahash_alg *alg;
  379. struct crypto_alg *base;
  380. int ret;
  381. tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL);
  382. if (!tmpl)
  383. return -ENOMEM;
  384. tmpl->std_iv = def->std_iv;
  385. alg = &tmpl->alg.ahash;
  386. alg->init = qce_ahash_init;
  387. alg->update = qce_ahash_update;
  388. alg->final = qce_ahash_final;
  389. alg->digest = qce_ahash_digest;
  390. alg->export = qce_ahash_export;
  391. alg->import = qce_ahash_import;
  392. if (IS_SHA_HMAC(def->flags))
  393. alg->setkey = qce_ahash_hmac_setkey;
  394. alg->halg.digestsize = def->digestsize;
  395. alg->halg.statesize = def->statesize;
  396. if (IS_SHA1(def->flags))
  397. tmpl->hash_zero = sha1_zero_message_hash;
  398. else if (IS_SHA256(def->flags))
  399. tmpl->hash_zero = sha256_zero_message_hash;
  400. base = &alg->halg.base;
  401. base->cra_blocksize = def->blocksize;
  402. base->cra_priority = 300;
  403. base->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
  404. base->cra_ctxsize = sizeof(struct qce_sha_ctx);
  405. base->cra_alignmask = 0;
  406. base->cra_module = THIS_MODULE;
  407. base->cra_init = qce_ahash_cra_init;
  408. snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name);
  409. snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
  410. def->drv_name);
  411. INIT_LIST_HEAD(&tmpl->entry);
  412. tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_AHASH;
  413. tmpl->alg_flags = def->flags;
  414. tmpl->qce = qce;
  415. ret = crypto_register_ahash(alg);
  416. if (ret) {
  417. dev_err(qce->dev, "%s registration failed\n", base->cra_name);
  418. kfree(tmpl);
  419. return ret;
  420. }
  421. list_add_tail(&tmpl->entry, &ahash_algs);
  422. dev_dbg(qce->dev, "%s is registered\n", base->cra_name);
  423. return 0;
  424. }
  425. static void qce_ahash_unregister(struct qce_device *qce)
  426. {
  427. struct qce_alg_template *tmpl, *n;
  428. list_for_each_entry_safe(tmpl, n, &ahash_algs, entry) {
  429. crypto_unregister_ahash(&tmpl->alg.ahash);
  430. list_del(&tmpl->entry);
  431. kfree(tmpl);
  432. }
  433. }
  434. static int qce_ahash_register(struct qce_device *qce)
  435. {
  436. int ret, i;
  437. for (i = 0; i < ARRAY_SIZE(ahash_def); i++) {
  438. ret = qce_ahash_register_one(&ahash_def[i], qce);
  439. if (ret)
  440. goto err;
  441. }
  442. return 0;
  443. err:
  444. qce_ahash_unregister(qce);
  445. return ret;
  446. }
  447. const struct qce_algo_ops ahash_ops = {
  448. .type = CRYPTO_ALG_TYPE_AHASH,
  449. .register_algs = qce_ahash_register,
  450. .unregister_algs = qce_ahash_unregister,
  451. .async_req_handle = qce_ahash_async_req_handle,
  452. };