qm_common.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* Copyright (c) 2022 HiSilicon Limited. */
  3. #ifndef QM_COMMON_H
  4. #define QM_COMMON_H
  5. #define QM_DBG_READ_LEN 256
  6. struct qm_cqe {
  7. __le32 rsvd0;
  8. __le16 cmd_id;
  9. __le16 rsvd1;
  10. __le16 sq_head;
  11. __le16 sq_num;
  12. __le16 rsvd2;
  13. __le16 w7;
  14. };
  15. struct qm_eqe {
  16. __le32 dw0;
  17. };
  18. struct qm_aeqe {
  19. __le32 dw0;
  20. };
  21. struct qm_sqc {
  22. __le16 head;
  23. __le16 tail;
  24. __le32 base_l;
  25. __le32 base_h;
  26. __le32 dw3;
  27. __le16 w8;
  28. __le16 rsvd0;
  29. __le16 pasid;
  30. __le16 w11;
  31. __le16 cq_num;
  32. __le16 w13;
  33. __le32 rsvd1;
  34. };
  35. struct qm_cqc {
  36. __le16 head;
  37. __le16 tail;
  38. __le32 base_l;
  39. __le32 base_h;
  40. __le32 dw3;
  41. __le16 w8;
  42. __le16 rsvd0;
  43. __le16 pasid;
  44. __le16 w11;
  45. __le32 dw6;
  46. __le32 rsvd1;
  47. };
  48. struct qm_eqc {
  49. __le16 head;
  50. __le16 tail;
  51. __le32 base_l;
  52. __le32 base_h;
  53. __le32 dw3;
  54. __le32 rsvd[2];
  55. __le32 dw6;
  56. };
  57. struct qm_aeqc {
  58. __le16 head;
  59. __le16 tail;
  60. __le32 base_l;
  61. __le32 base_h;
  62. __le32 dw3;
  63. __le32 rsvd[2];
  64. __le32 dw6;
  65. };
  66. static const char * const qm_s[] = {
  67. "init", "start", "close", "stop",
  68. };
  69. void *hisi_qm_ctx_alloc(struct hisi_qm *qm, size_t ctx_size,
  70. dma_addr_t *dma_addr);
  71. void hisi_qm_ctx_free(struct hisi_qm *qm, size_t ctx_size,
  72. const void *ctx_addr, dma_addr_t *dma_addr);
  73. void hisi_qm_show_last_dfx_regs(struct hisi_qm *qm);
  74. void hisi_qm_set_algqos_init(struct hisi_qm *qm);
  75. #endif