ccp-dmaengine.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * AMD Cryptographic Coprocessor (CCP) driver
  4. *
  5. * Copyright (C) 2016,2019 Advanced Micro Devices, Inc.
  6. *
  7. * Author: Gary R Hook <[email protected]>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/kernel.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/mutex.h>
  15. #include <linux/ccp.h>
  16. #include "ccp-dev.h"
  17. #include "../../dma/dmaengine.h"
  18. #define CCP_DMA_WIDTH(_mask) \
  19. ({ \
  20. u64 mask = _mask + 1; \
  21. (mask == 0) ? 64 : fls64(mask); \
  22. })
  23. /* The CCP as a DMA provider can be configured for public or private
  24. * channels. Default is specified in the vdata for the device (PCI ID).
  25. * This module parameter will override for all channels on all devices:
  26. * dma_chan_attr = 0x2 to force all channels public
  27. * = 0x1 to force all channels private
  28. * = 0x0 to defer to the vdata setting
  29. * = any other value: warning, revert to 0x0
  30. */
  31. static unsigned int dma_chan_attr = CCP_DMA_DFLT;
  32. module_param(dma_chan_attr, uint, 0444);
  33. MODULE_PARM_DESC(dma_chan_attr, "Set DMA channel visibility: 0 (default) = device defaults, 1 = make private, 2 = make public");
  34. static unsigned int dmaengine = 1;
  35. module_param(dmaengine, uint, 0444);
  36. MODULE_PARM_DESC(dmaengine, "Register services with the DMA subsystem (any non-zero value, default: 1)");
  37. static unsigned int ccp_get_dma_chan_attr(struct ccp_device *ccp)
  38. {
  39. switch (dma_chan_attr) {
  40. case CCP_DMA_DFLT:
  41. return ccp->vdata->dma_chan_attr;
  42. case CCP_DMA_PRIV:
  43. return DMA_PRIVATE;
  44. case CCP_DMA_PUB:
  45. return 0;
  46. default:
  47. dev_info_once(ccp->dev, "Invalid value for dma_chan_attr: %d\n",
  48. dma_chan_attr);
  49. return ccp->vdata->dma_chan_attr;
  50. }
  51. }
  52. static void ccp_free_cmd_resources(struct ccp_device *ccp,
  53. struct list_head *list)
  54. {
  55. struct ccp_dma_cmd *cmd, *ctmp;
  56. list_for_each_entry_safe(cmd, ctmp, list, entry) {
  57. list_del(&cmd->entry);
  58. kmem_cache_free(ccp->dma_cmd_cache, cmd);
  59. }
  60. }
  61. static void ccp_free_desc_resources(struct ccp_device *ccp,
  62. struct list_head *list)
  63. {
  64. struct ccp_dma_desc *desc, *dtmp;
  65. list_for_each_entry_safe(desc, dtmp, list, entry) {
  66. ccp_free_cmd_resources(ccp, &desc->active);
  67. ccp_free_cmd_resources(ccp, &desc->pending);
  68. list_del(&desc->entry);
  69. kmem_cache_free(ccp->dma_desc_cache, desc);
  70. }
  71. }
  72. static void ccp_free_chan_resources(struct dma_chan *dma_chan)
  73. {
  74. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  75. dma_chan);
  76. unsigned long flags;
  77. dev_dbg(chan->ccp->dev, "%s - chan=%p\n", __func__, chan);
  78. spin_lock_irqsave(&chan->lock, flags);
  79. ccp_free_desc_resources(chan->ccp, &chan->complete);
  80. ccp_free_desc_resources(chan->ccp, &chan->active);
  81. ccp_free_desc_resources(chan->ccp, &chan->pending);
  82. ccp_free_desc_resources(chan->ccp, &chan->created);
  83. spin_unlock_irqrestore(&chan->lock, flags);
  84. }
  85. static void ccp_cleanup_desc_resources(struct ccp_device *ccp,
  86. struct list_head *list)
  87. {
  88. struct ccp_dma_desc *desc, *dtmp;
  89. list_for_each_entry_safe_reverse(desc, dtmp, list, entry) {
  90. if (!async_tx_test_ack(&desc->tx_desc))
  91. continue;
  92. dev_dbg(ccp->dev, "%s - desc=%p\n", __func__, desc);
  93. ccp_free_cmd_resources(ccp, &desc->active);
  94. ccp_free_cmd_resources(ccp, &desc->pending);
  95. list_del(&desc->entry);
  96. kmem_cache_free(ccp->dma_desc_cache, desc);
  97. }
  98. }
  99. static void ccp_do_cleanup(unsigned long data)
  100. {
  101. struct ccp_dma_chan *chan = (struct ccp_dma_chan *)data;
  102. unsigned long flags;
  103. dev_dbg(chan->ccp->dev, "%s - chan=%s\n", __func__,
  104. dma_chan_name(&chan->dma_chan));
  105. spin_lock_irqsave(&chan->lock, flags);
  106. ccp_cleanup_desc_resources(chan->ccp, &chan->complete);
  107. spin_unlock_irqrestore(&chan->lock, flags);
  108. }
  109. static int ccp_issue_next_cmd(struct ccp_dma_desc *desc)
  110. {
  111. struct ccp_dma_cmd *cmd;
  112. int ret;
  113. cmd = list_first_entry(&desc->pending, struct ccp_dma_cmd, entry);
  114. list_move(&cmd->entry, &desc->active);
  115. dev_dbg(desc->ccp->dev, "%s - tx %d, cmd=%p\n", __func__,
  116. desc->tx_desc.cookie, cmd);
  117. ret = ccp_enqueue_cmd(&cmd->ccp_cmd);
  118. if (!ret || (ret == -EINPROGRESS) || (ret == -EBUSY))
  119. return 0;
  120. dev_dbg(desc->ccp->dev, "%s - error: ret=%d, tx %d, cmd=%p\n", __func__,
  121. ret, desc->tx_desc.cookie, cmd);
  122. return ret;
  123. }
  124. static void ccp_free_active_cmd(struct ccp_dma_desc *desc)
  125. {
  126. struct ccp_dma_cmd *cmd;
  127. cmd = list_first_entry_or_null(&desc->active, struct ccp_dma_cmd,
  128. entry);
  129. if (!cmd)
  130. return;
  131. dev_dbg(desc->ccp->dev, "%s - freeing tx %d cmd=%p\n",
  132. __func__, desc->tx_desc.cookie, cmd);
  133. list_del(&cmd->entry);
  134. kmem_cache_free(desc->ccp->dma_cmd_cache, cmd);
  135. }
  136. static struct ccp_dma_desc *__ccp_next_dma_desc(struct ccp_dma_chan *chan,
  137. struct ccp_dma_desc *desc)
  138. {
  139. /* Move current DMA descriptor to the complete list */
  140. if (desc)
  141. list_move(&desc->entry, &chan->complete);
  142. /* Get the next DMA descriptor on the active list */
  143. desc = list_first_entry_or_null(&chan->active, struct ccp_dma_desc,
  144. entry);
  145. return desc;
  146. }
  147. static struct ccp_dma_desc *ccp_handle_active_desc(struct ccp_dma_chan *chan,
  148. struct ccp_dma_desc *desc)
  149. {
  150. struct dma_async_tx_descriptor *tx_desc;
  151. unsigned long flags;
  152. /* Loop over descriptors until one is found with commands */
  153. do {
  154. if (desc) {
  155. /* Remove the DMA command from the list and free it */
  156. ccp_free_active_cmd(desc);
  157. if (!list_empty(&desc->pending)) {
  158. /* No errors, keep going */
  159. if (desc->status != DMA_ERROR)
  160. return desc;
  161. /* Error, free remaining commands and move on */
  162. ccp_free_cmd_resources(desc->ccp,
  163. &desc->pending);
  164. }
  165. tx_desc = &desc->tx_desc;
  166. } else {
  167. tx_desc = NULL;
  168. }
  169. spin_lock_irqsave(&chan->lock, flags);
  170. if (desc) {
  171. if (desc->status != DMA_ERROR)
  172. desc->status = DMA_COMPLETE;
  173. dev_dbg(desc->ccp->dev,
  174. "%s - tx %d complete, status=%u\n", __func__,
  175. desc->tx_desc.cookie, desc->status);
  176. dma_cookie_complete(tx_desc);
  177. dma_descriptor_unmap(tx_desc);
  178. }
  179. desc = __ccp_next_dma_desc(chan, desc);
  180. spin_unlock_irqrestore(&chan->lock, flags);
  181. if (tx_desc) {
  182. dmaengine_desc_get_callback_invoke(tx_desc, NULL);
  183. dma_run_dependencies(tx_desc);
  184. }
  185. } while (desc);
  186. return NULL;
  187. }
  188. static struct ccp_dma_desc *__ccp_pending_to_active(struct ccp_dma_chan *chan)
  189. {
  190. struct ccp_dma_desc *desc;
  191. if (list_empty(&chan->pending))
  192. return NULL;
  193. desc = list_empty(&chan->active)
  194. ? list_first_entry(&chan->pending, struct ccp_dma_desc, entry)
  195. : NULL;
  196. list_splice_tail_init(&chan->pending, &chan->active);
  197. return desc;
  198. }
  199. static void ccp_cmd_callback(void *data, int err)
  200. {
  201. struct ccp_dma_desc *desc = data;
  202. struct ccp_dma_chan *chan;
  203. int ret;
  204. if (err == -EINPROGRESS)
  205. return;
  206. chan = container_of(desc->tx_desc.chan, struct ccp_dma_chan,
  207. dma_chan);
  208. dev_dbg(chan->ccp->dev, "%s - tx %d callback, err=%d\n",
  209. __func__, desc->tx_desc.cookie, err);
  210. if (err)
  211. desc->status = DMA_ERROR;
  212. while (true) {
  213. /* Check for DMA descriptor completion */
  214. desc = ccp_handle_active_desc(chan, desc);
  215. /* Don't submit cmd if no descriptor or DMA is paused */
  216. if (!desc || (chan->status == DMA_PAUSED))
  217. break;
  218. ret = ccp_issue_next_cmd(desc);
  219. if (!ret)
  220. break;
  221. desc->status = DMA_ERROR;
  222. }
  223. tasklet_schedule(&chan->cleanup_tasklet);
  224. }
  225. static dma_cookie_t ccp_tx_submit(struct dma_async_tx_descriptor *tx_desc)
  226. {
  227. struct ccp_dma_desc *desc = container_of(tx_desc, struct ccp_dma_desc,
  228. tx_desc);
  229. struct ccp_dma_chan *chan;
  230. dma_cookie_t cookie;
  231. unsigned long flags;
  232. chan = container_of(tx_desc->chan, struct ccp_dma_chan, dma_chan);
  233. spin_lock_irqsave(&chan->lock, flags);
  234. cookie = dma_cookie_assign(tx_desc);
  235. list_move_tail(&desc->entry, &chan->pending);
  236. spin_unlock_irqrestore(&chan->lock, flags);
  237. dev_dbg(chan->ccp->dev, "%s - added tx descriptor %d to pending list\n",
  238. __func__, cookie);
  239. return cookie;
  240. }
  241. static struct ccp_dma_cmd *ccp_alloc_dma_cmd(struct ccp_dma_chan *chan)
  242. {
  243. struct ccp_dma_cmd *cmd;
  244. cmd = kmem_cache_alloc(chan->ccp->dma_cmd_cache, GFP_NOWAIT);
  245. if (cmd)
  246. memset(cmd, 0, sizeof(*cmd));
  247. return cmd;
  248. }
  249. static struct ccp_dma_desc *ccp_alloc_dma_desc(struct ccp_dma_chan *chan,
  250. unsigned long flags)
  251. {
  252. struct ccp_dma_desc *desc;
  253. desc = kmem_cache_zalloc(chan->ccp->dma_desc_cache, GFP_NOWAIT);
  254. if (!desc)
  255. return NULL;
  256. dma_async_tx_descriptor_init(&desc->tx_desc, &chan->dma_chan);
  257. desc->tx_desc.flags = flags;
  258. desc->tx_desc.tx_submit = ccp_tx_submit;
  259. desc->ccp = chan->ccp;
  260. INIT_LIST_HEAD(&desc->entry);
  261. INIT_LIST_HEAD(&desc->pending);
  262. INIT_LIST_HEAD(&desc->active);
  263. desc->status = DMA_IN_PROGRESS;
  264. return desc;
  265. }
  266. static struct ccp_dma_desc *ccp_create_desc(struct dma_chan *dma_chan,
  267. struct scatterlist *dst_sg,
  268. unsigned int dst_nents,
  269. struct scatterlist *src_sg,
  270. unsigned int src_nents,
  271. unsigned long flags)
  272. {
  273. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  274. dma_chan);
  275. struct ccp_device *ccp = chan->ccp;
  276. struct ccp_dma_desc *desc;
  277. struct ccp_dma_cmd *cmd;
  278. struct ccp_cmd *ccp_cmd;
  279. struct ccp_passthru_nomap_engine *ccp_pt;
  280. unsigned int src_offset, src_len;
  281. unsigned int dst_offset, dst_len;
  282. unsigned int len;
  283. unsigned long sflags;
  284. size_t total_len;
  285. if (!dst_sg || !src_sg)
  286. return NULL;
  287. if (!dst_nents || !src_nents)
  288. return NULL;
  289. desc = ccp_alloc_dma_desc(chan, flags);
  290. if (!desc)
  291. return NULL;
  292. total_len = 0;
  293. src_len = sg_dma_len(src_sg);
  294. src_offset = 0;
  295. dst_len = sg_dma_len(dst_sg);
  296. dst_offset = 0;
  297. while (true) {
  298. if (!src_len) {
  299. src_nents--;
  300. if (!src_nents)
  301. break;
  302. src_sg = sg_next(src_sg);
  303. if (!src_sg)
  304. break;
  305. src_len = sg_dma_len(src_sg);
  306. src_offset = 0;
  307. continue;
  308. }
  309. if (!dst_len) {
  310. dst_nents--;
  311. if (!dst_nents)
  312. break;
  313. dst_sg = sg_next(dst_sg);
  314. if (!dst_sg)
  315. break;
  316. dst_len = sg_dma_len(dst_sg);
  317. dst_offset = 0;
  318. continue;
  319. }
  320. len = min(dst_len, src_len);
  321. cmd = ccp_alloc_dma_cmd(chan);
  322. if (!cmd)
  323. goto err;
  324. ccp_cmd = &cmd->ccp_cmd;
  325. ccp_cmd->ccp = chan->ccp;
  326. ccp_pt = &ccp_cmd->u.passthru_nomap;
  327. ccp_cmd->flags = CCP_CMD_MAY_BACKLOG;
  328. ccp_cmd->flags |= CCP_CMD_PASSTHRU_NO_DMA_MAP;
  329. ccp_cmd->engine = CCP_ENGINE_PASSTHRU;
  330. ccp_pt->bit_mod = CCP_PASSTHRU_BITWISE_NOOP;
  331. ccp_pt->byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;
  332. ccp_pt->src_dma = sg_dma_address(src_sg) + src_offset;
  333. ccp_pt->dst_dma = sg_dma_address(dst_sg) + dst_offset;
  334. ccp_pt->src_len = len;
  335. ccp_pt->final = 1;
  336. ccp_cmd->callback = ccp_cmd_callback;
  337. ccp_cmd->data = desc;
  338. list_add_tail(&cmd->entry, &desc->pending);
  339. dev_dbg(ccp->dev,
  340. "%s - cmd=%p, src=%pad, dst=%pad, len=%llu\n", __func__,
  341. cmd, &ccp_pt->src_dma,
  342. &ccp_pt->dst_dma, ccp_pt->src_len);
  343. total_len += len;
  344. src_len -= len;
  345. src_offset += len;
  346. dst_len -= len;
  347. dst_offset += len;
  348. }
  349. desc->len = total_len;
  350. if (list_empty(&desc->pending))
  351. goto err;
  352. dev_dbg(ccp->dev, "%s - desc=%p\n", __func__, desc);
  353. spin_lock_irqsave(&chan->lock, sflags);
  354. list_add_tail(&desc->entry, &chan->created);
  355. spin_unlock_irqrestore(&chan->lock, sflags);
  356. return desc;
  357. err:
  358. ccp_free_cmd_resources(ccp, &desc->pending);
  359. kmem_cache_free(ccp->dma_desc_cache, desc);
  360. return NULL;
  361. }
  362. static struct dma_async_tx_descriptor *ccp_prep_dma_memcpy(
  363. struct dma_chan *dma_chan, dma_addr_t dst, dma_addr_t src, size_t len,
  364. unsigned long flags)
  365. {
  366. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  367. dma_chan);
  368. struct ccp_dma_desc *desc;
  369. struct scatterlist dst_sg, src_sg;
  370. dev_dbg(chan->ccp->dev,
  371. "%s - src=%pad, dst=%pad, len=%zu, flags=%#lx\n",
  372. __func__, &src, &dst, len, flags);
  373. sg_init_table(&dst_sg, 1);
  374. sg_dma_address(&dst_sg) = dst;
  375. sg_dma_len(&dst_sg) = len;
  376. sg_init_table(&src_sg, 1);
  377. sg_dma_address(&src_sg) = src;
  378. sg_dma_len(&src_sg) = len;
  379. desc = ccp_create_desc(dma_chan, &dst_sg, 1, &src_sg, 1, flags);
  380. if (!desc)
  381. return NULL;
  382. return &desc->tx_desc;
  383. }
  384. static struct dma_async_tx_descriptor *ccp_prep_dma_interrupt(
  385. struct dma_chan *dma_chan, unsigned long flags)
  386. {
  387. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  388. dma_chan);
  389. struct ccp_dma_desc *desc;
  390. desc = ccp_alloc_dma_desc(chan, flags);
  391. if (!desc)
  392. return NULL;
  393. return &desc->tx_desc;
  394. }
  395. static void ccp_issue_pending(struct dma_chan *dma_chan)
  396. {
  397. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  398. dma_chan);
  399. struct ccp_dma_desc *desc;
  400. unsigned long flags;
  401. dev_dbg(chan->ccp->dev, "%s\n", __func__);
  402. spin_lock_irqsave(&chan->lock, flags);
  403. desc = __ccp_pending_to_active(chan);
  404. spin_unlock_irqrestore(&chan->lock, flags);
  405. /* If there was nothing active, start processing */
  406. if (desc)
  407. ccp_cmd_callback(desc, 0);
  408. }
  409. static enum dma_status ccp_tx_status(struct dma_chan *dma_chan,
  410. dma_cookie_t cookie,
  411. struct dma_tx_state *state)
  412. {
  413. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  414. dma_chan);
  415. struct ccp_dma_desc *desc;
  416. enum dma_status ret;
  417. unsigned long flags;
  418. if (chan->status == DMA_PAUSED) {
  419. ret = DMA_PAUSED;
  420. goto out;
  421. }
  422. ret = dma_cookie_status(dma_chan, cookie, state);
  423. if (ret == DMA_COMPLETE) {
  424. spin_lock_irqsave(&chan->lock, flags);
  425. /* Get status from complete chain, if still there */
  426. list_for_each_entry(desc, &chan->complete, entry) {
  427. if (desc->tx_desc.cookie != cookie)
  428. continue;
  429. ret = desc->status;
  430. break;
  431. }
  432. spin_unlock_irqrestore(&chan->lock, flags);
  433. }
  434. out:
  435. dev_dbg(chan->ccp->dev, "%s - %u\n", __func__, ret);
  436. return ret;
  437. }
  438. static int ccp_pause(struct dma_chan *dma_chan)
  439. {
  440. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  441. dma_chan);
  442. chan->status = DMA_PAUSED;
  443. /*TODO: Wait for active DMA to complete before returning? */
  444. return 0;
  445. }
  446. static int ccp_resume(struct dma_chan *dma_chan)
  447. {
  448. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  449. dma_chan);
  450. struct ccp_dma_desc *desc;
  451. unsigned long flags;
  452. spin_lock_irqsave(&chan->lock, flags);
  453. desc = list_first_entry_or_null(&chan->active, struct ccp_dma_desc,
  454. entry);
  455. spin_unlock_irqrestore(&chan->lock, flags);
  456. /* Indicate the channel is running again */
  457. chan->status = DMA_IN_PROGRESS;
  458. /* If there was something active, re-start */
  459. if (desc)
  460. ccp_cmd_callback(desc, 0);
  461. return 0;
  462. }
  463. static int ccp_terminate_all(struct dma_chan *dma_chan)
  464. {
  465. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  466. dma_chan);
  467. unsigned long flags;
  468. dev_dbg(chan->ccp->dev, "%s\n", __func__);
  469. /*TODO: Wait for active DMA to complete before continuing */
  470. spin_lock_irqsave(&chan->lock, flags);
  471. /*TODO: Purge the complete list? */
  472. ccp_free_desc_resources(chan->ccp, &chan->active);
  473. ccp_free_desc_resources(chan->ccp, &chan->pending);
  474. ccp_free_desc_resources(chan->ccp, &chan->created);
  475. spin_unlock_irqrestore(&chan->lock, flags);
  476. return 0;
  477. }
  478. static void ccp_dma_release(struct ccp_device *ccp)
  479. {
  480. struct ccp_dma_chan *chan;
  481. struct dma_chan *dma_chan;
  482. unsigned int i;
  483. for (i = 0; i < ccp->cmd_q_count; i++) {
  484. chan = ccp->ccp_dma_chan + i;
  485. dma_chan = &chan->dma_chan;
  486. tasklet_kill(&chan->cleanup_tasklet);
  487. list_del_rcu(&dma_chan->device_node);
  488. }
  489. }
  490. static void ccp_dma_release_channels(struct ccp_device *ccp)
  491. {
  492. struct ccp_dma_chan *chan;
  493. struct dma_chan *dma_chan;
  494. unsigned int i;
  495. for (i = 0; i < ccp->cmd_q_count; i++) {
  496. chan = ccp->ccp_dma_chan + i;
  497. dma_chan = &chan->dma_chan;
  498. if (dma_chan->client_count)
  499. dma_release_channel(dma_chan);
  500. }
  501. }
  502. int ccp_dmaengine_register(struct ccp_device *ccp)
  503. {
  504. struct ccp_dma_chan *chan;
  505. struct dma_device *dma_dev = &ccp->dma_dev;
  506. struct dma_chan *dma_chan;
  507. char *dma_cmd_cache_name;
  508. char *dma_desc_cache_name;
  509. unsigned int i;
  510. int ret;
  511. if (!dmaengine)
  512. return 0;
  513. ccp->ccp_dma_chan = devm_kcalloc(ccp->dev, ccp->cmd_q_count,
  514. sizeof(*(ccp->ccp_dma_chan)),
  515. GFP_KERNEL);
  516. if (!ccp->ccp_dma_chan)
  517. return -ENOMEM;
  518. dma_cmd_cache_name = devm_kasprintf(ccp->dev, GFP_KERNEL,
  519. "%s-dmaengine-cmd-cache",
  520. ccp->name);
  521. if (!dma_cmd_cache_name)
  522. return -ENOMEM;
  523. ccp->dma_cmd_cache = kmem_cache_create(dma_cmd_cache_name,
  524. sizeof(struct ccp_dma_cmd),
  525. sizeof(void *),
  526. SLAB_HWCACHE_ALIGN, NULL);
  527. if (!ccp->dma_cmd_cache)
  528. return -ENOMEM;
  529. dma_desc_cache_name = devm_kasprintf(ccp->dev, GFP_KERNEL,
  530. "%s-dmaengine-desc-cache",
  531. ccp->name);
  532. if (!dma_desc_cache_name) {
  533. ret = -ENOMEM;
  534. goto err_cache;
  535. }
  536. ccp->dma_desc_cache = kmem_cache_create(dma_desc_cache_name,
  537. sizeof(struct ccp_dma_desc),
  538. sizeof(void *),
  539. SLAB_HWCACHE_ALIGN, NULL);
  540. if (!ccp->dma_desc_cache) {
  541. ret = -ENOMEM;
  542. goto err_cache;
  543. }
  544. dma_dev->dev = ccp->dev;
  545. dma_dev->src_addr_widths = CCP_DMA_WIDTH(dma_get_mask(ccp->dev));
  546. dma_dev->dst_addr_widths = CCP_DMA_WIDTH(dma_get_mask(ccp->dev));
  547. dma_dev->directions = DMA_MEM_TO_MEM;
  548. dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
  549. dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
  550. dma_cap_set(DMA_INTERRUPT, dma_dev->cap_mask);
  551. /* The DMA channels for this device can be set to public or private,
  552. * and overridden by the module parameter dma_chan_attr.
  553. * Default: according to the value in vdata (dma_chan_attr=0)
  554. * dma_chan_attr=0x1: all channels private (override vdata)
  555. * dma_chan_attr=0x2: all channels public (override vdata)
  556. */
  557. if (ccp_get_dma_chan_attr(ccp) == DMA_PRIVATE)
  558. dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
  559. INIT_LIST_HEAD(&dma_dev->channels);
  560. for (i = 0; i < ccp->cmd_q_count; i++) {
  561. chan = ccp->ccp_dma_chan + i;
  562. dma_chan = &chan->dma_chan;
  563. chan->ccp = ccp;
  564. spin_lock_init(&chan->lock);
  565. INIT_LIST_HEAD(&chan->created);
  566. INIT_LIST_HEAD(&chan->pending);
  567. INIT_LIST_HEAD(&chan->active);
  568. INIT_LIST_HEAD(&chan->complete);
  569. tasklet_init(&chan->cleanup_tasklet, ccp_do_cleanup,
  570. (unsigned long)chan);
  571. dma_chan->device = dma_dev;
  572. dma_cookie_init(dma_chan);
  573. list_add_tail(&dma_chan->device_node, &dma_dev->channels);
  574. }
  575. dma_dev->device_free_chan_resources = ccp_free_chan_resources;
  576. dma_dev->device_prep_dma_memcpy = ccp_prep_dma_memcpy;
  577. dma_dev->device_prep_dma_interrupt = ccp_prep_dma_interrupt;
  578. dma_dev->device_issue_pending = ccp_issue_pending;
  579. dma_dev->device_tx_status = ccp_tx_status;
  580. dma_dev->device_pause = ccp_pause;
  581. dma_dev->device_resume = ccp_resume;
  582. dma_dev->device_terminate_all = ccp_terminate_all;
  583. ret = dma_async_device_register(dma_dev);
  584. if (ret)
  585. goto err_reg;
  586. return 0;
  587. err_reg:
  588. ccp_dma_release(ccp);
  589. kmem_cache_destroy(ccp->dma_desc_cache);
  590. err_cache:
  591. kmem_cache_destroy(ccp->dma_cmd_cache);
  592. return ret;
  593. }
  594. void ccp_dmaengine_unregister(struct ccp_device *ccp)
  595. {
  596. struct dma_device *dma_dev = &ccp->dma_dev;
  597. if (!dmaengine)
  598. return;
  599. ccp_dma_release_channels(ccp);
  600. dma_async_device_unregister(dma_dev);
  601. ccp_dma_release(ccp);
  602. kmem_cache_destroy(ccp->dma_desc_cache);
  603. kmem_cache_destroy(ccp->dma_cmd_cache);
  604. }