ftm-quaddec.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Flex Timer Module Quadrature decoder
  4. *
  5. * This module implements a driver for decoding the FTM quadrature
  6. * of ex. a LS1021A
  7. */
  8. #include <linux/fsl/ftm.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/of.h>
  12. #include <linux/io.h>
  13. #include <linux/mutex.h>
  14. #include <linux/counter.h>
  15. #include <linux/bitfield.h>
  16. #include <linux/types.h>
  17. #define FTM_FIELD_UPDATE(ftm, offset, mask, val) \
  18. ({ \
  19. uint32_t flags; \
  20. ftm_read(ftm, offset, &flags); \
  21. flags &= ~mask; \
  22. flags |= FIELD_PREP(mask, val); \
  23. ftm_write(ftm, offset, flags); \
  24. })
  25. struct ftm_quaddec {
  26. struct platform_device *pdev;
  27. void __iomem *ftm_base;
  28. bool big_endian;
  29. struct mutex ftm_quaddec_mutex;
  30. };
  31. static void ftm_read(struct ftm_quaddec *ftm, uint32_t offset, uint32_t *data)
  32. {
  33. if (ftm->big_endian)
  34. *data = ioread32be(ftm->ftm_base + offset);
  35. else
  36. *data = ioread32(ftm->ftm_base + offset);
  37. }
  38. static void ftm_write(struct ftm_quaddec *ftm, uint32_t offset, uint32_t data)
  39. {
  40. if (ftm->big_endian)
  41. iowrite32be(data, ftm->ftm_base + offset);
  42. else
  43. iowrite32(data, ftm->ftm_base + offset);
  44. }
  45. /* Hold mutex before modifying write protection state */
  46. static void ftm_clear_write_protection(struct ftm_quaddec *ftm)
  47. {
  48. uint32_t flag;
  49. /* First see if it is enabled */
  50. ftm_read(ftm, FTM_FMS, &flag);
  51. if (flag & FTM_FMS_WPEN)
  52. FTM_FIELD_UPDATE(ftm, FTM_MODE, FTM_MODE_WPDIS, 1);
  53. }
  54. static void ftm_set_write_protection(struct ftm_quaddec *ftm)
  55. {
  56. FTM_FIELD_UPDATE(ftm, FTM_FMS, FTM_FMS_WPEN, 1);
  57. }
  58. static void ftm_reset_counter(struct ftm_quaddec *ftm)
  59. {
  60. /* Reset hardware counter to CNTIN */
  61. ftm_write(ftm, FTM_CNT, 0x0);
  62. }
  63. static void ftm_quaddec_init(struct ftm_quaddec *ftm)
  64. {
  65. ftm_clear_write_protection(ftm);
  66. /*
  67. * Do not write in the region from the CNTIN register through the
  68. * PWMLOAD register when FTMEN = 0.
  69. * Also reset other fields to zero
  70. */
  71. ftm_write(ftm, FTM_MODE, FTM_MODE_FTMEN);
  72. ftm_write(ftm, FTM_CNTIN, 0x0000);
  73. ftm_write(ftm, FTM_MOD, 0xffff);
  74. ftm_write(ftm, FTM_CNT, 0x0);
  75. /* Set prescaler, reset other fields to zero */
  76. ftm_write(ftm, FTM_SC, FTM_SC_PS_1);
  77. /* Select quad mode, reset other fields to zero */
  78. ftm_write(ftm, FTM_QDCTRL, FTM_QDCTRL_QUADEN);
  79. /* Unused features and reset to default section */
  80. ftm_write(ftm, FTM_POL, 0x0);
  81. ftm_write(ftm, FTM_FLTCTRL, 0x0);
  82. ftm_write(ftm, FTM_SYNCONF, 0x0);
  83. ftm_write(ftm, FTM_SYNC, 0xffff);
  84. /* Lock the FTM */
  85. ftm_set_write_protection(ftm);
  86. }
  87. static void ftm_quaddec_disable(void *ftm)
  88. {
  89. struct ftm_quaddec *ftm_qua = ftm;
  90. ftm_clear_write_protection(ftm_qua);
  91. ftm_write(ftm_qua, FTM_MODE, 0);
  92. ftm_write(ftm_qua, FTM_QDCTRL, 0);
  93. /*
  94. * This is enough to disable the counter. No clock has been
  95. * selected by writing to FTM_SC in init()
  96. */
  97. ftm_set_write_protection(ftm_qua);
  98. }
  99. static int ftm_quaddec_get_prescaler(struct counter_device *counter,
  100. struct counter_count *count, u32 *cnt_mode)
  101. {
  102. struct ftm_quaddec *ftm = counter_priv(counter);
  103. uint32_t scflags;
  104. ftm_read(ftm, FTM_SC, &scflags);
  105. *cnt_mode = FIELD_GET(FTM_SC_PS_MASK, scflags);
  106. return 0;
  107. }
  108. static int ftm_quaddec_set_prescaler(struct counter_device *counter,
  109. struct counter_count *count, u32 cnt_mode)
  110. {
  111. struct ftm_quaddec *ftm = counter_priv(counter);
  112. mutex_lock(&ftm->ftm_quaddec_mutex);
  113. ftm_clear_write_protection(ftm);
  114. FTM_FIELD_UPDATE(ftm, FTM_SC, FTM_SC_PS_MASK, cnt_mode);
  115. ftm_set_write_protection(ftm);
  116. /* Also resets the counter as it is undefined anyway now */
  117. ftm_reset_counter(ftm);
  118. mutex_unlock(&ftm->ftm_quaddec_mutex);
  119. return 0;
  120. }
  121. static const char * const ftm_quaddec_prescaler[] = {
  122. "1", "2", "4", "8", "16", "32", "64", "128"
  123. };
  124. static const enum counter_synapse_action ftm_quaddec_synapse_actions[] = {
  125. COUNTER_SYNAPSE_ACTION_BOTH_EDGES
  126. };
  127. static const enum counter_function ftm_quaddec_count_functions[] = {
  128. COUNTER_FUNCTION_QUADRATURE_X4
  129. };
  130. static int ftm_quaddec_count_read(struct counter_device *counter,
  131. struct counter_count *count,
  132. u64 *val)
  133. {
  134. struct ftm_quaddec *const ftm = counter_priv(counter);
  135. uint32_t cntval;
  136. ftm_read(ftm, FTM_CNT, &cntval);
  137. *val = cntval;
  138. return 0;
  139. }
  140. static int ftm_quaddec_count_write(struct counter_device *counter,
  141. struct counter_count *count,
  142. const u64 val)
  143. {
  144. struct ftm_quaddec *const ftm = counter_priv(counter);
  145. if (val != 0) {
  146. dev_warn(&ftm->pdev->dev, "Can only accept '0' as new counter value\n");
  147. return -EINVAL;
  148. }
  149. ftm_reset_counter(ftm);
  150. return 0;
  151. }
  152. static int ftm_quaddec_count_function_read(struct counter_device *counter,
  153. struct counter_count *count,
  154. enum counter_function *function)
  155. {
  156. *function = COUNTER_FUNCTION_QUADRATURE_X4;
  157. return 0;
  158. }
  159. static int ftm_quaddec_action_read(struct counter_device *counter,
  160. struct counter_count *count,
  161. struct counter_synapse *synapse,
  162. enum counter_synapse_action *action)
  163. {
  164. *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
  165. return 0;
  166. }
  167. static const struct counter_ops ftm_quaddec_cnt_ops = {
  168. .count_read = ftm_quaddec_count_read,
  169. .count_write = ftm_quaddec_count_write,
  170. .function_read = ftm_quaddec_count_function_read,
  171. .action_read = ftm_quaddec_action_read,
  172. };
  173. static struct counter_signal ftm_quaddec_signals[] = {
  174. {
  175. .id = 0,
  176. .name = "Channel 1 Phase A"
  177. },
  178. {
  179. .id = 1,
  180. .name = "Channel 1 Phase B"
  181. }
  182. };
  183. static struct counter_synapse ftm_quaddec_count_synapses[] = {
  184. {
  185. .actions_list = ftm_quaddec_synapse_actions,
  186. .num_actions = ARRAY_SIZE(ftm_quaddec_synapse_actions),
  187. .signal = &ftm_quaddec_signals[0]
  188. },
  189. {
  190. .actions_list = ftm_quaddec_synapse_actions,
  191. .num_actions = ARRAY_SIZE(ftm_quaddec_synapse_actions),
  192. .signal = &ftm_quaddec_signals[1]
  193. }
  194. };
  195. static DEFINE_COUNTER_ENUM(ftm_quaddec_prescaler_enum, ftm_quaddec_prescaler);
  196. static struct counter_comp ftm_quaddec_count_ext[] = {
  197. COUNTER_COMP_COUNT_ENUM("prescaler", ftm_quaddec_get_prescaler,
  198. ftm_quaddec_set_prescaler,
  199. ftm_quaddec_prescaler_enum),
  200. };
  201. static struct counter_count ftm_quaddec_counts = {
  202. .id = 0,
  203. .name = "Channel 1 Count",
  204. .functions_list = ftm_quaddec_count_functions,
  205. .num_functions = ARRAY_SIZE(ftm_quaddec_count_functions),
  206. .synapses = ftm_quaddec_count_synapses,
  207. .num_synapses = ARRAY_SIZE(ftm_quaddec_count_synapses),
  208. .ext = ftm_quaddec_count_ext,
  209. .num_ext = ARRAY_SIZE(ftm_quaddec_count_ext)
  210. };
  211. static int ftm_quaddec_probe(struct platform_device *pdev)
  212. {
  213. struct counter_device *counter;
  214. struct ftm_quaddec *ftm;
  215. struct device_node *node = pdev->dev.of_node;
  216. struct resource *io;
  217. int ret;
  218. counter = devm_counter_alloc(&pdev->dev, sizeof(*ftm));
  219. if (!counter)
  220. return -ENOMEM;
  221. ftm = counter_priv(counter);
  222. io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  223. if (!io) {
  224. dev_err(&pdev->dev, "Failed to get memory region\n");
  225. return -ENODEV;
  226. }
  227. ftm->pdev = pdev;
  228. ftm->big_endian = of_property_read_bool(node, "big-endian");
  229. ftm->ftm_base = devm_ioremap(&pdev->dev, io->start, resource_size(io));
  230. if (!ftm->ftm_base) {
  231. dev_err(&pdev->dev, "Failed to map memory region\n");
  232. return -EINVAL;
  233. }
  234. counter->name = dev_name(&pdev->dev);
  235. counter->parent = &pdev->dev;
  236. counter->ops = &ftm_quaddec_cnt_ops;
  237. counter->counts = &ftm_quaddec_counts;
  238. counter->num_counts = 1;
  239. counter->signals = ftm_quaddec_signals;
  240. counter->num_signals = ARRAY_SIZE(ftm_quaddec_signals);
  241. mutex_init(&ftm->ftm_quaddec_mutex);
  242. ftm_quaddec_init(ftm);
  243. ret = devm_add_action_or_reset(&pdev->dev, ftm_quaddec_disable, ftm);
  244. if (ret)
  245. return ret;
  246. ret = devm_counter_add(&pdev->dev, counter);
  247. if (ret)
  248. return dev_err_probe(&pdev->dev, ret, "Failed to add counter\n");
  249. return 0;
  250. }
  251. static const struct of_device_id ftm_quaddec_match[] = {
  252. { .compatible = "fsl,ftm-quaddec" },
  253. {},
  254. };
  255. static struct platform_driver ftm_quaddec_driver = {
  256. .driver = {
  257. .name = "ftm-quaddec",
  258. .of_match_table = ftm_quaddec_match,
  259. },
  260. .probe = ftm_quaddec_probe,
  261. };
  262. module_platform_driver(ftm_quaddec_driver);
  263. MODULE_LICENSE("GPL");
  264. MODULE_AUTHOR("Kjeld Flarup <[email protected]>");
  265. MODULE_AUTHOR("Patrick Havelange <[email protected]>");
  266. MODULE_IMPORT_NS(COUNTER);