clk-sunxi.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Emilio López
  4. *
  5. * Emilio López <[email protected]>
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/clkdev.h>
  10. #include <linux/io.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <linux/reset-controller.h>
  14. #include <linux/slab.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/log2.h>
  17. #include "clk-factors.h"
  18. static DEFINE_SPINLOCK(clk_lock);
  19. /* Maximum number of parents our clocks have */
  20. #define SUNXI_MAX_PARENTS 5
  21. /*
  22. * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
  23. * PLL1 rate is calculated as follows
  24. * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
  25. * parent_rate is always 24Mhz
  26. */
  27. static void sun4i_get_pll1_factors(struct factors_request *req)
  28. {
  29. u8 div;
  30. /* Normalize value to a 6M multiple */
  31. div = req->rate / 6000000;
  32. req->rate = 6000000 * div;
  33. /* m is always zero for pll1 */
  34. req->m = 0;
  35. /* k is 1 only on these cases */
  36. if (req->rate >= 768000000 || req->rate == 42000000 ||
  37. req->rate == 54000000)
  38. req->k = 1;
  39. else
  40. req->k = 0;
  41. /* p will be 3 for divs under 10 */
  42. if (div < 10)
  43. req->p = 3;
  44. /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
  45. else if (div < 20 || (div < 32 && (div & 1)))
  46. req->p = 2;
  47. /* p will be 1 for even divs under 32, divs under 40 and odd pairs
  48. * of divs between 40-62 */
  49. else if (div < 40 || (div < 64 && (div & 2)))
  50. req->p = 1;
  51. /* any other entries have p = 0 */
  52. else
  53. req->p = 0;
  54. /* calculate a suitable n based on k and p */
  55. div <<= req->p;
  56. div /= (req->k + 1);
  57. req->n = div / 4;
  58. }
  59. /*
  60. * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
  61. * PLL1 rate is calculated as follows
  62. * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
  63. * parent_rate should always be 24MHz
  64. */
  65. static void sun6i_a31_get_pll1_factors(struct factors_request *req)
  66. {
  67. /*
  68. * We can operate only on MHz, this will make our life easier
  69. * later.
  70. */
  71. u32 freq_mhz = req->rate / 1000000;
  72. u32 parent_freq_mhz = req->parent_rate / 1000000;
  73. /*
  74. * Round down the frequency to the closest multiple of either
  75. * 6 or 16
  76. */
  77. u32 round_freq_6 = rounddown(freq_mhz, 6);
  78. u32 round_freq_16 = round_down(freq_mhz, 16);
  79. if (round_freq_6 > round_freq_16)
  80. freq_mhz = round_freq_6;
  81. else
  82. freq_mhz = round_freq_16;
  83. req->rate = freq_mhz * 1000000;
  84. /* If the frequency is a multiple of 32 MHz, k is always 3 */
  85. if (!(freq_mhz % 32))
  86. req->k = 3;
  87. /* If the frequency is a multiple of 9 MHz, k is always 2 */
  88. else if (!(freq_mhz % 9))
  89. req->k = 2;
  90. /* If the frequency is a multiple of 8 MHz, k is always 1 */
  91. else if (!(freq_mhz % 8))
  92. req->k = 1;
  93. /* Otherwise, we don't use the k factor */
  94. else
  95. req->k = 0;
  96. /*
  97. * If the frequency is a multiple of 2 but not a multiple of
  98. * 3, m is 3. This is the first time we use 6 here, yet we
  99. * will use it on several other places.
  100. * We use this number because it's the lowest frequency we can
  101. * generate (with n = 0, k = 0, m = 3), so every other frequency
  102. * somehow relates to this frequency.
  103. */
  104. if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
  105. req->m = 2;
  106. /*
  107. * If the frequency is a multiple of 6MHz, but the factor is
  108. * odd, m will be 3
  109. */
  110. else if ((freq_mhz / 6) & 1)
  111. req->m = 3;
  112. /* Otherwise, we end up with m = 1 */
  113. else
  114. req->m = 1;
  115. /* Calculate n thanks to the above factors we already got */
  116. req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz)
  117. - 1;
  118. /*
  119. * If n end up being outbound, and that we can still decrease
  120. * m, do it.
  121. */
  122. if ((req->n + 1) > 31 && (req->m + 1) > 1) {
  123. req->n = (req->n + 1) / 2 - 1;
  124. req->m = (req->m + 1) / 2 - 1;
  125. }
  126. }
  127. /*
  128. * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
  129. * PLL1 rate is calculated as follows
  130. * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
  131. * parent_rate is always 24Mhz
  132. */
  133. static void sun8i_a23_get_pll1_factors(struct factors_request *req)
  134. {
  135. u8 div;
  136. /* Normalize value to a 6M multiple */
  137. div = req->rate / 6000000;
  138. req->rate = 6000000 * div;
  139. /* m is always zero for pll1 */
  140. req->m = 0;
  141. /* k is 1 only on these cases */
  142. if (req->rate >= 768000000 || req->rate == 42000000 ||
  143. req->rate == 54000000)
  144. req->k = 1;
  145. else
  146. req->k = 0;
  147. /* p will be 2 for divs under 20 and odd divs under 32 */
  148. if (div < 20 || (div < 32 && (div & 1)))
  149. req->p = 2;
  150. /* p will be 1 for even divs under 32, divs under 40 and odd pairs
  151. * of divs between 40-62 */
  152. else if (div < 40 || (div < 64 && (div & 2)))
  153. req->p = 1;
  154. /* any other entries have p = 0 */
  155. else
  156. req->p = 0;
  157. /* calculate a suitable n based on k and p */
  158. div <<= req->p;
  159. div /= (req->k + 1);
  160. req->n = div / 4 - 1;
  161. }
  162. /*
  163. * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
  164. * PLL5 rate is calculated as follows
  165. * rate = parent_rate * n * (k + 1)
  166. * parent_rate is always 24Mhz
  167. */
  168. static void sun4i_get_pll5_factors(struct factors_request *req)
  169. {
  170. u8 div;
  171. /* Normalize value to a parent_rate multiple (24M) */
  172. div = req->rate / req->parent_rate;
  173. req->rate = req->parent_rate * div;
  174. if (div < 31)
  175. req->k = 0;
  176. else if (div / 2 < 31)
  177. req->k = 1;
  178. else if (div / 3 < 31)
  179. req->k = 2;
  180. else
  181. req->k = 3;
  182. req->n = DIV_ROUND_UP(div, (req->k + 1));
  183. }
  184. /*
  185. * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
  186. * PLL6x2 rate is calculated as follows
  187. * rate = parent_rate * (n + 1) * (k + 1)
  188. * parent_rate is always 24Mhz
  189. */
  190. static void sun6i_a31_get_pll6_factors(struct factors_request *req)
  191. {
  192. u8 div;
  193. /* Normalize value to a parent_rate multiple (24M) */
  194. div = req->rate / req->parent_rate;
  195. req->rate = req->parent_rate * div;
  196. req->k = div / 32;
  197. if (req->k > 3)
  198. req->k = 3;
  199. req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1;
  200. }
  201. /*
  202. * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
  203. * AHB rate is calculated as follows
  204. * rate = parent_rate >> p
  205. */
  206. static void sun5i_a13_get_ahb_factors(struct factors_request *req)
  207. {
  208. u32 div;
  209. /* divide only */
  210. if (req->parent_rate < req->rate)
  211. req->rate = req->parent_rate;
  212. /*
  213. * user manual says valid speed is 8k ~ 276M, but tests show it
  214. * can work at speeds up to 300M, just after reparenting to pll6
  215. */
  216. if (req->rate < 8000)
  217. req->rate = 8000;
  218. if (req->rate > 300000000)
  219. req->rate = 300000000;
  220. div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate));
  221. /* p = 0 ~ 3 */
  222. if (div > 3)
  223. div = 3;
  224. req->rate = req->parent_rate >> div;
  225. req->p = div;
  226. }
  227. #define SUN6I_AHB1_PARENT_PLL6 3
  228. /*
  229. * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
  230. * AHB rate is calculated as follows
  231. * rate = parent_rate >> p
  232. *
  233. * if parent is pll6, then
  234. * parent_rate = pll6 rate / (m + 1)
  235. */
  236. static void sun6i_get_ahb1_factors(struct factors_request *req)
  237. {
  238. u8 div, calcp, calcm = 1;
  239. /*
  240. * clock can only divide, so we will never be able to achieve
  241. * frequencies higher than the parent frequency
  242. */
  243. if (req->parent_rate && req->rate > req->parent_rate)
  244. req->rate = req->parent_rate;
  245. div = DIV_ROUND_UP(req->parent_rate, req->rate);
  246. /* calculate pre-divider if parent is pll6 */
  247. if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
  248. if (div < 4)
  249. calcp = 0;
  250. else if (div / 2 < 4)
  251. calcp = 1;
  252. else if (div / 4 < 4)
  253. calcp = 2;
  254. else
  255. calcp = 3;
  256. calcm = DIV_ROUND_UP(div, 1 << calcp);
  257. } else {
  258. calcp = __roundup_pow_of_two(div);
  259. calcp = calcp > 3 ? 3 : calcp;
  260. }
  261. req->rate = (req->parent_rate / calcm) >> calcp;
  262. req->p = calcp;
  263. req->m = calcm - 1;
  264. }
  265. /*
  266. * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
  267. * parent index
  268. */
  269. static void sun6i_ahb1_recalc(struct factors_request *req)
  270. {
  271. req->rate = req->parent_rate;
  272. /* apply pre-divider first if parent is pll6 */
  273. if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
  274. req->rate /= req->m + 1;
  275. /* clk divider */
  276. req->rate >>= req->p;
  277. }
  278. /*
  279. * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  280. * APB1 rate is calculated as follows
  281. * rate = (parent_rate >> p) / (m + 1);
  282. */
  283. static void sun4i_get_apb1_factors(struct factors_request *req)
  284. {
  285. u8 calcm, calcp;
  286. int div;
  287. if (req->parent_rate < req->rate)
  288. req->rate = req->parent_rate;
  289. div = DIV_ROUND_UP(req->parent_rate, req->rate);
  290. /* Invalid rate! */
  291. if (div > 32)
  292. return;
  293. if (div <= 4)
  294. calcp = 0;
  295. else if (div <= 8)
  296. calcp = 1;
  297. else if (div <= 16)
  298. calcp = 2;
  299. else
  300. calcp = 3;
  301. calcm = (div >> calcp) - 1;
  302. req->rate = (req->parent_rate >> calcp) / (calcm + 1);
  303. req->m = calcm;
  304. req->p = calcp;
  305. }
  306. /*
  307. * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
  308. * CLK_OUT rate is calculated as follows
  309. * rate = (parent_rate >> p) / (m + 1);
  310. */
  311. static void sun7i_a20_get_out_factors(struct factors_request *req)
  312. {
  313. u8 div, calcm, calcp;
  314. /* These clocks can only divide, so we will never be able to achieve
  315. * frequencies higher than the parent frequency */
  316. if (req->rate > req->parent_rate)
  317. req->rate = req->parent_rate;
  318. div = DIV_ROUND_UP(req->parent_rate, req->rate);
  319. if (div < 32)
  320. calcp = 0;
  321. else if (div / 2 < 32)
  322. calcp = 1;
  323. else if (div / 4 < 32)
  324. calcp = 2;
  325. else
  326. calcp = 3;
  327. calcm = DIV_ROUND_UP(div, 1 << calcp);
  328. req->rate = (req->parent_rate >> calcp) / calcm;
  329. req->m = calcm - 1;
  330. req->p = calcp;
  331. }
  332. /*
  333. * sunxi_factors_clk_setup() - Setup function for factor clocks
  334. */
  335. static const struct clk_factors_config sun4i_pll1_config = {
  336. .nshift = 8,
  337. .nwidth = 5,
  338. .kshift = 4,
  339. .kwidth = 2,
  340. .mshift = 0,
  341. .mwidth = 2,
  342. .pshift = 16,
  343. .pwidth = 2,
  344. };
  345. static const struct clk_factors_config sun6i_a31_pll1_config = {
  346. .nshift = 8,
  347. .nwidth = 5,
  348. .kshift = 4,
  349. .kwidth = 2,
  350. .mshift = 0,
  351. .mwidth = 2,
  352. .n_start = 1,
  353. };
  354. static const struct clk_factors_config sun8i_a23_pll1_config = {
  355. .nshift = 8,
  356. .nwidth = 5,
  357. .kshift = 4,
  358. .kwidth = 2,
  359. .mshift = 0,
  360. .mwidth = 2,
  361. .pshift = 16,
  362. .pwidth = 2,
  363. .n_start = 1,
  364. };
  365. static const struct clk_factors_config sun4i_pll5_config = {
  366. .nshift = 8,
  367. .nwidth = 5,
  368. .kshift = 4,
  369. .kwidth = 2,
  370. };
  371. static const struct clk_factors_config sun6i_a31_pll6_config = {
  372. .nshift = 8,
  373. .nwidth = 5,
  374. .kshift = 4,
  375. .kwidth = 2,
  376. .n_start = 1,
  377. };
  378. static const struct clk_factors_config sun5i_a13_ahb_config = {
  379. .pshift = 4,
  380. .pwidth = 2,
  381. };
  382. static const struct clk_factors_config sun6i_ahb1_config = {
  383. .mshift = 6,
  384. .mwidth = 2,
  385. .pshift = 4,
  386. .pwidth = 2,
  387. };
  388. static const struct clk_factors_config sun4i_apb1_config = {
  389. .mshift = 0,
  390. .mwidth = 5,
  391. .pshift = 16,
  392. .pwidth = 2,
  393. };
  394. /* user manual says "n" but it's really "p" */
  395. static const struct clk_factors_config sun7i_a20_out_config = {
  396. .mshift = 8,
  397. .mwidth = 5,
  398. .pshift = 20,
  399. .pwidth = 2,
  400. };
  401. static const struct factors_data sun4i_pll1_data __initconst = {
  402. .enable = 31,
  403. .table = &sun4i_pll1_config,
  404. .getter = sun4i_get_pll1_factors,
  405. };
  406. static const struct factors_data sun6i_a31_pll1_data __initconst = {
  407. .enable = 31,
  408. .table = &sun6i_a31_pll1_config,
  409. .getter = sun6i_a31_get_pll1_factors,
  410. };
  411. static const struct factors_data sun8i_a23_pll1_data __initconst = {
  412. .enable = 31,
  413. .table = &sun8i_a23_pll1_config,
  414. .getter = sun8i_a23_get_pll1_factors,
  415. };
  416. static const struct factors_data sun7i_a20_pll4_data __initconst = {
  417. .enable = 31,
  418. .table = &sun4i_pll5_config,
  419. .getter = sun4i_get_pll5_factors,
  420. };
  421. static const struct factors_data sun4i_pll5_data __initconst = {
  422. .enable = 31,
  423. .table = &sun4i_pll5_config,
  424. .getter = sun4i_get_pll5_factors,
  425. };
  426. static const struct factors_data sun6i_a31_pll6_data __initconst = {
  427. .enable = 31,
  428. .table = &sun6i_a31_pll6_config,
  429. .getter = sun6i_a31_get_pll6_factors,
  430. };
  431. static const struct factors_data sun5i_a13_ahb_data __initconst = {
  432. .mux = 6,
  433. .muxmask = BIT(1) | BIT(0),
  434. .table = &sun5i_a13_ahb_config,
  435. .getter = sun5i_a13_get_ahb_factors,
  436. };
  437. static const struct factors_data sun6i_ahb1_data __initconst = {
  438. .mux = 12,
  439. .muxmask = BIT(1) | BIT(0),
  440. .table = &sun6i_ahb1_config,
  441. .getter = sun6i_get_ahb1_factors,
  442. .recalc = sun6i_ahb1_recalc,
  443. };
  444. static const struct factors_data sun4i_apb1_data __initconst = {
  445. .mux = 24,
  446. .muxmask = BIT(1) | BIT(0),
  447. .table = &sun4i_apb1_config,
  448. .getter = sun4i_get_apb1_factors,
  449. };
  450. static const struct factors_data sun7i_a20_out_data __initconst = {
  451. .enable = 31,
  452. .mux = 24,
  453. .muxmask = BIT(1) | BIT(0),
  454. .table = &sun7i_a20_out_config,
  455. .getter = sun7i_a20_get_out_factors,
  456. };
  457. static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
  458. const struct factors_data *data)
  459. {
  460. void __iomem *reg;
  461. reg = of_iomap(node, 0);
  462. if (!reg) {
  463. pr_err("Could not get registers for factors-clk: %pOFn\n",
  464. node);
  465. return NULL;
  466. }
  467. return sunxi_factors_register(node, data, &clk_lock, reg);
  468. }
  469. static void __init sun4i_pll1_clk_setup(struct device_node *node)
  470. {
  471. sunxi_factors_clk_setup(node, &sun4i_pll1_data);
  472. }
  473. CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk",
  474. sun4i_pll1_clk_setup);
  475. static void __init sun6i_pll1_clk_setup(struct device_node *node)
  476. {
  477. sunxi_factors_clk_setup(node, &sun6i_a31_pll1_data);
  478. }
  479. CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk",
  480. sun6i_pll1_clk_setup);
  481. static void __init sun8i_pll1_clk_setup(struct device_node *node)
  482. {
  483. sunxi_factors_clk_setup(node, &sun8i_a23_pll1_data);
  484. }
  485. CLK_OF_DECLARE(sun8i_pll1, "allwinner,sun8i-a23-pll1-clk",
  486. sun8i_pll1_clk_setup);
  487. static void __init sun7i_pll4_clk_setup(struct device_node *node)
  488. {
  489. sunxi_factors_clk_setup(node, &sun7i_a20_pll4_data);
  490. }
  491. CLK_OF_DECLARE(sun7i_pll4, "allwinner,sun7i-a20-pll4-clk",
  492. sun7i_pll4_clk_setup);
  493. static void __init sun5i_ahb_clk_setup(struct device_node *node)
  494. {
  495. sunxi_factors_clk_setup(node, &sun5i_a13_ahb_data);
  496. }
  497. CLK_OF_DECLARE(sun5i_ahb, "allwinner,sun5i-a13-ahb-clk",
  498. sun5i_ahb_clk_setup);
  499. static void __init sun6i_ahb1_clk_setup(struct device_node *node)
  500. {
  501. sunxi_factors_clk_setup(node, &sun6i_ahb1_data);
  502. }
  503. CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
  504. sun6i_ahb1_clk_setup);
  505. static void __init sun4i_apb1_clk_setup(struct device_node *node)
  506. {
  507. sunxi_factors_clk_setup(node, &sun4i_apb1_data);
  508. }
  509. CLK_OF_DECLARE(sun4i_apb1, "allwinner,sun4i-a10-apb1-clk",
  510. sun4i_apb1_clk_setup);
  511. static void __init sun7i_out_clk_setup(struct device_node *node)
  512. {
  513. sunxi_factors_clk_setup(node, &sun7i_a20_out_data);
  514. }
  515. CLK_OF_DECLARE(sun7i_out, "allwinner,sun7i-a20-out-clk",
  516. sun7i_out_clk_setup);
  517. /*
  518. * sunxi_mux_clk_setup() - Setup function for muxes
  519. */
  520. #define SUNXI_MUX_GATE_WIDTH 2
  521. struct mux_data {
  522. u8 shift;
  523. };
  524. static const struct mux_data sun4i_cpu_mux_data __initconst = {
  525. .shift = 16,
  526. };
  527. static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
  528. .shift = 12,
  529. };
  530. static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
  531. .shift = 0,
  532. };
  533. static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
  534. const struct mux_data *data,
  535. unsigned long flags)
  536. {
  537. struct clk *clk;
  538. const char *clk_name = node->name;
  539. const char *parents[SUNXI_MAX_PARENTS];
  540. void __iomem *reg;
  541. int i;
  542. reg = of_iomap(node, 0);
  543. if (!reg) {
  544. pr_err("Could not map registers for mux-clk: %pOF\n", node);
  545. return NULL;
  546. }
  547. i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
  548. if (of_property_read_string(node, "clock-output-names", &clk_name)) {
  549. pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
  550. __func__, node);
  551. goto out_unmap;
  552. }
  553. clk = clk_register_mux(NULL, clk_name, parents, i,
  554. CLK_SET_RATE_PARENT | flags, reg,
  555. data->shift, SUNXI_MUX_GATE_WIDTH,
  556. 0, &clk_lock);
  557. if (IS_ERR(clk)) {
  558. pr_err("%s: failed to register mux clock %s: %ld\n", __func__,
  559. clk_name, PTR_ERR(clk));
  560. goto out_unmap;
  561. }
  562. if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
  563. pr_err("%s: failed to add clock provider for %s\n",
  564. __func__, clk_name);
  565. clk_unregister_divider(clk);
  566. goto out_unmap;
  567. }
  568. return clk;
  569. out_unmap:
  570. iounmap(reg);
  571. return NULL;
  572. }
  573. static void __init sun4i_cpu_clk_setup(struct device_node *node)
  574. {
  575. /* Protect CPU clock */
  576. sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data, CLK_IS_CRITICAL);
  577. }
  578. CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
  579. sun4i_cpu_clk_setup);
  580. static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node)
  581. {
  582. sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data, 0);
  583. }
  584. CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
  585. sun6i_ahb1_mux_clk_setup);
  586. static void __init sun8i_ahb2_clk_setup(struct device_node *node)
  587. {
  588. sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data, 0);
  589. }
  590. CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
  591. sun8i_ahb2_clk_setup);
  592. /*
  593. * sunxi_divider_clk_setup() - Setup function for simple divider clocks
  594. */
  595. struct div_data {
  596. u8 shift;
  597. u8 pow;
  598. u8 width;
  599. const struct clk_div_table *table;
  600. };
  601. static const struct div_data sun4i_axi_data __initconst = {
  602. .shift = 0,
  603. .pow = 0,
  604. .width = 2,
  605. };
  606. static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
  607. { .val = 0, .div = 1 },
  608. { .val = 1, .div = 2 },
  609. { .val = 2, .div = 3 },
  610. { .val = 3, .div = 4 },
  611. { .val = 4, .div = 4 },
  612. { .val = 5, .div = 4 },
  613. { .val = 6, .div = 4 },
  614. { .val = 7, .div = 4 },
  615. { } /* sentinel */
  616. };
  617. static const struct div_data sun8i_a23_axi_data __initconst = {
  618. .width = 3,
  619. .table = sun8i_a23_axi_table,
  620. };
  621. static const struct div_data sun4i_ahb_data __initconst = {
  622. .shift = 4,
  623. .pow = 1,
  624. .width = 2,
  625. };
  626. static const struct clk_div_table sun4i_apb0_table[] __initconst = {
  627. { .val = 0, .div = 2 },
  628. { .val = 1, .div = 2 },
  629. { .val = 2, .div = 4 },
  630. { .val = 3, .div = 8 },
  631. { } /* sentinel */
  632. };
  633. static const struct div_data sun4i_apb0_data __initconst = {
  634. .shift = 8,
  635. .pow = 1,
  636. .width = 2,
  637. .table = sun4i_apb0_table,
  638. };
  639. static void __init sunxi_divider_clk_setup(struct device_node *node,
  640. const struct div_data *data)
  641. {
  642. struct clk *clk;
  643. const char *clk_name = node->name;
  644. const char *clk_parent;
  645. void __iomem *reg;
  646. reg = of_iomap(node, 0);
  647. if (!reg) {
  648. pr_err("Could not map registers for mux-clk: %pOF\n", node);
  649. return;
  650. }
  651. clk_parent = of_clk_get_parent_name(node, 0);
  652. if (of_property_read_string(node, "clock-output-names", &clk_name)) {
  653. pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
  654. __func__, node);
  655. goto out_unmap;
  656. }
  657. clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
  658. reg, data->shift, data->width,
  659. data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
  660. data->table, &clk_lock);
  661. if (IS_ERR(clk)) {
  662. pr_err("%s: failed to register divider clock %s: %ld\n",
  663. __func__, clk_name, PTR_ERR(clk));
  664. goto out_unmap;
  665. }
  666. if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
  667. pr_err("%s: failed to add clock provider for %s\n",
  668. __func__, clk_name);
  669. goto out_unregister;
  670. }
  671. if (clk_register_clkdev(clk, clk_name, NULL)) {
  672. of_clk_del_provider(node);
  673. goto out_unregister;
  674. }
  675. return;
  676. out_unregister:
  677. clk_unregister_divider(clk);
  678. out_unmap:
  679. iounmap(reg);
  680. }
  681. static void __init sun4i_ahb_clk_setup(struct device_node *node)
  682. {
  683. sunxi_divider_clk_setup(node, &sun4i_ahb_data);
  684. }
  685. CLK_OF_DECLARE(sun4i_ahb, "allwinner,sun4i-a10-ahb-clk",
  686. sun4i_ahb_clk_setup);
  687. static void __init sun4i_apb0_clk_setup(struct device_node *node)
  688. {
  689. sunxi_divider_clk_setup(node, &sun4i_apb0_data);
  690. }
  691. CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
  692. sun4i_apb0_clk_setup);
  693. static void __init sun4i_axi_clk_setup(struct device_node *node)
  694. {
  695. sunxi_divider_clk_setup(node, &sun4i_axi_data);
  696. }
  697. CLK_OF_DECLARE(sun4i_axi, "allwinner,sun4i-a10-axi-clk",
  698. sun4i_axi_clk_setup);
  699. static void __init sun8i_axi_clk_setup(struct device_node *node)
  700. {
  701. sunxi_divider_clk_setup(node, &sun8i_a23_axi_data);
  702. }
  703. CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk",
  704. sun8i_axi_clk_setup);
  705. /*
  706. * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
  707. */
  708. #define SUNXI_GATES_MAX_SIZE 64
  709. struct gates_data {
  710. DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
  711. };
  712. /*
  713. * sunxi_divs_clk_setup() helper data
  714. */
  715. #define SUNXI_DIVS_MAX_QTY 4
  716. #define SUNXI_DIVISOR_WIDTH 2
  717. struct divs_data {
  718. const struct factors_data *factors; /* data for the factor clock */
  719. int ndivs; /* number of outputs */
  720. /*
  721. * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
  722. * self or base factor clock refers to the output from the pll
  723. * itself. The remaining refer to fixed or configurable divider
  724. * outputs.
  725. */
  726. struct {
  727. u8 self; /* is it the base factor clock? (only one) */
  728. u8 fixed; /* is it a fixed divisor? if not... */
  729. struct clk_div_table *table; /* is it a table based divisor? */
  730. u8 shift; /* otherwise it's a normal divisor with this shift */
  731. u8 pow; /* is it power-of-two based? */
  732. u8 gate; /* is it independently gateable? */
  733. bool critical;
  734. } div[SUNXI_DIVS_MAX_QTY];
  735. };
  736. static struct clk_div_table pll6_sata_tbl[] = {
  737. { .val = 0, .div = 6, },
  738. { .val = 1, .div = 12, },
  739. { .val = 2, .div = 18, },
  740. { .val = 3, .div = 24, },
  741. { } /* sentinel */
  742. };
  743. static const struct divs_data pll5_divs_data __initconst = {
  744. .factors = &sun4i_pll5_data,
  745. .ndivs = 2,
  746. .div = {
  747. /* Protect PLL5_DDR */
  748. { .shift = 0, .pow = 0, .critical = true }, /* M, DDR */
  749. { .shift = 16, .pow = 1, }, /* P, other */
  750. /* No output for the base factor clock */
  751. }
  752. };
  753. static const struct divs_data pll6_divs_data __initconst = {
  754. .factors = &sun4i_pll5_data,
  755. .ndivs = 4,
  756. .div = {
  757. { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
  758. { .fixed = 2 }, /* P, other */
  759. { .self = 1 }, /* base factor clock, 2x */
  760. { .fixed = 4 }, /* pll6 / 4, used as ahb input */
  761. }
  762. };
  763. static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
  764. .factors = &sun6i_a31_pll6_data,
  765. .ndivs = 2,
  766. .div = {
  767. { .fixed = 2 }, /* normal output */
  768. { .self = 1 }, /* base factor clock, 2x */
  769. }
  770. };
  771. /*
  772. * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
  773. *
  774. * These clocks look something like this
  775. * ________________________
  776. * | ___divisor 1---|----> to consumer
  777. * parent >--| pll___/___divisor 2---|----> to consumer
  778. * | \_______________|____> to consumer
  779. * |________________________|
  780. */
  781. static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
  782. const struct divs_data *data)
  783. {
  784. struct clk_onecell_data *clk_data;
  785. const char *parent;
  786. const char *clk_name;
  787. struct clk **clks, *pclk;
  788. struct clk_hw *gate_hw, *rate_hw;
  789. const struct clk_ops *rate_ops;
  790. struct clk_gate *gate = NULL;
  791. struct clk_fixed_factor *fix_factor;
  792. struct clk_divider *divider;
  793. struct factors_data factors = *data->factors;
  794. char *derived_name = NULL;
  795. void __iomem *reg;
  796. int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
  797. int flags, clkflags;
  798. /* if number of children known, use it */
  799. if (data->ndivs)
  800. ndivs = data->ndivs;
  801. /* Try to find a name for base factor clock */
  802. for (i = 0; i < ndivs; i++) {
  803. if (data->div[i].self) {
  804. of_property_read_string_index(node, "clock-output-names",
  805. i, &factors.name);
  806. break;
  807. }
  808. }
  809. /* If we don't have a .self clk use the first output-name up to '_' */
  810. if (factors.name == NULL) {
  811. char *endp;
  812. of_property_read_string_index(node, "clock-output-names",
  813. 0, &clk_name);
  814. endp = strchr(clk_name, '_');
  815. if (endp) {
  816. derived_name = kstrndup(clk_name, endp - clk_name,
  817. GFP_KERNEL);
  818. if (!derived_name)
  819. return NULL;
  820. factors.name = derived_name;
  821. } else {
  822. factors.name = clk_name;
  823. }
  824. }
  825. /* Set up factor clock that we will be dividing */
  826. pclk = sunxi_factors_clk_setup(node, &factors);
  827. if (!pclk)
  828. return NULL;
  829. parent = __clk_get_name(pclk);
  830. kfree(derived_name);
  831. reg = of_iomap(node, 0);
  832. if (!reg) {
  833. pr_err("Could not map registers for divs-clk: %pOF\n", node);
  834. return NULL;
  835. }
  836. clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
  837. if (!clk_data)
  838. goto out_unmap;
  839. clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
  840. if (!clks)
  841. goto free_clkdata;
  842. clk_data->clks = clks;
  843. /* It's not a good idea to have automatic reparenting changing
  844. * our RAM clock! */
  845. clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
  846. for (i = 0; i < ndivs; i++) {
  847. if (of_property_read_string_index(node, "clock-output-names",
  848. i, &clk_name) != 0)
  849. break;
  850. /* If this is the base factor clock, only update clks */
  851. if (data->div[i].self) {
  852. clk_data->clks[i] = pclk;
  853. continue;
  854. }
  855. gate_hw = NULL;
  856. rate_hw = NULL;
  857. rate_ops = NULL;
  858. /* If this leaf clock can be gated, create a gate */
  859. if (data->div[i].gate) {
  860. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  861. if (!gate)
  862. goto free_clks;
  863. gate->reg = reg;
  864. gate->bit_idx = data->div[i].gate;
  865. gate->lock = &clk_lock;
  866. gate_hw = &gate->hw;
  867. }
  868. /* Leaves can be fixed or configurable divisors */
  869. if (data->div[i].fixed) {
  870. fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
  871. if (!fix_factor)
  872. goto free_gate;
  873. fix_factor->mult = 1;
  874. fix_factor->div = data->div[i].fixed;
  875. rate_hw = &fix_factor->hw;
  876. rate_ops = &clk_fixed_factor_ops;
  877. } else {
  878. divider = kzalloc(sizeof(*divider), GFP_KERNEL);
  879. if (!divider)
  880. goto free_gate;
  881. flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
  882. divider->reg = reg;
  883. divider->shift = data->div[i].shift;
  884. divider->width = SUNXI_DIVISOR_WIDTH;
  885. divider->flags = flags;
  886. divider->lock = &clk_lock;
  887. divider->table = data->div[i].table;
  888. rate_hw = &divider->hw;
  889. rate_ops = &clk_divider_ops;
  890. }
  891. /* Wrap the (potential) gate and the divisor on a composite
  892. * clock to unify them */
  893. clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
  894. NULL, NULL,
  895. rate_hw, rate_ops,
  896. gate_hw, &clk_gate_ops,
  897. clkflags |
  898. (data->div[i].critical ?
  899. CLK_IS_CRITICAL : 0));
  900. WARN_ON(IS_ERR(clk_data->clks[i]));
  901. }
  902. /* Adjust to the real max */
  903. clk_data->clk_num = i;
  904. if (of_clk_add_provider(node, of_clk_src_onecell_get, clk_data)) {
  905. pr_err("%s: failed to add clock provider for %s\n",
  906. __func__, clk_name);
  907. goto free_gate;
  908. }
  909. return clks;
  910. free_gate:
  911. kfree(gate);
  912. free_clks:
  913. kfree(clks);
  914. free_clkdata:
  915. kfree(clk_data);
  916. out_unmap:
  917. iounmap(reg);
  918. return NULL;
  919. }
  920. static void __init sun4i_pll5_clk_setup(struct device_node *node)
  921. {
  922. sunxi_divs_clk_setup(node, &pll5_divs_data);
  923. }
  924. CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
  925. sun4i_pll5_clk_setup);
  926. static void __init sun4i_pll6_clk_setup(struct device_node *node)
  927. {
  928. sunxi_divs_clk_setup(node, &pll6_divs_data);
  929. }
  930. CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
  931. sun4i_pll6_clk_setup);
  932. static void __init sun6i_pll6_clk_setup(struct device_node *node)
  933. {
  934. sunxi_divs_clk_setup(node, &sun6i_a31_pll6_divs_data);
  935. }
  936. CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
  937. sun6i_pll6_clk_setup);
  938. /*
  939. * sun6i display
  940. *
  941. * rate = parent_rate / (m + 1);
  942. */
  943. static void sun6i_display_factors(struct factors_request *req)
  944. {
  945. u8 m;
  946. if (req->rate > req->parent_rate)
  947. req->rate = req->parent_rate;
  948. m = DIV_ROUND_UP(req->parent_rate, req->rate);
  949. req->rate = req->parent_rate / m;
  950. req->m = m - 1;
  951. }
  952. static const struct clk_factors_config sun6i_display_config = {
  953. .mshift = 0,
  954. .mwidth = 4,
  955. };
  956. static const struct factors_data sun6i_display_data __initconst = {
  957. .enable = 31,
  958. .mux = 24,
  959. .muxmask = BIT(2) | BIT(1) | BIT(0),
  960. .table = &sun6i_display_config,
  961. .getter = sun6i_display_factors,
  962. };
  963. static void __init sun6i_display_setup(struct device_node *node)
  964. {
  965. sunxi_factors_clk_setup(node, &sun6i_display_data);
  966. }
  967. CLK_OF_DECLARE(sun6i_display, "allwinner,sun6i-a31-display-clk",
  968. sun6i_display_setup);