ccu-sun8i-v3s.h 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright (c) 2016 Icenowy Zheng <[email protected]>
  4. *
  5. * Based on ccu-sun8i-h3.h, which is:
  6. * Copyright (c) 2016 Maxime Ripard <[email protected]>
  7. */
  8. #ifndef _CCU_SUN8I_H3_H_
  9. #define _CCU_SUN8I_H3_H_
  10. #include <dt-bindings/clock/sun8i-v3s-ccu.h>
  11. #include <dt-bindings/reset/sun8i-v3s-ccu.h>
  12. #define CLK_PLL_CPU 0
  13. #define CLK_PLL_AUDIO_BASE 1
  14. #define CLK_PLL_AUDIO 2
  15. #define CLK_PLL_AUDIO_2X 3
  16. #define CLK_PLL_AUDIO_4X 4
  17. #define CLK_PLL_AUDIO_8X 5
  18. #define CLK_PLL_VIDEO 6
  19. #define CLK_PLL_VE 7
  20. #define CLK_PLL_DDR0 8
  21. #define CLK_PLL_PERIPH0 9
  22. #define CLK_PLL_PERIPH0_2X 10
  23. #define CLK_PLL_ISP 11
  24. #define CLK_PLL_PERIPH1 12
  25. /* Reserve one number for not implemented and not used PLL_DDR1 */
  26. /* The CPU clock is exported */
  27. #define CLK_AXI 15
  28. #define CLK_AHB1 16
  29. #define CLK_APB1 17
  30. #define CLK_APB2 18
  31. #define CLK_AHB2 19
  32. /* All the bus gates are exported */
  33. /* The first bunch of module clocks are exported */
  34. #define CLK_DRAM 58
  35. /* All the DRAM gates are exported */
  36. /* Some more module clocks are exported */
  37. #define CLK_MBUS 72
  38. /* And the GPU module clock is exported */
  39. #define CLK_PLL_DDR1 74
  40. #endif /* _CCU_SUN8I_H3_H_ */