ccu-sun5i.h 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright 2016 Maxime Ripard
  4. *
  5. * Maxime Ripard <[email protected]>
  6. */
  7. #ifndef _CCU_SUN5I_H_
  8. #define _CCU_SUN5I_H_
  9. #include <dt-bindings/clock/sun5i-ccu.h>
  10. #include <dt-bindings/reset/sun5i-ccu.h>
  11. /* The HOSC is exported */
  12. #define CLK_PLL_CORE 2
  13. #define CLK_PLL_AUDIO_BASE 3
  14. #define CLK_PLL_AUDIO 4
  15. #define CLK_PLL_AUDIO_2X 5
  16. #define CLK_PLL_AUDIO_4X 6
  17. #define CLK_PLL_AUDIO_8X 7
  18. #define CLK_PLL_VIDEO0 8
  19. /* The PLL_VIDEO0_2X is exported for HDMI */
  20. #define CLK_PLL_VE 10
  21. #define CLK_PLL_DDR_BASE 11
  22. #define CLK_PLL_DDR 12
  23. #define CLK_PLL_DDR_OTHER 13
  24. #define CLK_PLL_PERIPH 14
  25. #define CLK_PLL_VIDEO1 15
  26. /* The PLL_VIDEO1_2X is exported for HDMI */
  27. /* The CPU clock is exported */
  28. #define CLK_AXI 18
  29. #define CLK_AHB 19
  30. #define CLK_APB0 20
  31. #define CLK_APB1 21
  32. #define CLK_DRAM_AXI 22
  33. /* AHB gates are exported */
  34. /* APB0 gates are exported */
  35. /* APB1 gates are exported */
  36. /* Modules clocks are exported */
  37. /* USB clocks are exported */
  38. /* GPS clock is exported */
  39. /* DRAM gates are exported */
  40. /* More display modules clocks are exported */
  41. #define CLK_TCON_CH1_SCLK 91
  42. /* The rest of the module clocks are exported */
  43. #define CLK_NUMBER (CLK_IEP + 1)
  44. #endif /* _CCU_SUN5I_H_ */