clkgen-pll.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2014 STMicroelectronics (R&D) Limited
  4. */
  5. /*
  6. * Authors:
  7. * Stephen Gallimore <[email protected]>,
  8. * Pankaj Dev <[email protected]>.
  9. */
  10. #include <linux/slab.h>
  11. #include <linux/of_address.h>
  12. #include <linux/clk.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/iopoll.h>
  15. #include "clkgen.h"
  16. static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
  17. DEFINE_SPINLOCK(clkgen_a9_lock);
  18. /*
  19. * PLL configuration register bits for PLL3200 C32
  20. */
  21. #define C32_NDIV_MASK (0xff)
  22. #define C32_IDF_MASK (0x7)
  23. #define C32_ODF_MASK (0x3f)
  24. #define C32_LDF_MASK (0x7f)
  25. #define C32_CP_MASK (0x1f)
  26. #define C32_MAX_ODFS (4)
  27. /*
  28. * PLL configuration register bits for PLL4600 C28
  29. */
  30. #define C28_NDIV_MASK (0xff)
  31. #define C28_IDF_MASK (0x7)
  32. #define C28_ODF_MASK (0x3f)
  33. struct clkgen_pll_data {
  34. struct clkgen_field pdn_status;
  35. struct clkgen_field pdn_ctrl;
  36. struct clkgen_field locked_status;
  37. struct clkgen_field mdiv;
  38. struct clkgen_field ndiv;
  39. struct clkgen_field pdiv;
  40. struct clkgen_field idf;
  41. struct clkgen_field ldf;
  42. struct clkgen_field cp;
  43. unsigned int num_odfs;
  44. struct clkgen_field odf[C32_MAX_ODFS];
  45. struct clkgen_field odf_gate[C32_MAX_ODFS];
  46. bool switch2pll_en;
  47. struct clkgen_field switch2pll;
  48. spinlock_t *lock;
  49. const struct clk_ops *ops;
  50. };
  51. struct clkgen_clk_out {
  52. const char *name;
  53. unsigned long flags;
  54. };
  55. struct clkgen_pll_data_clks {
  56. struct clkgen_pll_data *data;
  57. const struct clkgen_clk_out *outputs;
  58. };
  59. static const struct clk_ops stm_pll3200c32_ops;
  60. static const struct clk_ops stm_pll3200c32_a9_ops;
  61. static const struct clk_ops stm_pll4600c28_ops;
  62. static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
  63. /* 407 C0 PLL0 */
  64. .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
  65. .pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
  66. .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
  67. .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
  68. .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
  69. .num_odfs = 1,
  70. .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
  71. .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
  72. .ops = &stm_pll3200c32_ops,
  73. };
  74. static const struct clkgen_pll_data_clks st_pll3200c32_cx_0_legacy_data = {
  75. .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
  76. };
  77. static const struct clkgen_clk_out st_pll3200c32_ax_0_clks[] = {
  78. { .name = "clk-s-a0-pll-odf-0", },
  79. };
  80. static const struct clkgen_pll_data_clks st_pll3200c32_a0_data = {
  81. .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
  82. .outputs = st_pll3200c32_ax_0_clks,
  83. };
  84. static const struct clkgen_clk_out st_pll3200c32_cx_0_clks[] = {
  85. { .name = "clk-s-c0-pll0-odf-0", },
  86. };
  87. static const struct clkgen_pll_data_clks st_pll3200c32_c0_data = {
  88. .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
  89. .outputs = st_pll3200c32_cx_0_clks,
  90. };
  91. static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
  92. /* 407 C0 PLL1 */
  93. .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
  94. .pdn_ctrl = CLKGEN_FIELD(0x2c8, 0x1, 8),
  95. .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
  96. .ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
  97. .idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0),
  98. .num_odfs = 1,
  99. .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) },
  100. .odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) },
  101. .ops = &stm_pll3200c32_ops,
  102. };
  103. static const struct clkgen_pll_data_clks st_pll3200c32_cx_1_legacy_data = {
  104. .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1,
  105. };
  106. static const struct clkgen_clk_out st_pll3200c32_cx_1_clks[] = {
  107. { .name = "clk-s-c0-pll1-odf-0", },
  108. };
  109. static const struct clkgen_pll_data_clks st_pll3200c32_c1_data = {
  110. .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1,
  111. .outputs = st_pll3200c32_cx_1_clks,
  112. };
  113. static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
  114. /* 407 A9 */
  115. .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
  116. .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1, 0),
  117. .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
  118. .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0),
  119. .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25),
  120. .num_odfs = 1,
  121. .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
  122. .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
  123. .switch2pll_en = true,
  124. .cp = CLKGEN_FIELD(0x1a8, C32_CP_MASK, 1),
  125. .switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1),
  126. .lock = &clkgen_a9_lock,
  127. .ops = &stm_pll3200c32_a9_ops,
  128. };
  129. static const struct clkgen_clk_out st_pll3200c32_407_a9_clks[] = {
  130. { .name = "clockgen-a9-pll-odf", },
  131. };
  132. static const struct clkgen_pll_data_clks st_pll3200c32_407_a9_data = {
  133. .data = (struct clkgen_pll_data *)&st_pll3200c32_407_a9,
  134. .outputs = st_pll3200c32_407_a9_clks,
  135. };
  136. static struct clkgen_pll_data st_pll4600c28_418_a9 = {
  137. /* 418 A9 */
  138. .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
  139. .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1, 0),
  140. .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
  141. .ndiv = CLKGEN_FIELD(0x1b0, C28_NDIV_MASK, 0),
  142. .idf = CLKGEN_FIELD(0x1a8, C28_IDF_MASK, 25),
  143. .num_odfs = 1,
  144. .odf = { CLKGEN_FIELD(0x1b0, C28_ODF_MASK, 8) },
  145. .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
  146. .switch2pll_en = true,
  147. .switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1),
  148. .lock = &clkgen_a9_lock,
  149. .ops = &stm_pll4600c28_ops,
  150. };
  151. static const struct clkgen_clk_out st_pll4600c28_418_a9_clks[] = {
  152. { .name = "clockgen-a9-pll-odf", },
  153. };
  154. static const struct clkgen_pll_data_clks st_pll4600c28_418_a9_data = {
  155. .data = (struct clkgen_pll_data *)&st_pll4600c28_418_a9,
  156. .outputs = st_pll4600c28_418_a9_clks,
  157. };
  158. /**
  159. * DOC: Clock Generated by PLL, rate set and enabled by bootloader
  160. *
  161. * Traits of this clock:
  162. * prepare - clk_(un)prepare only ensures parent is (un)prepared
  163. * enable - clk_enable/disable only ensures parent is enabled
  164. * rate - rate is fixed. No clk_set_rate support
  165. * parent - fixed parent. No clk_set_parent support
  166. */
  167. /*
  168. * PLL clock that is integrated in the ClockGenA instances on the STiH415
  169. * and STiH416.
  170. *
  171. * @hw: handle between common and hardware-specific interfaces.
  172. * @regs_base: base of the PLL configuration register(s).
  173. *
  174. */
  175. struct clkgen_pll {
  176. struct clk_hw hw;
  177. struct clkgen_pll_data *data;
  178. void __iomem *regs_base;
  179. spinlock_t *lock;
  180. u32 ndiv;
  181. u32 idf;
  182. u32 cp;
  183. };
  184. #define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
  185. struct stm_pll {
  186. unsigned long mdiv;
  187. unsigned long ndiv;
  188. unsigned long pdiv;
  189. unsigned long odf;
  190. unsigned long idf;
  191. unsigned long ldf;
  192. unsigned long cp;
  193. };
  194. static int clkgen_pll_is_locked(struct clk_hw *hw)
  195. {
  196. struct clkgen_pll *pll = to_clkgen_pll(hw);
  197. u32 locked = CLKGEN_READ(pll, locked_status);
  198. return !!locked;
  199. }
  200. static int clkgen_pll_is_enabled(struct clk_hw *hw)
  201. {
  202. struct clkgen_pll *pll = to_clkgen_pll(hw);
  203. u32 poweroff = CLKGEN_READ(pll, pdn_status);
  204. return !poweroff;
  205. }
  206. static int __clkgen_pll_enable(struct clk_hw *hw)
  207. {
  208. struct clkgen_pll *pll = to_clkgen_pll(hw);
  209. void __iomem *base = pll->regs_base;
  210. struct clkgen_field *field = &pll->data->locked_status;
  211. int ret = 0;
  212. u32 reg;
  213. if (clkgen_pll_is_enabled(hw))
  214. return 0;
  215. CLKGEN_WRITE(pll, pdn_ctrl, 0);
  216. ret = readl_relaxed_poll_timeout(base + field->offset, reg,
  217. !!((reg >> field->shift) & field->mask), 0, 10000);
  218. if (!ret) {
  219. if (pll->data->switch2pll_en)
  220. CLKGEN_WRITE(pll, switch2pll, 0);
  221. pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__);
  222. }
  223. return ret;
  224. }
  225. static int clkgen_pll_enable(struct clk_hw *hw)
  226. {
  227. struct clkgen_pll *pll = to_clkgen_pll(hw);
  228. unsigned long flags = 0;
  229. int ret = 0;
  230. if (pll->lock)
  231. spin_lock_irqsave(pll->lock, flags);
  232. ret = __clkgen_pll_enable(hw);
  233. if (pll->lock)
  234. spin_unlock_irqrestore(pll->lock, flags);
  235. return ret;
  236. }
  237. static void __clkgen_pll_disable(struct clk_hw *hw)
  238. {
  239. struct clkgen_pll *pll = to_clkgen_pll(hw);
  240. if (!clkgen_pll_is_enabled(hw))
  241. return;
  242. if (pll->data->switch2pll_en)
  243. CLKGEN_WRITE(pll, switch2pll, 1);
  244. CLKGEN_WRITE(pll, pdn_ctrl, 1);
  245. pr_debug("%s:%s disabled\n", __clk_get_name(hw->clk), __func__);
  246. }
  247. static void clkgen_pll_disable(struct clk_hw *hw)
  248. {
  249. struct clkgen_pll *pll = to_clkgen_pll(hw);
  250. unsigned long flags = 0;
  251. if (pll->lock)
  252. spin_lock_irqsave(pll->lock, flags);
  253. __clkgen_pll_disable(hw);
  254. if (pll->lock)
  255. spin_unlock_irqrestore(pll->lock, flags);
  256. }
  257. static int clk_pll3200c32_get_params(unsigned long input, unsigned long output,
  258. struct stm_pll *pll)
  259. {
  260. unsigned long i, n;
  261. unsigned long deviation = ~0;
  262. unsigned long new_freq;
  263. long new_deviation;
  264. /* Charge pump table: highest ndiv value for cp=6 to 25 */
  265. static const unsigned char cp_table[] = {
  266. 48, 56, 64, 72, 80, 88, 96, 104, 112, 120,
  267. 128, 136, 144, 152, 160, 168, 176, 184, 192
  268. };
  269. /* Output clock range: 800Mhz to 1600Mhz */
  270. if (output < 800000000 || output > 1600000000)
  271. return -EINVAL;
  272. input /= 1000;
  273. output /= 1000;
  274. for (i = 1; i <= 7 && deviation; i++) {
  275. n = i * output / (2 * input);
  276. /* Checks */
  277. if (n < 8)
  278. continue;
  279. if (n > 200)
  280. break;
  281. new_freq = (input * 2 * n) / i;
  282. new_deviation = abs(new_freq - output);
  283. if (!new_deviation || new_deviation < deviation) {
  284. pll->idf = i;
  285. pll->ndiv = n;
  286. deviation = new_deviation;
  287. }
  288. }
  289. if (deviation == ~0) /* No solution found */
  290. return -EINVAL;
  291. /* Computing recommended charge pump value */
  292. for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++)
  293. ;
  294. return 0;
  295. }
  296. static int clk_pll3200c32_get_rate(unsigned long input, struct stm_pll *pll,
  297. unsigned long *rate)
  298. {
  299. if (!pll->idf)
  300. pll->idf = 1;
  301. *rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000;
  302. return 0;
  303. }
  304. static unsigned long recalc_stm_pll3200c32(struct clk_hw *hw,
  305. unsigned long parent_rate)
  306. {
  307. struct clkgen_pll *pll = to_clkgen_pll(hw);
  308. unsigned long ndiv, idf;
  309. unsigned long rate = 0;
  310. if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
  311. return 0;
  312. ndiv = CLKGEN_READ(pll, ndiv);
  313. idf = CLKGEN_READ(pll, idf);
  314. if (idf)
  315. /* Note: input is divided to avoid overflow */
  316. rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000;
  317. pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
  318. return rate;
  319. }
  320. static long round_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate,
  321. unsigned long *prate)
  322. {
  323. struct stm_pll params;
  324. if (!clk_pll3200c32_get_params(*prate, rate, &params))
  325. clk_pll3200c32_get_rate(*prate, &params, &rate);
  326. else {
  327. pr_debug("%s: %s rate %ld Invalid\n", __func__,
  328. __clk_get_name(hw->clk), rate);
  329. return 0;
  330. }
  331. pr_debug("%s: %s new rate %ld [ndiv=%u] [idf=%u]\n",
  332. __func__, __clk_get_name(hw->clk),
  333. rate, (unsigned int)params.ndiv,
  334. (unsigned int)params.idf);
  335. return rate;
  336. }
  337. static int set_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate,
  338. unsigned long parent_rate)
  339. {
  340. struct clkgen_pll *pll = to_clkgen_pll(hw);
  341. struct stm_pll params;
  342. long hwrate = 0;
  343. unsigned long flags = 0;
  344. if (!rate || !parent_rate)
  345. return -EINVAL;
  346. if (!clk_pll3200c32_get_params(parent_rate, rate, &params))
  347. clk_pll3200c32_get_rate(parent_rate, &params, &hwrate);
  348. pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",
  349. __func__, __clk_get_name(hw->clk),
  350. hwrate, (unsigned int)params.ndiv,
  351. (unsigned int)params.idf);
  352. if (!hwrate)
  353. return -EINVAL;
  354. pll->ndiv = params.ndiv;
  355. pll->idf = params.idf;
  356. pll->cp = params.cp;
  357. __clkgen_pll_disable(hw);
  358. if (pll->lock)
  359. spin_lock_irqsave(pll->lock, flags);
  360. CLKGEN_WRITE(pll, ndiv, pll->ndiv);
  361. CLKGEN_WRITE(pll, idf, pll->idf);
  362. CLKGEN_WRITE(pll, cp, pll->cp);
  363. if (pll->lock)
  364. spin_unlock_irqrestore(pll->lock, flags);
  365. __clkgen_pll_enable(hw);
  366. return 0;
  367. }
  368. /* PLL output structure
  369. * FVCO >> /2 >> FVCOBY2 (no output)
  370. * |> Divider (ODF) >> PHI
  371. *
  372. * FVCOby2 output = (input * 2 * NDIV) / IDF (assuming FRAC_CONTROL==L)
  373. *
  374. * Rules:
  375. * 4Mhz <= INFF input <= 350Mhz
  376. * 4Mhz <= INFIN (INFF / IDF) <= 50Mhz
  377. * 19.05Mhz <= FVCOby2 output (PHI w ODF=1) <= 3000Mhz
  378. * 1 <= i (register/dec value for IDF) <= 7
  379. * 8 <= n (register/dec value for NDIV) <= 246
  380. */
  381. static int clk_pll4600c28_get_params(unsigned long input, unsigned long output,
  382. struct stm_pll *pll)
  383. {
  384. unsigned long i, infin, n;
  385. unsigned long deviation = ~0;
  386. unsigned long new_freq, new_deviation;
  387. /* Output clock range: 19Mhz to 3000Mhz */
  388. if (output < 19000000 || output > 3000000000u)
  389. return -EINVAL;
  390. /* For better jitter, IDF should be smallest and NDIV must be maximum */
  391. for (i = 1; i <= 7 && deviation; i++) {
  392. /* INFIN checks */
  393. infin = input / i;
  394. if (infin < 4000000 || infin > 50000000)
  395. continue; /* Invalid case */
  396. n = output / (infin * 2);
  397. if (n < 8 || n > 246)
  398. continue; /* Invalid case */
  399. if (n < 246)
  400. n++; /* To work around 'y' when n=x.y */
  401. for (; n >= 8 && deviation; n--) {
  402. new_freq = infin * 2 * n;
  403. if (new_freq < output)
  404. break; /* Optimization: shorting loop */
  405. new_deviation = new_freq - output;
  406. if (!new_deviation || new_deviation < deviation) {
  407. pll->idf = i;
  408. pll->ndiv = n;
  409. deviation = new_deviation;
  410. }
  411. }
  412. }
  413. if (deviation == ~0) /* No solution found */
  414. return -EINVAL;
  415. return 0;
  416. }
  417. static int clk_pll4600c28_get_rate(unsigned long input, struct stm_pll *pll,
  418. unsigned long *rate)
  419. {
  420. if (!pll->idf)
  421. pll->idf = 1;
  422. *rate = (input / pll->idf) * 2 * pll->ndiv;
  423. return 0;
  424. }
  425. static unsigned long recalc_stm_pll4600c28(struct clk_hw *hw,
  426. unsigned long parent_rate)
  427. {
  428. struct clkgen_pll *pll = to_clkgen_pll(hw);
  429. struct stm_pll params;
  430. unsigned long rate;
  431. if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
  432. return 0;
  433. params.ndiv = CLKGEN_READ(pll, ndiv);
  434. params.idf = CLKGEN_READ(pll, idf);
  435. clk_pll4600c28_get_rate(parent_rate, &params, &rate);
  436. pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
  437. return rate;
  438. }
  439. static long round_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate,
  440. unsigned long *prate)
  441. {
  442. struct stm_pll params;
  443. if (!clk_pll4600c28_get_params(*prate, rate, &params)) {
  444. clk_pll4600c28_get_rate(*prate, &params, &rate);
  445. } else {
  446. pr_debug("%s: %s rate %ld Invalid\n", __func__,
  447. __clk_get_name(hw->clk), rate);
  448. return 0;
  449. }
  450. pr_debug("%s: %s new rate %ld [ndiv=%u] [idf=%u]\n",
  451. __func__, __clk_get_name(hw->clk),
  452. rate, (unsigned int)params.ndiv,
  453. (unsigned int)params.idf);
  454. return rate;
  455. }
  456. static int set_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate,
  457. unsigned long parent_rate)
  458. {
  459. struct clkgen_pll *pll = to_clkgen_pll(hw);
  460. struct stm_pll params;
  461. long hwrate;
  462. unsigned long flags = 0;
  463. if (!rate || !parent_rate)
  464. return -EINVAL;
  465. if (!clk_pll4600c28_get_params(parent_rate, rate, &params)) {
  466. clk_pll4600c28_get_rate(parent_rate, &params, &hwrate);
  467. } else {
  468. pr_debug("%s: %s rate %ld Invalid\n", __func__,
  469. __clk_get_name(hw->clk), rate);
  470. return -EINVAL;
  471. }
  472. pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",
  473. __func__, __clk_get_name(hw->clk),
  474. hwrate, (unsigned int)params.ndiv,
  475. (unsigned int)params.idf);
  476. if (!hwrate)
  477. return -EINVAL;
  478. pll->ndiv = params.ndiv;
  479. pll->idf = params.idf;
  480. __clkgen_pll_disable(hw);
  481. if (pll->lock)
  482. spin_lock_irqsave(pll->lock, flags);
  483. CLKGEN_WRITE(pll, ndiv, pll->ndiv);
  484. CLKGEN_WRITE(pll, idf, pll->idf);
  485. if (pll->lock)
  486. spin_unlock_irqrestore(pll->lock, flags);
  487. __clkgen_pll_enable(hw);
  488. return 0;
  489. }
  490. static const struct clk_ops stm_pll3200c32_ops = {
  491. .enable = clkgen_pll_enable,
  492. .disable = clkgen_pll_disable,
  493. .is_enabled = clkgen_pll_is_enabled,
  494. .recalc_rate = recalc_stm_pll3200c32,
  495. };
  496. static const struct clk_ops stm_pll3200c32_a9_ops = {
  497. .enable = clkgen_pll_enable,
  498. .disable = clkgen_pll_disable,
  499. .is_enabled = clkgen_pll_is_enabled,
  500. .recalc_rate = recalc_stm_pll3200c32,
  501. .round_rate = round_rate_stm_pll3200c32,
  502. .set_rate = set_rate_stm_pll3200c32,
  503. };
  504. static const struct clk_ops stm_pll4600c28_ops = {
  505. .enable = clkgen_pll_enable,
  506. .disable = clkgen_pll_disable,
  507. .is_enabled = clkgen_pll_is_enabled,
  508. .recalc_rate = recalc_stm_pll4600c28,
  509. .round_rate = round_rate_stm_pll4600c28,
  510. .set_rate = set_rate_stm_pll4600c28,
  511. };
  512. static struct clk * __init clkgen_pll_register(const char *parent_name,
  513. struct clkgen_pll_data *pll_data,
  514. void __iomem *reg, unsigned long pll_flags,
  515. const char *clk_name, spinlock_t *lock)
  516. {
  517. struct clkgen_pll *pll;
  518. struct clk *clk;
  519. struct clk_init_data init;
  520. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  521. if (!pll)
  522. return ERR_PTR(-ENOMEM);
  523. init.name = clk_name;
  524. init.ops = pll_data->ops;
  525. init.flags = pll_flags | CLK_GET_RATE_NOCACHE;
  526. init.parent_names = &parent_name;
  527. init.num_parents = 1;
  528. pll->data = pll_data;
  529. pll->regs_base = reg;
  530. pll->hw.init = &init;
  531. pll->lock = lock;
  532. clk = clk_register(NULL, &pll->hw);
  533. if (IS_ERR(clk)) {
  534. kfree(pll);
  535. return clk;
  536. }
  537. pr_debug("%s: parent %s rate %lu\n",
  538. __clk_get_name(clk),
  539. __clk_get_name(clk_get_parent(clk)),
  540. clk_get_rate(clk));
  541. return clk;
  542. }
  543. static void __iomem * __init clkgen_get_register_base(
  544. struct device_node *np)
  545. {
  546. struct device_node *pnode;
  547. void __iomem *reg = NULL;
  548. pnode = of_get_parent(np);
  549. if (!pnode)
  550. return NULL;
  551. reg = of_iomap(pnode, 0);
  552. of_node_put(pnode);
  553. return reg;
  554. }
  555. static struct clk * __init clkgen_odf_register(const char *parent_name,
  556. void __iomem *reg,
  557. struct clkgen_pll_data *pll_data,
  558. unsigned long pll_flags, int odf,
  559. spinlock_t *odf_lock,
  560. const char *odf_name)
  561. {
  562. struct clk *clk;
  563. unsigned long flags;
  564. struct clk_gate *gate;
  565. struct clk_divider *div;
  566. flags = pll_flags | CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT;
  567. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  568. if (!gate)
  569. return ERR_PTR(-ENOMEM);
  570. gate->flags = CLK_GATE_SET_TO_DISABLE;
  571. gate->reg = reg + pll_data->odf_gate[odf].offset;
  572. gate->bit_idx = pll_data->odf_gate[odf].shift;
  573. gate->lock = odf_lock;
  574. div = kzalloc(sizeof(*div), GFP_KERNEL);
  575. if (!div) {
  576. kfree(gate);
  577. return ERR_PTR(-ENOMEM);
  578. }
  579. div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
  580. div->reg = reg + pll_data->odf[odf].offset;
  581. div->shift = pll_data->odf[odf].shift;
  582. div->width = fls(pll_data->odf[odf].mask);
  583. div->lock = odf_lock;
  584. clk = clk_register_composite(NULL, odf_name, &parent_name, 1,
  585. NULL, NULL,
  586. &div->hw, &clk_divider_ops,
  587. &gate->hw, &clk_gate_ops,
  588. flags);
  589. if (IS_ERR(clk))
  590. return clk;
  591. pr_debug("%s: parent %s rate %lu\n",
  592. __clk_get_name(clk),
  593. __clk_get_name(clk_get_parent(clk)),
  594. clk_get_rate(clk));
  595. return clk;
  596. }
  597. static void __init clkgen_c32_pll_setup(struct device_node *np,
  598. struct clkgen_pll_data_clks *datac)
  599. {
  600. struct clk *clk;
  601. const char *parent_name, *pll_name;
  602. void __iomem *pll_base;
  603. int num_odfs, odf;
  604. struct clk_onecell_data *clk_data;
  605. unsigned long pll_flags = 0;
  606. parent_name = of_clk_get_parent_name(np, 0);
  607. if (!parent_name)
  608. return;
  609. pll_base = clkgen_get_register_base(np);
  610. if (!pll_base)
  611. return;
  612. of_clk_detect_critical(np, 0, &pll_flags);
  613. clk = clkgen_pll_register(parent_name, datac->data, pll_base, pll_flags,
  614. np->name, datac->data->lock);
  615. if (IS_ERR(clk))
  616. return;
  617. pll_name = __clk_get_name(clk);
  618. num_odfs = datac->data->num_odfs;
  619. clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
  620. if (!clk_data)
  621. return;
  622. clk_data->clk_num = num_odfs;
  623. clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
  624. GFP_KERNEL);
  625. if (!clk_data->clks)
  626. goto err;
  627. for (odf = 0; odf < num_odfs; odf++) {
  628. struct clk *clk;
  629. const char *clk_name;
  630. unsigned long odf_flags = 0;
  631. if (datac->outputs) {
  632. clk_name = datac->outputs[odf].name;
  633. odf_flags = datac->outputs[odf].flags;
  634. } else {
  635. if (of_property_read_string_index(np,
  636. "clock-output-names",
  637. odf, &clk_name))
  638. return;
  639. of_clk_detect_critical(np, odf, &odf_flags);
  640. }
  641. clk = clkgen_odf_register(pll_name, pll_base, datac->data,
  642. odf_flags, odf, &clkgena_c32_odf_lock,
  643. clk_name);
  644. if (IS_ERR(clk))
  645. goto err;
  646. clk_data->clks[odf] = clk;
  647. }
  648. of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
  649. return;
  650. err:
  651. kfree(pll_name);
  652. kfree(clk_data->clks);
  653. kfree(clk_data);
  654. }
  655. static void __init clkgen_c32_pll0_setup(struct device_node *np)
  656. {
  657. clkgen_c32_pll_setup(np,
  658. (struct clkgen_pll_data_clks *) &st_pll3200c32_cx_0_legacy_data);
  659. }
  660. CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup);
  661. static void __init clkgen_c32_pll0_a0_setup(struct device_node *np)
  662. {
  663. clkgen_c32_pll_setup(np,
  664. (struct clkgen_pll_data_clks *) &st_pll3200c32_a0_data);
  665. }
  666. CLK_OF_DECLARE(c32_pll0_a0, "st,clkgen-pll0-a0", clkgen_c32_pll0_a0_setup);
  667. static void __init clkgen_c32_pll0_c0_setup(struct device_node *np)
  668. {
  669. clkgen_c32_pll_setup(np,
  670. (struct clkgen_pll_data_clks *) &st_pll3200c32_c0_data);
  671. }
  672. CLK_OF_DECLARE(c32_pll0_c0, "st,clkgen-pll0-c0", clkgen_c32_pll0_c0_setup);
  673. static void __init clkgen_c32_pll1_setup(struct device_node *np)
  674. {
  675. clkgen_c32_pll_setup(np,
  676. (struct clkgen_pll_data_clks *) &st_pll3200c32_cx_1_legacy_data);
  677. }
  678. CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup);
  679. static void __init clkgen_c32_pll1_c0_setup(struct device_node *np)
  680. {
  681. clkgen_c32_pll_setup(np,
  682. (struct clkgen_pll_data_clks *) &st_pll3200c32_c1_data);
  683. }
  684. CLK_OF_DECLARE(c32_pll1_c0, "st,clkgen-pll1-c0", clkgen_c32_pll1_c0_setup);
  685. static void __init clkgen_c32_plla9_setup(struct device_node *np)
  686. {
  687. clkgen_c32_pll_setup(np,
  688. (struct clkgen_pll_data_clks *) &st_pll3200c32_407_a9_data);
  689. }
  690. CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup);
  691. static void __init clkgen_c28_plla9_setup(struct device_node *np)
  692. {
  693. clkgen_c32_pll_setup(np,
  694. (struct clkgen_pll_data_clks *) &st_pll4600c28_418_a9_data);
  695. }
  696. CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);