clk-pll.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * Copyright (c) 2013 Linaro Ltd.
  5. *
  6. * Common Clock Framework support for all PLL's in Samsung platforms
  7. */
  8. #ifndef __SAMSUNG_CLK_PLL_H
  9. #define __SAMSUNG_CLK_PLL_H
  10. enum samsung_pll_type {
  11. pll_2126,
  12. pll_3000,
  13. pll_35xx,
  14. pll_36xx,
  15. pll_2550,
  16. pll_2650,
  17. pll_4500,
  18. pll_4502,
  19. pll_4508,
  20. pll_4600,
  21. pll_4650,
  22. pll_4650c,
  23. pll_6552,
  24. pll_6552_s3c2416,
  25. pll_6553,
  26. pll_s3c2410_mpll,
  27. pll_s3c2410_upll,
  28. pll_s3c2440_mpll,
  29. pll_2550x,
  30. pll_2550xx,
  31. pll_2650x,
  32. pll_2650xx,
  33. pll_1417x,
  34. pll_1450x,
  35. pll_1451x,
  36. pll_1452x,
  37. pll_1460x,
  38. pll_0822x,
  39. pll_0831x,
  40. pll_142xx,
  41. };
  42. #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
  43. ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
  44. #define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
  45. BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
  46. #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \
  47. { \
  48. .rate = PLL_VALID_RATE(_fin, _rate, \
  49. _m, _p, _s, 0, 16), \
  50. .mdiv = (_m), \
  51. .pdiv = (_p), \
  52. .sdiv = (_s), \
  53. }
  54. #define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s) \
  55. { \
  56. .rate = PLL_VALID_RATE(_fin, _rate, \
  57. _m + 8, _p + 2, _s, 0, 16), \
  58. .mdiv = (_m), \
  59. .pdiv = (_p), \
  60. .sdiv = (_s), \
  61. }
  62. #define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s) \
  63. { \
  64. .rate = PLL_VALID_RATE(_fin, _rate, \
  65. 2 * (_m + 8), _p + 2, _s, 0, 16), \
  66. .mdiv = (_m), \
  67. .pdiv = (_p), \
  68. .sdiv = (_s), \
  69. }
  70. #define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \
  71. { \
  72. .rate = PLL_VALID_RATE(_fin, _rate, \
  73. _m, _p, _s, _k, 16), \
  74. .mdiv = (_m), \
  75. .pdiv = (_p), \
  76. .sdiv = (_s), \
  77. .kdiv = (_k), \
  78. }
  79. #define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc) \
  80. { \
  81. .rate = PLL_VALID_RATE(_fin, _rate, \
  82. _m, _p, _s - 1, 0, 16), \
  83. .mdiv = (_m), \
  84. .pdiv = (_p), \
  85. .sdiv = (_s), \
  86. .afc = (_afc), \
  87. }
  88. #define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel) \
  89. { \
  90. .rate = PLL_VALID_RATE(_fin, _rate, \
  91. _m, _p, _s, _k, 16), \
  92. .mdiv = (_m), \
  93. .pdiv = (_p), \
  94. .sdiv = (_s), \
  95. .kdiv = (_k), \
  96. .vsel = (_vsel), \
  97. }
  98. #define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
  99. { \
  100. .rate = PLL_VALID_RATE(_fin, _rate, \
  101. _m, _p, _s, _k, 10), \
  102. .mdiv = (_m), \
  103. .pdiv = (_p), \
  104. .sdiv = (_s), \
  105. .kdiv = (_k), \
  106. .mfr = (_mfr), \
  107. .mrr = (_mrr), \
  108. .vsel = (_vsel), \
  109. }
  110. /* NOTE: Rate table should be kept sorted in descending order. */
  111. struct samsung_pll_rate_table {
  112. unsigned int rate;
  113. unsigned int pdiv;
  114. unsigned int mdiv;
  115. unsigned int sdiv;
  116. unsigned int kdiv;
  117. unsigned int afc;
  118. unsigned int mfr;
  119. unsigned int mrr;
  120. unsigned int vsel;
  121. };
  122. #endif /* __SAMSUNG_CLK_PLL_H */