Home Explore Help
Sign In
samsung-sm8650
/
android_kernel_samsung_sm8650_ksu
2
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Tree: 9e449c3f83
Branches Tags
android_kernel_...
/
drivers
/
clk
/
qcom
/
virtio_clk_sm8150.c

virtio_clk_sm8150.c 6.2 KB
History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118 
  1. // SPDX-License-Identifier: GPL-2.0-only
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #include <linux/kernel.h>
    7. 

  7. #include <linux/module.h>
    8. 

  8. #include <dt-bindings/clock/qcom,gcc-sm8150.h>
    9. 

  9. #include <dt-bindings/clock/qcom,scc-sm8150.h>
    10. 

  10. #include "virtio_clk_common.h"
    11. 

  11. 

  12. static const struct virtio_clk_init_data sm8150_gcc_virtio_clocks[] = {
    13. 

  13. 	[GCC_QUPV3_WRAP0_S0_CLK] = {.name = "gcc_qupv3_wrap0_s0_clk",},
    14. 

  14. 	[GCC_QUPV3_WRAP0_S1_CLK] = {.name = "gcc_qupv3_wrap0_s1_clk",},
    15. 

  15. 	[GCC_QUPV3_WRAP0_S2_CLK] = {.name = "gcc_qupv3_wrap0_s2_clk",},
    16. 

  16. 	[GCC_QUPV3_WRAP0_S3_CLK] = {.name = "gcc_qupv3_wrap0_s3_clk",},
    17. 

  17. 	[GCC_QUPV3_WRAP0_S4_CLK] = {.name = "gcc_qupv3_wrap0_s4_clk",},
    18. 

  18. 	[GCC_QUPV3_WRAP0_S5_CLK] = {.name = "gcc_qupv3_wrap0_s5_clk",},
    19. 

  19. 	[GCC_QUPV3_WRAP0_S6_CLK] = {.name = "gcc_qupv3_wrap0_s6_clk",},
    20. 

  20. 	[GCC_QUPV3_WRAP0_S7_CLK] = {.name = "gcc_qupv3_wrap0_s7_clk",},
    21. 

  21. 	[GCC_QUPV3_WRAP1_S0_CLK] = {.name = "gcc_qupv3_wrap1_s0_clk",},
    22. 

  22. 	[GCC_QUPV3_WRAP1_S1_CLK] = {.name = "gcc_qupv3_wrap1_s1_clk",},
    23. 

  23. 	[GCC_QUPV3_WRAP1_S2_CLK] = {.name = "gcc_qupv3_wrap1_s2_clk",},
    24. 

  24. 	[GCC_QUPV3_WRAP1_S3_CLK] = {.name = "gcc_qupv3_wrap1_s3_clk",},
    25. 

  25. 	[GCC_QUPV3_WRAP1_S4_CLK] = {.name = "gcc_qupv3_wrap1_s4_clk",},
    26. 

  26. 	[GCC_QUPV3_WRAP1_S5_CLK] = {.name = "gcc_qupv3_wrap1_s5_clk",},
    27. 

  27. 	[GCC_QUPV3_WRAP2_S0_CLK] = {.name = "gcc_qupv3_wrap2_s0_clk",},
    28. 

  28. 	[GCC_QUPV3_WRAP2_S1_CLK] = {.name = "gcc_qupv3_wrap2_s1_clk",},
    29. 

  29. 	[GCC_QUPV3_WRAP2_S2_CLK] = {.name = "gcc_qupv3_wrap2_s2_clk",},
    30. 

  30. 	[GCC_QUPV3_WRAP2_S3_CLK] = {.name = "gcc_qupv3_wrap2_s3_clk",},
    31. 

  31. 	[GCC_QUPV3_WRAP2_S4_CLK] = {.name = "gcc_qupv3_wrap2_s4_clk",},
    32. 

  32. 	[GCC_QUPV3_WRAP2_S5_CLK] = {.name = "gcc_qupv3_wrap2_s5_clk",},
    33. 

  33. 	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = {.name = "gcc_qupv3_wrap_0_m_ahb_clk",},
    34. 

  34. 	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = {.name = "gcc_qupv3_wrap_0_s_ahb_clk",},
    35. 

  35. 	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = {.name = "gcc_qupv3_wrap_1_m_ahb_clk",},
    36. 

  36. 	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = {.name = "gcc_qupv3_wrap_1_s_ahb_clk",},
    37. 

  37. 	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = {.name = "gcc_qupv3_wrap_2_m_ahb_clk",},
    38. 

  38. 	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = {.name = "gcc_qupv3_wrap_2_s_ahb_clk",},
    39. 

  39. 	[GCC_USB30_PRIM_MASTER_CLK] = {.name = "gcc_usb30_prim_master_clk",},
    40. 

  40. 	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = {.name = "gcc_cfg_noc_usb3_prim_axi_clk",},
    41. 

  41. 	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = {.name = "gcc_aggre_usb3_prim_axi_clk",},
    42. 

  42. 	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = {.name = "gcc_usb30_prim_mock_utmi_clk",},
    43. 

  43. 	[GCC_USB30_PRIM_SLEEP_CLK] = {.name = "gcc_usb30_prim_sleep_clk",},
    44. 

  44. 	[GCC_USB3_SEC_CLKREF_CLK] = {.name = "gcc_usb3_sec_clkref_en",},
    45. 

  45. 	[GCC_USB3_PRIM_PHY_AUX_CLK] = {.name = "gcc_usb3_prim_phy_aux_clk",},
    46. 

  46. 	[GCC_USB3_PRIM_PHY_PIPE_CLK] = {.name = "gcc_usb3_prim_phy_pipe_clk",},
    47. 

  47. 	[GCC_USB3_PRIM_CLKREF_CLK] = {.name = "gcc_usb3_prim_clkref_en",},
    48. 

  48. 	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = {.name = "gcc_usb3_prim_phy_com_aux_clk",},
    49. 

  49. 	[GCC_USB30_SEC_MASTER_CLK] = {.name = "gcc_usb30_sec_master_clk",},
    50. 

  50. 	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = {.name = "gcc_cfg_noc_usb3_sec_axi_clk",},
    51. 

  51. 	[GCC_AGGRE_USB3_SEC_AXI_CLK] = {.name = "gcc_aggre_usb3_sec_axi_clk",},
    52. 

  52. 	[GCC_USB30_SEC_MOCK_UTMI_CLK] = {.name = "gcc_usb30_sec_mock_utmi_clk",},
    53. 

  53. 	[GCC_USB30_SEC_SLEEP_CLK] = {.name = "gcc_usb30_sec_sleep_clk",},
    54. 

  54. 	[GCC_USB3_SEC_PHY_AUX_CLK] = {.name = "gcc_usb3_sec_phy_aux_clk",},
    55. 

  55. 	[GCC_USB3_SEC_PHY_PIPE_CLK] = {.name = "gcc_usb3_sec_phy_pipe_clk",},
    56. 

  56. 	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = {.name = "gcc_usb3_sec_phy_com_aux_clk",},
    57. 

  57. 	[GCC_PCIE_0_PIPE_CLK] = {.name = "gcc_pcie_0_pipe_clk",},
    58. 

  58. 	[GCC_PCIE_0_AUX_CLK] = {.name = "gcc_pcie_0_aux_clk",},
    59. 

  59. 	[GCC_PCIE_0_CFG_AHB_CLK] = {.name = "gcc_pcie_0_cfg_ahb_clk",},
    60. 

  60. 	[GCC_PCIE_0_MSTR_AXI_CLK] = {.name = "gcc_pcie_0_mstr_axi_clk",},
    61. 

  61. 	[GCC_PCIE_0_SLV_AXI_CLK] = {.name = "gcc_pcie_0_slv_axi_clk",},
    62. 

  62. 	[GCC_PCIE_0_CLKREF_CLK] = {.name = "gcc_pcie_0_clkref_en",},
    63. 

  63. 	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = {.name = "gcc_pcie_0_slv_q2a_axi_clk",},
    64. 

  64. 	[GCC_PCIE_1_PIPE_CLK] = {.name = "gcc_pcie_1_pipe_clk",},
    65. 

  65. 	[GCC_PCIE_1_AUX_CLK] = {.name = "gcc_pcie_1_aux_clk",},
    66. 

  66. 	[GCC_PCIE_1_CFG_AHB_CLK] = {.name = "gcc_pcie_1_cfg_ahb_clk",},
    67. 

  67. 	[GCC_PCIE_1_MSTR_AXI_CLK] = {.name = "gcc_pcie_1_mstr_axi_clk",},
    68. 

  68. 	[GCC_PCIE_1_SLV_AXI_CLK] = {.name = "gcc_pcie_1_slv_axi_clk",},
    69. 

  69. 	[GCC_PCIE_1_CLKREF_CLK] = {.name = "gcc_pcie_1_clkref_en",},
    70. 

  70. 	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = {.name = "gcc_pcie_1_slv_q2a_axi_clk",},
    71. 

  71. 	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = {.name = "gcc_aggre_noc_pcie_tbu_clk",},
    72. 

  72. 	[GCC_PCIE0_PHY_REFGEN_CLK] = {.name = "gcc_pcie0_phy_refgen_clk",},
    73. 

  73. 	[GCC_PCIE1_PHY_REFGEN_CLK] = {.name = "gcc_pcie1_phy_refgen_clk",},
    74. 

  74. 	[GCC_PCIE_PHY_AUX_CLK] = {.name = "gcc_pcie_phy_aux_clk",},
    75. 

  75. 	[GCC_SDCC2_AHB_CLK] = {.name = "gcc_sdcc2_ahb_clk",},
    76. 

  76. 	[GCC_SDCC2_APPS_CLK] = {.name = "gcc_sdcc2_apps_clk",},
    77. 

  77. 	[GCC_PRNG_AHB_CLK] = {.name = "gcc_prng_ahb_clk",},
    78. 

  78. };
    79. 

  79. 

  80. static const char * const sm8150_gcc_virtio_resets[] = {
    81. 

  81. 	[GCC_QUSB2PHY_PRIM_BCR] = "gcc_qusb2phy_prim_bcr",
    82. 

  82. 	[GCC_QUSB2PHY_SEC_BCR] = "gcc_qusb2phy_sec_bcr",
    83. 

  83. 	[GCC_USB3_PHY_PRIM_BCR] = "gcc_usb3_phy_prim_bcr",
    84. 

  84. 	[GCC_USB3_DP_PHY_PRIM_BCR] = "gcc_usb3_dp_phy_prim_bcr",
    85. 

  85. 	[GCC_USB3_PHY_SEC_BCR] = "gcc_usb3_phy_sec_bcr",
    86. 

  86. 	[GCC_USB3PHY_PHY_SEC_BCR] = "gcc_usb3phy_phy_sec_bcr",
    87. 

  87. 	[GCC_USB30_PRIM_BCR] = "gcc_usb30_prim_master_clk",
    88. 

  88. 	[GCC_USB30_SEC_BCR] = "gcc_usb30_sec_master_clk",
    89. 

  89. 	[GCC_PCIE_0_BCR] = "gcc_pcie_0_mstr_axi_clk",
    90. 

  90. 	[GCC_PCIE_0_PHY_BCR] = "gcc_pcie_0_phy_bcr",
    91. 

  91. 	[GCC_PCIE_1_BCR] = "gcc_pcie_1_mstr_axi_clk",
    92. 

  92. 	[GCC_PCIE_1_PHY_BCR] = "gcc_pcie_1_phy_bcr",
    93. 

  93. };
    94. 

  94. 

  95. const struct clk_virtio_desc clk_virtio_sm8150_gcc = {
    96. 

  96. 	.clks = sm8150_gcc_virtio_clocks,
    97. 

  97. 	.num_clks = ARRAY_SIZE(sm8150_gcc_virtio_clocks),
    98. 

  98. 	.reset_names = sm8150_gcc_virtio_resets,
    99. 

  99. 	.num_resets = ARRAY_SIZE(sm8150_gcc_virtio_resets),
    100. 

  100. };
    101. 

  101. EXPORT_SYMBOL(clk_virtio_sm8150_gcc);
    102. 

  102. 

  103. static const struct virtio_clk_init_data sm8150_scc_virtio_clocks[] = {
    104. 

  104. 	[SCC_QUPV3_SE0_CLK] = {.name = "scc_qupv3_se0_clk",},
    105. 

  105. 	[SCC_QUPV3_SE1_CLK] = {.name = "scc_qupv3_se1_clk",},
    106. 

  106. 	[SCC_QUPV3_SE2_CLK] = {.name = "scc_qupv3_se2_clk",},
    107. 

  107. 	[SCC_QUPV3_SE3_CLK] = {.name = "scc_qupv3_se3_clk",},
    108. 

  108. 	[SCC_QUPV3_M_HCLK_CLK] = {.name = "scc_qupv3_m_hclk_clk",},
    109. 

  109. 	[SCC_QUPV3_S_HCLK_CLK] = {.name = "scc_qupv3_s_hclk_clk",},
    110. 

  110. };
    111. 

  111. 

  112. const struct clk_virtio_desc clk_virtio_sm8150_scc = {
    113. 

  113. 	.clks = sm8150_scc_virtio_clocks,
    114. 

  114. 	.num_clks = ARRAY_SIZE(sm8150_scc_virtio_clocks),
    115. 

  115. };
    116. 

  116. EXPORT_SYMBOL(clk_virtio_sm8150_scc);
    117. 

  117. 

  118. MODULE_LICENSE("GPL");
    119.