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virtio_clk_sa8195p.c

virtio_clk_sa8195p.c 8.3 KB
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  1. // SPDX-License-Identifier: GPL-2.0-only
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved..
    4. 

  4.  */
    5. 

  5. 

  6. #include <linux/kernel.h>
    7. 

  7. #include <linux/module.h>
    8. 

  8. #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
    9. 

  9. #include "virtio_clk_common.h"
    10. 

  10. 

  11. static const struct virtio_clk_init_data sa8195p_gcc_virtio_clocks[] = {
    12. 

  12. 	[GCC_QUPV3_WRAP0_S0_CLK] = {.name = "gcc_qupv3_wrap0_s0_clk",},
    13. 

  13. 	[GCC_QUPV3_WRAP0_S1_CLK] = {.name = "gcc_qupv3_wrap0_s1_clk",},
    14. 

  14. 	[GCC_QUPV3_WRAP0_S2_CLK] = {.name = "gcc_qupv3_wrap0_s2_clk",},
    15. 

  15. 	[GCC_QUPV3_WRAP0_S3_CLK] = {.name = "gcc_qupv3_wrap0_s3_clk",},
    16. 

  16. 	[GCC_QUPV3_WRAP0_S4_CLK] = {.name = "gcc_qupv3_wrap0_s4_clk",},
    17. 

  17. 	[GCC_QUPV3_WRAP0_S5_CLK] = {.name = "gcc_qupv3_wrap0_s5_clk",},
    18. 

  18. 	[GCC_QUPV3_WRAP0_S6_CLK] = {.name = "gcc_qupv3_wrap0_s6_clk",},
    19. 

  19. 	[GCC_QUPV3_WRAP0_S7_CLK] = {.name = "gcc_qupv3_wrap0_s7_clk",},
    20. 

  20. 	[GCC_QUPV3_WRAP1_S0_CLK] = {.name = "gcc_qupv3_wrap1_s0_clk",},
    21. 

  21. 	[GCC_QUPV3_WRAP1_S1_CLK] = {.name = "gcc_qupv3_wrap1_s1_clk",},
    22. 

  22. 	[GCC_QUPV3_WRAP1_S2_CLK] = {.name = "gcc_qupv3_wrap1_s2_clk",},
    23. 

  23. 	[GCC_QUPV3_WRAP1_S3_CLK] = {.name = "gcc_qupv3_wrap1_s3_clk",},
    24. 

  24. 	[GCC_QUPV3_WRAP1_S4_CLK] = {.name = "gcc_qupv3_wrap1_s4_clk",},
    25. 

  25. 	[GCC_QUPV3_WRAP1_S5_CLK] = {.name = "gcc_qupv3_wrap1_s5_clk",},
    26. 

  26. 	[GCC_QUPV3_WRAP2_S0_CLK] = {.name = "gcc_qupv3_wrap2_s0_clk",},
    27. 

  27. 	[GCC_QUPV3_WRAP2_S1_CLK] = {.name = "gcc_qupv3_wrap2_s1_clk",},
    28. 

  28. 	[GCC_QUPV3_WRAP2_S2_CLK] = {.name = "gcc_qupv3_wrap2_s2_clk",},
    29. 

  29. 	[GCC_QUPV3_WRAP2_S3_CLK] = {.name = "gcc_qupv3_wrap2_s3_clk",},
    30. 

  30. 	[GCC_QUPV3_WRAP2_S4_CLK] = {.name = "gcc_qupv3_wrap2_s4_clk",},
    31. 

  31. 	[GCC_QUPV3_WRAP2_S5_CLK] = {.name = "gcc_qupv3_wrap2_s5_clk",},
    32. 

  32. 	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = {.name = "gcc_qupv3_wrap_0_m_ahb_clk",},
    33. 

  33. 	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = {.name = "gcc_qupv3_wrap_0_s_ahb_clk",},
    34. 

  34. 	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = {.name = "gcc_qupv3_wrap_1_m_ahb_clk",},
    35. 

  35. 	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = {.name = "gcc_qupv3_wrap_1_s_ahb_clk",},
    36. 

  36. 	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = {.name = "gcc_qupv3_wrap_2_m_ahb_clk",},
    37. 

  37. 	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = {.name = "gcc_qupv3_wrap_2_s_ahb_clk",},
    38. 

  38. 	[GCC_USB30_PRIM_MASTER_CLK] = {.name = "gcc_usb30_prim_master_clk",},
    39. 

  39. 	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = {.name = "gcc_cfg_noc_usb3_prim_axi_clk",},
    40. 

  40. 	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = {.name = "gcc_aggre_usb3_prim_axi_clk",},
    41. 

  41. 	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = {.name = "gcc_usb30_prim_mock_utmi_clk",},
    42. 

  42. 	[GCC_USB30_PRIM_SLEEP_CLK] = {.name = "gcc_usb30_prim_sleep_clk",},
    43. 

  43. 	[GCC_USB3_PRIM_PHY_AUX_CLK] = {.name = "gcc_usb3_prim_phy_aux_clk",},
    44. 

  44. 	[GCC_USB3_PRIM_PHY_PIPE_CLK] = {.name = "gcc_usb3_prim_phy_pipe_clk",},
    45. 

  45. 	[GCC_USB3_PRIM_CLKREF_CLK] = {.name = "gcc_usb3_prim_clkref_en",},
    46. 

  46. 	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = {.name = "gcc_usb3_prim_phy_com_aux_clk",},
    47. 

  47. 	[GCC_USB30_SEC_MASTER_CLK] = {.name = "gcc_usb30_sec_master_clk",},
    48. 

  48. 	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = {.name = "gcc_cfg_noc_usb3_sec_axi_clk",},
    49. 

  49. 	[GCC_AGGRE_USB3_SEC_AXI_CLK] = {.name = "gcc_aggre_usb3_sec_axi_clk",},
    50. 

  50. 	[GCC_USB30_SEC_MOCK_UTMI_CLK] = {.name = "gcc_usb30_sec_mock_utmi_clk",},
    51. 

  51. 	[GCC_USB30_SEC_SLEEP_CLK] = {.name = "gcc_usb30_sec_sleep_clk",},
    52. 

  52. 	[GCC_USB3_SEC_PHY_AUX_CLK] = {.name = "gcc_usb3_sec_phy_aux_clk",},
    53. 

  53. 	[GCC_USB3_SEC_PHY_PIPE_CLK] = {.name = "gcc_usb3_sec_phy_pipe_clk",},
    54. 

  54. 	[GCC_USB3_SEC_CLKREF_CLK] = {.name = "gcc_usb3_sec_clkref_en",},
    55. 

  55. 	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = {.name = "gcc_usb3_sec_phy_com_aux_clk",},
    56. 

  56. 	[GCC_USB30_MP_MASTER_CLK] = {.name = "gcc_usb30_mp_master_clk",},
    57. 

  57. 	[GCC_CFG_NOC_USB3_MP_AXI_CLK] = {.name = "gcc_cfg_noc_usb3_mp_axi_clk",},
    58. 

  58. 	[GCC_AGGRE_USB3_MP_AXI_CLK] = {.name = "gcc_aggre_usb3_mp_axi_clk",},
    59. 

  59. 	[GCC_USB30_MP_MOCK_UTMI_CLK] = {.name = "gcc_usb30_mp_mock_utmi_clk",},
    60. 

  60. 	[GCC_USB30_MP_SLEEP_CLK] = {.name = "gcc_usb30_mp_sleep_clk",},
    61. 

  61. 	[GCC_USB3_MP_PHY_AUX_CLK] = {.name = "gcc_usb3_mp_phy_aux_clk",},
    62. 

  62. 	[GCC_USB3_MP_PHY_PIPE_0_CLK] = {.name = "gcc_usb3_mp_phy_pipe_0_clk",},
    63. 

  63. 	[GCC_USB3_MP_PHY_COM_AUX_CLK] = {.name = "gcc_usb3_mp_phy_com_aux_clk",},
    64. 

  64. 	[GCC_USB3_MP_PHY_PIPE_1_CLK] = {.name = "gcc_usb3_mp_phy_pipe_1_clk",},
    65. 

  65. 	[GCC_PCIE_0_PIPE_CLK] = {.name = "gcc_pcie_0_pipe_clk",},
    66. 

  66. 	[GCC_PCIE_0_AUX_CLK] = {.name = "gcc_pcie_0_aux_clk",},
    67. 

  67. 	[GCC_PCIE_0_CFG_AHB_CLK] = {.name = "gcc_pcie_0_cfg_ahb_clk",},
    68. 

  68. 	[GCC_PCIE_0_MSTR_AXI_CLK] = {.name = "gcc_pcie_0_mstr_axi_clk",},
    69. 

  69. 	[GCC_PCIE_0_SLV_AXI_CLK] = {.name = "gcc_pcie_0_slv_axi_clk",},
    70. 

  70. 	[GCC_PCIE_0_CLKREF_CLK] = {.name = "gcc_pcie_0_clkref_en",},
    71. 

  71. 	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = {.name = "gcc_pcie_0_slv_q2a_axi_clk",},
    72. 

  72. 	[GCC_PCIE_1_PIPE_CLK] = {.name = "gcc_pcie_1_pipe_clk",},
    73. 

  73. 	[GCC_PCIE_1_AUX_CLK] = {.name = "gcc_pcie_1_aux_clk",},
    74. 

  74. 	[GCC_PCIE_1_CFG_AHB_CLK] = {.name = "gcc_pcie_1_cfg_ahb_clk",},
    75. 

  75. 	[GCC_PCIE_1_MSTR_AXI_CLK] = {.name = "gcc_pcie_1_mstr_axi_clk",},
    76. 

  76. 	[GCC_PCIE_1_SLV_AXI_CLK] = {.name = "gcc_pcie_1_slv_axi_clk",},
    77. 

  77. 	[GCC_PCIE_1_CLKREF_CLK] = {.name = "gcc_pcie_1_clkref_en",},
    78. 

  78. 	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = {.name = "gcc_pcie_1_slv_q2a_axi_clk",},
    79. 

  79. 	[GCC_PCIE_2_PIPE_CLK] = {.name = "gcc_pcie_2_pipe_clk",},
    80. 

  80. 	[GCC_PCIE_2_AUX_CLK] = {.name = "gcc_pcie_2_aux_clk",},
    81. 

  81. 	[GCC_PCIE_2_CFG_AHB_CLK] = {.name = "gcc_pcie_2_cfg_ahb_clk",},
    82. 

  82. 	[GCC_PCIE_2_MSTR_AXI_CLK] = {.name = "gcc_pcie_2_mstr_axi_clk",},
    83. 

  83. 	[GCC_PCIE_2_SLV_AXI_CLK] = {.name = "gcc_pcie_2_slv_axi_clk",},
    84. 

  84. 	[GCC_PCIE_2_CLKREF_CLK] = {.name = "gcc_pcie_2_clkref_en",},
    85. 

  85. 	[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = {.name = "gcc_pcie_2_slv_q2a_axi_clk",},
    86. 

  86. 	[GCC_PCIE_3_PIPE_CLK] = {.name = "gcc_pcie_3_pipe_clk",},
    87. 

  87. 	[GCC_PCIE_3_AUX_CLK] = {.name = "gcc_pcie_3_aux_clk",},
    88. 

  88. 	[GCC_PCIE_3_CFG_AHB_CLK] = {.name = "gcc_pcie_3_cfg_ahb_clk",},
    89. 

  89. 	[GCC_PCIE_3_MSTR_AXI_CLK] = {.name = "gcc_pcie_3_mstr_axi_clk",},
    90. 

  90. 	[GCC_PCIE_3_SLV_AXI_CLK] = {.name = "gcc_pcie_3_slv_axi_clk",},
    91. 

  91. 	[GCC_PCIE_3_CLKREF_CLK] = {.name = "gcc_pcie_3_clkref_en",},
    92. 

  92. 	[GCC_PCIE_3_SLV_Q2A_AXI_CLK] = {.name = "gcc_pcie_3_slv_q2a_axi_clk",},
    93. 

  93. 	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = {.name = "gcc_aggre_noc_pcie_tbu_clk",},
    94. 

  94. 	[GCC_PCIE0_PHY_REFGEN_CLK] = {.name = "gcc_pcie0_phy_refgen_clk",},
    95. 

  95. 	[GCC_PCIE1_PHY_REFGEN_CLK] = {.name = "gcc_pcie1_phy_refgen_clk",},
    96. 

  96. 	[GCC_PCIE2_PHY_REFGEN_CLK] = {.name = "gcc_pcie2_phy_refgen_clk",},
    97. 

  97. 	[GCC_PCIE3_PHY_REFGEN_CLK] = {.name = "gcc_pcie3_phy_refgen_clk",},
    98. 

  98. 	[GCC_PCIE_PHY_AUX_CLK] = {.name = "gcc_pcie_phy_aux_clk",},
    99. 

  99. 	[GCC_SDCC2_AHB_CLK] = {.name = "gcc_sdcc2_ahb_clk",},
    100. 

  100. 	[GCC_SDCC2_APPS_CLK] = {.name = "gcc_sdcc2_apps_clk",},
    101. 

  101. 	[GCC_PRNG_AHB_CLK] = {.name = "gcc_prng_ahb_clk",},
    102. 

  102. 	[GCC_UFS_PHY_ICE_CORE_CLK] = {.name = "gcc_ufs_phy_ice_core_clk",},
    103. 

  103. 	[GCC_UFS_CARD_2_AHB_CLK] = {.name = "gcc_ufs_card_2_ahb_clk",},
    104. 

  104. 	[GCC_UFS_CARD_2_ICE_CORE_CLK] = {.name = "gcc_ufs_card_2_ice_core_clk",},
    105. 

  105. 	[GCC_UFS_CARD_2_PHY_AUX_CLK] = {.name = "gcc_ufs_card_2_phy_aux_clk",},
    106. 

  106. 	[GCC_UFS_CARD_2_AXI_CLK] = {.name = "gcc_ufs_card_2_axi_clk",},
    107. 

  107. 	[GCC_AGGRE_UFS_CARD_2_AXI_CLK] = {.name = "gcc_aggre_ufs_card_2_axi_clk",},
    108. 

  108. 	[GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = {.name = "gcc_ufs_card_2_unipro_core_clk",},
    109. 

  109. 	[GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = {.name = "gcc_ufs_card_2_tx_symbol_0_clk",},
    110. 

  110. 	[GCC_UFS_CARD_2_RX_SYMBOL_0_CLK] = {.name = "gcc_ufs_card_2_rx_symbol_0_clk",},
    111. 

  111. 	[GCC_UFS_CARD_2_RX_SYMBOL_1_CLK] = {.name = "gcc_ufs_card_2_rx_symbol_1_clk",},
    112. 

  112. };
    113. 

  113. 

  114. static const char * const sa8195p_gcc_virtio_resets[] = {
    115. 

  115. 	[GCC_QUSB2PHY_PRIM_BCR] = "gcc_qusb2phy_prim_bcr",
    116. 

  116. 	[GCC_QUSB2PHY_SEC_BCR] = "gcc_qusb2phy_sec_bcr",
    117. 

  117. 	[GCC_QUSB2PHY_MP0_BCR] = "gcc_qusb2phy_mp0_bcr",
    118. 

  118. 	[GCC_QUSB2PHY_MP1_BCR] = "gcc_qusb2phy_mp1_bcr",
    119. 

  119. 	[GCC_USB30_PRIM_BCR] = "gcc_usb30_prim_master_clk",
    120. 

  120. 	[GCC_USB30_SEC_BCR] = "gcc_usb30_sec_master_clk",
    121. 

  121. 	[GCC_USB30_MP_BCR] = "gcc_usb30_mp_master_clk",
    122. 

  122. 	[GCC_USB3_UNIPHY_MP0_BCR] = "gcc_usb3_uniphy_mp0_bcr",
    123. 

  123. 	[GCC_USB3UNIPHY_PHY_MP0_BCR] = "gcc_usb3uniphy_phy_mp0_bcr",
    124. 

  124. 	[GCC_USB3_UNIPHY_MP1_BCR] = "gcc_usb3_uniphy_mp1_bcr",
    125. 

  125. 	[GCC_USB3UNIPHY_PHY_MP1_BCR] = "gcc_usb3uniphy_phy_mp1_bcr",
    126. 

  126. 	[GCC_PCIE_0_BCR] = "gcc_pcie_0_mstr_axi_clk",
    127. 

  127. 	[GCC_PCIE_0_PHY_BCR] = "gcc_pcie_0_phy_bcr",
    128. 

  128. 	[GCC_PCIE_1_BCR] = "gcc_pcie_1_mstr_axi_clk",
    129. 

  129. 	[GCC_PCIE_1_PHY_BCR] = "gcc_pcie_1_phy_bcr",
    130. 

  130. 	[GCC_PCIE_2_BCR] = "gcc_pcie_2_mstr_axi_clk",
    131. 

  131. 	[GCC_PCIE_2_PHY_BCR] = "gcc_pcie_2_phy_bcr",
    132. 

  132. 	[GCC_PCIE_3_BCR] = "gcc_pcie_3_mstr_axi_clk",
    133. 

  133. 	[GCC_PCIE_3_PHY_BCR] = "gcc_pcie_3_phy_bcr",
    134. 

  134. 	[GCC_UFS_CARD_2_BCR] = "gcc_ufs_card_2_axi_clk",
    135. 

  135. };
    136. 

  136. 

  137. const struct clk_virtio_desc clk_virtio_sa8195p_gcc = {
    138. 

  138. 	.clks = sa8195p_gcc_virtio_clocks,
    139. 

  139. 	.num_clks = ARRAY_SIZE(sa8195p_gcc_virtio_clocks),
    140. 

  140. 	.reset_names = sa8195p_gcc_virtio_resets,
    141. 

  141. 	.num_resets = ARRAY_SIZE(sa8195p_gcc_virtio_resets),
    142. 

  142. };
    143. 

  143. EXPORT_SYMBOL(clk_virtio_sa8195p_gcc);
    144. 

  144. 

  145. MODULE_LICENSE("GPL");
    146.