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virtio_clk_lemans.c

virtio_clk_lemans.c 8.5 KB
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  1. // SPDX-License-Identifier: GPL-2.0-only
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #include <linux/kernel.h>
    7. 

  7. #include <linux/module.h>
    8. 

  8. #include <dt-bindings/clock/qcom,gcc-lemans.h>
    9. 

  9. #include "virtio_clk_common.h"
    10. 

  10. 

  11. static const char * const lemans_gcc_parent_names_usb_prim[] = {
    12. 

  12. 	"usb3_phy_wrapper_gcc_usb30_pipe_clk",
    13. 

  13. 	"core_bi_pll_test_se",
    14. 

  14. 	"bi_tcxo",
    15. 

  15. };
    16. 

  16. 

  17. static const char * const lemans_gcc_parent_names_usb_sec[] = {
    18. 

  18. 	"usb3_uni_phy_sec_gcc_usb30_pipe_clk",
    19. 

  19. 	"core_bi_pll_test_se",
    20. 

  20. 	"bi_tcxo",
    21. 

  21. };
    22. 

  22. 

  23. static const char * const lemans_gcc_parent_names_pcie_0[] = {
    24. 

  24. 	"pcie_0_pipe_clk",
    25. 

  25. 	"gcc_pcie_mbist_pll_test_se_clk_src",
    26. 

  26. 	"bi_tcxo",
    27. 

  27. };
    28. 

  28. 

  29. static const char * const lemans_gcc_parent_names_pcie_1[] = {
    30. 

  30. 	"pcie_1_pipe_clk",
    31. 

  31. 	"gcc_pcie_mbist_pll_test_se_clk_src",
    32. 

  32. 	"bi_tcxo",
    33. 

  33. };
    34. 

  34. 

  35. static const struct virtio_clk_init_data lemans_gcc_virtio_clocks[] = {
    36. 

  36. 	[GCC_QUPV3_WRAP0_S0_CLK] = {.name = "gcc_qupv3_wrap0_s0_clk",},
    37. 

  37. 	[GCC_QUPV3_WRAP0_S1_CLK] = {.name = "gcc_qupv3_wrap0_s1_clk",},
    38. 

  38. 	[GCC_QUPV3_WRAP0_S2_CLK] = {.name = "gcc_qupv3_wrap0_s2_clk",},
    39. 

  39. 	[GCC_QUPV3_WRAP0_S3_CLK] = {.name = "gcc_qupv3_wrap0_s3_clk",},
    40. 

  40. 	[GCC_QUPV3_WRAP0_S4_CLK] = {.name = "gcc_qupv3_wrap0_s4_clk",},
    41. 

  41. 	[GCC_QUPV3_WRAP0_S5_CLK] = {.name = "gcc_qupv3_wrap0_s5_clk",},
    42. 

  42. 	[GCC_QUPV3_WRAP0_S6_CLK] = {.name = "gcc_qupv3_wrap0_s6_clk",},
    43. 

  43. 	[GCC_QUPV3_WRAP1_S0_CLK] = {.name = "gcc_qupv3_wrap1_s0_clk",},
    44. 

  44. 	[GCC_QUPV3_WRAP1_S1_CLK] = {.name = "gcc_qupv3_wrap1_s1_clk",},
    45. 

  45. 	[GCC_QUPV3_WRAP1_S2_CLK] = {.name = "gcc_qupv3_wrap1_s2_clk",},
    46. 

  46. 	[GCC_QUPV3_WRAP1_S3_CLK] = {.name = "gcc_qupv3_wrap1_s3_clk",},
    47. 

  47. 	[GCC_QUPV3_WRAP1_S4_CLK] = {.name = "gcc_qupv3_wrap1_s4_clk",},
    48. 

  48. 	[GCC_QUPV3_WRAP1_S5_CLK] = {.name = "gcc_qupv3_wrap1_s5_clk",},
    49. 

  49. 	[GCC_QUPV3_WRAP1_S6_CLK] = {.name = "gcc_qupv3_wrap1_s6_clk",},
    50. 

  50. 	[GCC_QUPV3_WRAP2_S0_CLK] = {.name = "gcc_qupv3_wrap2_s0_clk",},
    51. 

  51. 	[GCC_QUPV3_WRAP2_S1_CLK] = {.name = "gcc_qupv3_wrap2_s1_clk",},
    52. 

  52. 	[GCC_QUPV3_WRAP2_S2_CLK] = {.name = "gcc_qupv3_wrap2_s2_clk",},
    53. 

  53. 	[GCC_QUPV3_WRAP2_S3_CLK] = {.name = "gcc_qupv3_wrap2_s3_clk",},
    54. 

  54. 	[GCC_QUPV3_WRAP2_S4_CLK] = {.name = "gcc_qupv3_wrap2_s4_clk",},
    55. 

  55. 	[GCC_QUPV3_WRAP2_S5_CLK] = {.name = "gcc_qupv3_wrap2_s5_clk",},
    56. 

  56. 	[GCC_QUPV3_WRAP2_S6_CLK] = {.name = "gcc_qupv3_wrap2_s6_clk",},
    57. 

  57. 	[GCC_QUPV3_WRAP3_S0_CLK] = {.name = "gcc_qupv3_wrap3_s0_clk",},
    58. 

  58. 	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = {.name = "gcc_qupv3_wrap_0_m_ahb_clk",},
    59. 

  59. 	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = {.name = "gcc_qupv3_wrap_0_s_ahb_clk",},
    60. 

  60. 	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = {.name = "gcc_qupv3_wrap_1_m_ahb_clk",},
    61. 

  61. 	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = {.name = "gcc_qupv3_wrap_1_s_ahb_clk",},
    62. 

  62. 	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = {.name = "gcc_qupv3_wrap_2_m_ahb_clk",},
    63. 

  63. 	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = {.name = "gcc_qupv3_wrap_2_s_ahb_clk",},
    64. 

  64. 	[GCC_QUPV3_WRAP_3_M_AHB_CLK] = {.name = "gcc_qupv3_wrap_3_m_ahb_clk",},
    65. 

  65. 	[GCC_QUPV3_WRAP_3_S_AHB_CLK] = {.name = "gcc_qupv3_wrap_3_s_ahb_clk",},
    66. 

  66. 	[GCC_USB30_PRIM_MASTER_CLK] = {.name = "gcc_usb30_prim_master_clk",},
    67. 

  67. 	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = {.name = "gcc_cfg_noc_usb3_prim_axi_clk",},
    68. 

  68. 	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = {.name = "gcc_aggre_usb3_prim_axi_clk",},
    69. 

  69. 	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = {.name = "gcc_usb30_prim_mock_utmi_clk",},
    70. 

  70. 	[GCC_USB30_PRIM_SLEEP_CLK] = {.name = "gcc_usb30_prim_sleep_clk",},
    71. 

  71. 	[GCC_USB3_PRIM_PHY_AUX_CLK] = {.name = "gcc_usb3_prim_phy_aux_clk",},
    72. 

  72. 	[GCC_USB3_PRIM_PHY_PIPE_CLK] = {.name = "gcc_usb3_prim_phy_pipe_clk",},
    73. 

  73. 	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = {
    74. 

  74. 				.name = "gcc_usb3_prim_phy_pipe_clk_src",
    75. 

  75. 				.parent_names = lemans_gcc_parent_names_usb_prim,
    76. 

  76. 				.num_parents = ARRAY_SIZE(lemans_gcc_parent_names_usb_prim),
    77. 

  77. 				},
    78. 

  78. 	[GCC_USB_CLKREF_EN] = {.name = "gcc_usb_clkref_en",},
    79. 

  79. 	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = {.name = "gcc_usb3_prim_phy_com_aux_clk",},
    80. 

  80. 	[GCC_USB30_SEC_MASTER_CLK] = {.name = "gcc_usb30_sec_master_clk",},
    81. 

  81. 	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = {.name = "gcc_cfg_noc_usb3_sec_axi_clk",},
    82. 

  82. 	[GCC_AGGRE_USB3_SEC_AXI_CLK] = {.name = "gcc_aggre_usb3_sec_axi_clk",},
    83. 

  83. 	[GCC_USB30_SEC_MOCK_UTMI_CLK] = {.name = "gcc_usb30_sec_mock_utmi_clk",},
    84. 

  84. 	[GCC_USB30_SEC_SLEEP_CLK] = {.name = "gcc_usb30_sec_sleep_clk",},
    85. 

  85. 	[GCC_USB3_SEC_PHY_AUX_CLK] = {.name = "gcc_usb3_sec_phy_aux_clk",},
    86. 

  86. 	[GCC_USB3_SEC_PHY_PIPE_CLK] = {.name = "gcc_usb3_sec_phy_pipe_clk",},
    87. 

  87. 	[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = {
    88. 

  88. 				.name = "gcc_usb3_sec_phy_pipe_clk_src",
    89. 

  89. 				.parent_names = lemans_gcc_parent_names_usb_sec,
    90. 

  90. 				.num_parents = ARRAY_SIZE(lemans_gcc_parent_names_usb_sec),
    91. 

  91. 				},
    92. 

  92. 	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = {.name = "gcc_usb3_sec_phy_com_aux_clk",},
    93. 

  93. 	[GCC_USB20_MASTER_CLK] = {.name = "gcc_usb20_master_clk",},
    94. 

  94. 	[GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = {.name = "gcc_cfg_noc_usb2_prim_axi_clk",},
    95. 

  95. 	[GCC_AGGRE_USB2_PRIM_AXI_CLK] = {.name = "gcc_aggre_usb2_prim_axi_clk",},
    96. 

  96. 	[GCC_USB20_MOCK_UTMI_CLK] = {.name = "gcc_usb20_mock_utmi_clk",},
    97. 

  97. 	[GCC_USB20_SLEEP_CLK] = {.name = "gcc_usb20_sleep_clk",},
    98. 

  98. 	[GCC_PCIE_0_PIPE_CLK] = {.name = "gcc_pcie_0_pipe_clk",},
    99. 

  99. 	[GCC_PCIE_0_AUX_CLK] = {.name = "gcc_pcie_0_aux_clk",},
    100. 

  100. 	[GCC_PCIE_0_CFG_AHB_CLK] = {.name = "gcc_pcie_0_cfg_ahb_clk",},
    101. 

  101. 	[GCC_PCIE_0_MSTR_AXI_CLK] = {.name = "gcc_pcie_0_mstr_axi_clk",},
    102. 

  102. 	[GCC_PCIE_0_SLV_AXI_CLK] = {.name = "gcc_pcie_0_slv_axi_clk",},
    103. 

  103. 	[GCC_PCIE_CLKREF_EN] = {.name = "gcc_pcie_clkref_en",},
    104. 

  104. 	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = {.name = "gcc_pcie_0_slv_q2a_axi_clk",},
    105. 

  105. 	[GCC_PCIE_0_PHY_RCHNG_CLK] = {.name = "gcc_pcie_0_phy_rchng_clk",},
    106. 

  106. 	[GCC_PCIE_0_PHY_AUX_CLK] = {.name = "gcc_pcie_0_phy_aux_clk",},
    107. 

  107. 	[GCC_PCIE_0_PIPEDIV2_CLK] = {.name = "gcc_pcie_0_pipediv2_clk",},
    108. 

  108. 	[GCC_PCIE_0_PIPE_CLK_SRC] = {
    109. 

  109. 				.name = "gcc_pcie_0_pipe_clk_src",
    110. 

  110. 				.parent_names = lemans_gcc_parent_names_pcie_0,
    111. 

  111. 				.num_parents = ARRAY_SIZE(lemans_gcc_parent_names_pcie_0),
    112. 

  112. 				},
    113. 

  113. 	[GCC_PCIE_1_PIPE_CLK] = {.name = "gcc_pcie_1_pipe_clk",},
    114. 

  114. 	[GCC_PCIE_1_AUX_CLK] = {.name = "gcc_pcie_1_aux_clk",},
    115. 

  115. 	[GCC_PCIE_1_CFG_AHB_CLK] = {.name = "gcc_pcie_1_cfg_ahb_clk",},
    116. 

  116. 	[GCC_PCIE_1_MSTR_AXI_CLK] = {.name = "gcc_pcie_1_mstr_axi_clk",},
    117. 

  117. 	[GCC_PCIE_1_SLV_AXI_CLK] = {.name = "gcc_pcie_1_slv_axi_clk",},
    118. 

  118. 	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = {.name = "gcc_pcie_1_slv_q2a_axi_clk",},
    119. 

  119. 	[GCC_PCIE_1_PHY_RCHNG_CLK] = {.name = "gcc_pcie_1_phy_rchng_clk",},
    120. 

  120. 	[GCC_PCIE_1_PHY_AUX_CLK] = {.name = "gcc_pcie_1_phy_aux_clk",},
    121. 

  121. 	[GCC_PCIE_1_PIPEDIV2_CLK] = {.name = "gcc_pcie_1_pipediv2_clk",},
    122. 

  122. 	[GCC_PCIE_1_PIPE_CLK_SRC] = {
    123. 

  123. 				.name = "gcc_pcie_1_pipe_clk_src",
    124. 

  124. 				.parent_names = lemans_gcc_parent_names_pcie_1,
    125. 

  125. 				.num_parents = ARRAY_SIZE(lemans_gcc_parent_names_pcie_1),
    126. 

  126. 				},
    127. 

  127. 	[GCC_EDP_REF_CLKREF_EN] = {.name = "gcc_edp_ref_clkref_en",},
    128. 

  128. 	[GCC_UFS_CARD_PHY_AUX_CLK] = {.name = "gcc_ufs_card_phy_aux_clk",},
    129. 

  129. 	[GCC_UFS_CARD_AXI_CLK] = {.name = "gcc_ufs_card_axi_clk",},
    130. 

  130. 	[GCC_AGGRE_UFS_CARD_AXI_CLK] = {.name = "gcc_aggre_ufs_card_axi_clk",},
    131. 

  131. 	[GCC_UFS_CARD_AHB_CLK] = {.name = "gcc_ufs_card_ahb_clk",},
    132. 

  132. 	[GCC_UFS_CARD_UNIPRO_CORE_CLK] = {.name = "gcc_ufs_card_unipro_core_clk",},
    133. 

  133. 	[GCC_UFS_CARD_ICE_CORE_CLK] = {.name = "gcc_ufs_card_ice_core_clk",},
    134. 

  134. 	[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = {.name = "gcc_ufs_card_tx_symbol_0_clk",},
    135. 

  135. 	[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = {.name = "gcc_ufs_card_rx_symbol_0_clk",},
    136. 

  136. 	[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = {.name = "gcc_ufs_card_rx_symbol_1_clk",},
    137. 

  137. 	[GCC_EMAC1_AXI_CLK] = {.name = "gcc_emac1_axi_clk",},
    138. 

  138. 	[GCC_EMAC1_SLV_AHB_CLK] = {.name = "gcc_emac1_slv_ahb_clk",},
    139. 

  139. 	[GCC_EMAC1_PTP_CLK] = {.name = "gcc_emac1_ptp_clk",},
    140. 

  140. 	[GCC_EMAC1_PHY_AUX_CLK] = {.name = "gcc_emac1_phy_aux_clk",},
    141. 

  141. 	[GCC_SGMI_CLKREF_EN] = {.name = "gcc_sgmi_clkref_en",},
    142. 

  142. 	[GCC_EMAC1_RGMII_CLK] = {.name = "gcc_emac1_rgmii_clk",},
    143. 

  143. };
    144. 

  144. 

  145. static const char * const lemans_gcc_virtio_resets[] = {
    146. 

  146. 	[GCC_USB30_PRIM_BCR] = "gcc_usb30_prim_master_clk",
    147. 

  147. 	[GCC_USB2_PHY_PRIM_BCR] = "gcc_usb2_phy_prim_bcr",
    148. 

  148. 	[GCC_USB3_PHY_PRIM_BCR] = "gcc_usb3_phy_prim_bcr",
    149. 

  149. 	[GCC_USB3PHY_PHY_PRIM_BCR] = "gcc_usb3phy_phy_prim_bcr",
    150. 

  150. 	[GCC_USB30_SEC_BCR] = "gcc_usb30_sec_master_clk",
    151. 

  151. 	[GCC_USB2_PHY_SEC_BCR] = "gcc_usb2_phy_sec_bcr",
    152. 

  152. 	[GCC_USB3_PHY_SEC_BCR] = "gcc_usb3_phy_sec_bcr",
    153. 

  153. 	[GCC_USB3PHY_PHY_SEC_BCR] = "gcc_usb3phy_phy_sec_bcr",
    154. 

  154. 	[GCC_USB3_PHY_TERT_BCR] = "gcc_usb3_phy_tert_bcr",
    155. 

  155. 	[GCC_USB20_PRIM_BCR] = "gcc_usb20_master_clk",
    156. 

  156. 	[GCC_PCIE_0_BCR] = "gcc_pcie_0_bcr",
    157. 

  157. 	[GCC_PCIE_0_PHY_BCR] = "gcc_pcie_0_phy_bcr",
    158. 

  158. 	[GCC_PCIE_1_BCR] = "gcc_pcie_1_bcr",
    159. 

  159. 	[GCC_PCIE_1_PHY_BCR] = "gcc_pcie_1_phy_bcr",
    160. 

  160. 	[GCC_UFS_CARD_BCR] = "gcc_ufs_card_bcr",
    161. 

  161. };
    162. 

  162. 

  163. const struct clk_virtio_desc clk_virtio_lemans_gcc = {
    164. 

  164. 	.clks = lemans_gcc_virtio_clocks,
    165. 

  165. 	.num_clks = ARRAY_SIZE(lemans_gcc_virtio_clocks),
    166. 

  166. 	.reset_names = lemans_gcc_virtio_resets,
    167. 

  167. 	.num_resets = ARRAY_SIZE(lemans_gcc_virtio_resets),
    168. 

  168. };
    169. 

  169. EXPORT_SYMBOL(clk_virtio_lemans_gcc);
    170. 

  170. 

  171. MODULE_LICENSE("GPL");
    172.