videocc-sm8150.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/regmap.h>
  10. #include <dt-bindings/clock/qcom,videocc-sm8150.h>
  11. #include "common.h"
  12. #include "clk-alpha-pll.h"
  13. #include "clk-branch.h"
  14. #include "clk-rcg.h"
  15. #include "clk-regmap.h"
  16. #include "reset.h"
  17. #include "gdsc.h"
  18. #include "vdd-level-sm8150.h"
  19. #include "clk-pm.h"
  20. static DEFINE_VDD_REGULATORS(vdd_mm, VDD_HIGH + 1, 1, vdd_corner);
  21. static struct clk_vdd_class *video_cc_sm8150_regulators[] = {
  22. &vdd_mm,
  23. };
  24. enum {
  25. P_BI_TCXO,
  26. P_VIDEO_PLL0_OUT_MAIN,
  27. };
  28. static struct pll_vco trion_vco[] = {
  29. { 249600000, 2000000000, 0 },
  30. };
  31. /* 400 MHz configuration */
  32. static struct alpha_pll_config video_pll0_config = {
  33. .l = 0x14,
  34. .alpha = 0xD555,
  35. .config_ctl_val = 0x20485699,
  36. .config_ctl_hi_val = 0x00002267,
  37. .config_ctl_hi1_val = 0x00000024,
  38. .test_ctl_val = 0x00000000,
  39. .test_ctl_hi_val = 0x00000000,
  40. .test_ctl_hi1_val = 0x00000020,
  41. .user_ctl_val = 0x00000000,
  42. .user_ctl_hi_val = 0x00000805,
  43. .user_ctl_hi1_val = 0x000000D0,
  44. };
  45. static struct clk_alpha_pll video_pll0 = {
  46. .offset = 0x42c,
  47. .vco_table = trion_vco,
  48. .num_vco = ARRAY_SIZE(trion_vco),
  49. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  50. .config = &video_pll0_config,
  51. .clkr = {
  52. .hw.init = &(struct clk_init_data){
  53. .name = "video_pll0",
  54. .parent_data = &(const struct clk_parent_data){
  55. .fw_name = "bi_tcxo",
  56. },
  57. .num_parents = 1,
  58. .ops = &clk_alpha_pll_trion_ops,
  59. },
  60. .vdd_data = {
  61. .vdd_class = &vdd_mm,
  62. .num_rate_max = VDD_NUM,
  63. .rate_max = (unsigned long[VDD_NUM]) {
  64. [VDD_MIN] = 615000000,
  65. [VDD_LOW] = 1066000000,
  66. [VDD_LOW_L1] = 1600000000,
  67. [VDD_NOMINAL] = 2000000000},
  68. },
  69. },
  70. };
  71. static const struct parent_map video_cc_parent_map_0[] = {
  72. { P_BI_TCXO, 0 },
  73. { P_VIDEO_PLL0_OUT_MAIN, 1 },
  74. };
  75. static const struct clk_parent_data video_cc_parent_data_0[] = {
  76. { .fw_name = "bi_tcxo" },
  77. { .hw = &video_pll0.clkr.hw },
  78. };
  79. static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
  80. F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  81. F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  82. F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  83. F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  84. F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  85. F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  86. { }
  87. };
  88. static struct clk_rcg2 video_cc_iris_clk_src = {
  89. .cmd_rcgr = 0x7f0,
  90. .mnd_width = 0,
  91. .hid_width = 5,
  92. .parent_map = video_cc_parent_map_0,
  93. .freq_tbl = ftbl_video_cc_iris_clk_src,
  94. .enable_safe_config = true,
  95. .clkr.hw.init = &(struct clk_init_data){
  96. .name = "video_cc_iris_clk_src",
  97. .parent_data = video_cc_parent_data_0,
  98. .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
  99. .flags = CLK_SET_RATE_PARENT,
  100. .ops = &clk_rcg2_ops,
  101. },
  102. .clkr.vdd_data = {
  103. .vdd_class = &vdd_mm,
  104. .num_rate_max = VDD_NUM,
  105. .rate_max = (unsigned long[VDD_NUM]) {
  106. [VDD_MIN] = 200000000,
  107. [VDD_LOWER] = 240000000,
  108. [VDD_LOW] = 338000000,
  109. [VDD_LOW_L1] = 365000000,
  110. [VDD_NOMINAL] = 444000000,
  111. [VDD_HIGH] = 533000000},
  112. },
  113. };
  114. static struct clk_branch video_cc_iris_ahb_clk = {
  115. .halt_reg = 0x8f4,
  116. .halt_check = BRANCH_VOTED,
  117. .clkr = {
  118. .enable_reg = 0x8f4,
  119. .enable_mask = BIT(0),
  120. .hw.init = &(struct clk_init_data){
  121. .name = "video_cc_iris_ahb_clk",
  122. .parent_hws = (const struct clk_hw*[]){
  123. &video_cc_iris_clk_src.clkr.hw,
  124. },
  125. .num_parents = 1,
  126. .flags = CLK_SET_RATE_PARENT,
  127. .ops = &clk_branch2_ops,
  128. },
  129. },
  130. };
  131. static struct clk_branch video_cc_mvs0_core_clk = {
  132. .halt_reg = 0x890,
  133. .halt_check = BRANCH_VOTED,
  134. .clkr = {
  135. .enable_reg = 0x890,
  136. .enable_mask = BIT(0),
  137. .hw.init = &(struct clk_init_data){
  138. .name = "video_cc_mvs0_core_clk",
  139. .parent_hws = (const struct clk_hw*[]){
  140. &video_cc_iris_clk_src.clkr.hw,
  141. },
  142. .num_parents = 1,
  143. .flags = CLK_SET_RATE_PARENT,
  144. .ops = &clk_branch2_ops,
  145. },
  146. },
  147. };
  148. static struct clk_branch video_cc_mvs1_core_clk = {
  149. .halt_reg = 0x8d0,
  150. .halt_check = BRANCH_VOTED,
  151. .clkr = {
  152. .enable_reg = 0x8d0,
  153. .enable_mask = BIT(0),
  154. .hw.init = &(struct clk_init_data){
  155. .name = "video_cc_mvs1_core_clk",
  156. .parent_hws = (const struct clk_hw*[]){
  157. &video_cc_iris_clk_src.clkr.hw,
  158. },
  159. .num_parents = 1,
  160. .flags = CLK_SET_RATE_PARENT,
  161. .ops = &clk_branch2_ops,
  162. },
  163. },
  164. };
  165. static struct clk_branch video_cc_mvsc_core_clk = {
  166. .halt_reg = 0x850,
  167. .halt_check = BRANCH_HALT,
  168. .clkr = {
  169. .enable_reg = 0x850,
  170. .enable_mask = BIT(0),
  171. .hw.init = &(struct clk_init_data){
  172. .name = "video_cc_mvsc_core_clk",
  173. .parent_hws = (const struct clk_hw*[]){
  174. &video_cc_iris_clk_src.clkr.hw,
  175. },
  176. .num_parents = 1,
  177. .flags = CLK_SET_RATE_PARENT,
  178. .ops = &clk_branch2_ops,
  179. },
  180. },
  181. };
  182. static struct gdsc venus_gdsc = {
  183. .gdscr = 0x814,
  184. .pd = {
  185. .name = "venus_gdsc",
  186. },
  187. .flags = 0,
  188. .pwrsts = PWRSTS_OFF_ON,
  189. };
  190. static struct gdsc vcodec0_gdsc = {
  191. .gdscr = 0x874,
  192. .pd = {
  193. .name = "vcodec0_gdsc",
  194. },
  195. .flags = 0,
  196. .pwrsts = PWRSTS_OFF_ON,
  197. };
  198. static struct gdsc vcodec1_gdsc = {
  199. .gdscr = 0x8b4,
  200. .pd = {
  201. .name = "vcodec1_gdsc",
  202. },
  203. .flags = 0,
  204. .pwrsts = PWRSTS_OFF_ON,
  205. };
  206. static struct critical_clk_offset critical_clk_list[] = {
  207. { .offset = 0x984, .mask = BIT(1) },
  208. };
  209. static struct clk_regmap *video_cc_sm8150_clocks[] = {
  210. [VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
  211. [VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
  212. [VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
  213. [VIDEO_CC_MVS1_CORE_CLK] = &video_cc_mvs1_core_clk.clkr,
  214. [VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
  215. [VIDEO_CC_PLL0] = &video_pll0.clkr,
  216. };
  217. static struct gdsc *video_cc_sm8150_gdscs[] = {
  218. [VENUS_GDSC] = &venus_gdsc,
  219. [VCODEC0_GDSC] = &vcodec0_gdsc,
  220. [VCODEC1_GDSC] = &vcodec1_gdsc,
  221. };
  222. static const struct regmap_config video_cc_sm8150_regmap_config = {
  223. .reg_bits = 32,
  224. .reg_stride = 4,
  225. .val_bits = 32,
  226. .max_register = 0xb94,
  227. .fast_io = true,
  228. };
  229. static const struct qcom_reset_map video_cc_sm8150_resets[] = {
  230. [VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },
  231. [VIDEO_CC_MVS0_BCR] = { 0x870 },
  232. [VIDEO_CC_MVS1_BCR] = { 0x8b0 },
  233. [VIDEO_CC_MVSC_BCR] = { 0x810 },
  234. [VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
  235. };
  236. static struct qcom_cc_desc video_cc_sm8150_desc = {
  237. .config = &video_cc_sm8150_regmap_config,
  238. .clks = video_cc_sm8150_clocks,
  239. .num_clks = ARRAY_SIZE(video_cc_sm8150_clocks),
  240. .resets = video_cc_sm8150_resets,
  241. .num_resets = ARRAY_SIZE(video_cc_sm8150_resets),
  242. .clk_regulators = video_cc_sm8150_regulators,
  243. .num_clk_regulators = ARRAY_SIZE(video_cc_sm8150_regulators),
  244. .gdscs = video_cc_sm8150_gdscs,
  245. .num_gdscs = ARRAY_SIZE(video_cc_sm8150_gdscs),
  246. .critical_clk_en = critical_clk_list,
  247. .num_critical_clk = ARRAY_SIZE(critical_clk_list),
  248. };
  249. static const struct of_device_id video_cc_sm8150_match_table[] = {
  250. { .compatible = "qcom,sm8150-videocc" },
  251. { .compatible = "qcom,sa8155-videocc" },
  252. { }
  253. };
  254. MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table);
  255. static int video_cc_sm8150_probe(struct platform_device *pdev)
  256. {
  257. struct regmap *regmap;
  258. int ret;
  259. regmap = qcom_cc_map(pdev, &video_cc_sm8150_desc);
  260. if (IS_ERR(regmap)) {
  261. pr_err("Failed to map the Video CC registers\n");
  262. return PTR_ERR(regmap);
  263. }
  264. clk_trion_pll_configure(&video_pll0, regmap, video_pll0.config);
  265. /* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
  266. regmap_update_bits(regmap, 0x984, 0x1, 0x1);
  267. ret = qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
  268. if (ret) {
  269. dev_err(&pdev->dev, "Failed to register VIDEO CC clocks\n");
  270. return ret;
  271. }
  272. ret = register_qcom_clks_pm(pdev, false, &video_cc_sm8150_desc);
  273. if (ret)
  274. dev_err(&pdev->dev, "Failed to register for pm ops\n");
  275. dev_info(&pdev->dev, "Registered VIDEO CC clocks\n");
  276. return 0;
  277. }
  278. static void video_cc_sm8150_sync_state(struct device *dev)
  279. {
  280. qcom_cc_sync_state(dev, &video_cc_sm8150_desc);
  281. }
  282. static struct platform_driver video_cc_sm8150_driver = {
  283. .probe = video_cc_sm8150_probe,
  284. .driver = {
  285. .name = "video_cc-sm8150",
  286. .of_match_table = video_cc_sm8150_match_table,
  287. .sync_state = video_cc_sm8150_sync_state,
  288. },
  289. };
  290. static int __init video_cc_sm8150_init(void)
  291. {
  292. return platform_driver_register(&video_cc_sm8150_driver);
  293. }
  294. subsys_initcall(video_cc_sm8150_init);
  295. static void __exit video_cc_sm8150_exit(void)
  296. {
  297. platform_driver_unregister(&video_cc_sm8150_driver);
  298. }
  299. module_exit(video_cc_sm8150_exit);
  300. MODULE_LICENSE("GPL v2");
  301. MODULE_DESCRIPTION("QTI VIDEOCC SM8150 Driver");