videocc-kalama.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/err.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/of.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <dt-bindings/clock/qcom,videocc-kalama.h>
  15. #include "clk-alpha-pll.h"
  16. #include "clk-branch.h"
  17. #include "clk-pll.h"
  18. #include "clk-rcg.h"
  19. #include "clk-regmap.h"
  20. #include "clk-regmap-divider.h"
  21. #include "clk-regmap-mux.h"
  22. #include "common.h"
  23. #include "reset.h"
  24. #include "vdd-level.h"
  25. static DEFINE_VDD_REGULATORS(vdd_mm, VDD_HIGH + 1, 1, vdd_corner);
  26. static DEFINE_VDD_REGULATORS(vdd_mxc, VDD_HIGH + 1, 1, vdd_corner);
  27. static struct clk_vdd_class *video_cc_kalama_regulators[] = {
  28. &vdd_mm,
  29. &vdd_mxc,
  30. };
  31. enum {
  32. P_BI_TCXO,
  33. P_SLEEP_CLK,
  34. P_VIDEO_CC_PLL0_OUT_MAIN,
  35. P_VIDEO_CC_PLL1_OUT_MAIN,
  36. };
  37. static struct pll_vco lucid_ole_vco[] = {
  38. { 249600000, 2000000000, 0 },
  39. };
  40. static const struct alpha_pll_config video_cc_pll0_config = {
  41. .l = 0x1E,
  42. .cal_l = 0x44,
  43. .cal_l_ringosc = 0x44,
  44. .alpha = 0x0,
  45. .config_ctl_val = 0x20485699,
  46. .config_ctl_hi_val = 0x00182261,
  47. .config_ctl_hi1_val = 0x82AA299C,
  48. .test_ctl_val = 0x00000000,
  49. .test_ctl_hi_val = 0x00000003,
  50. .test_ctl_hi1_val = 0x00009000,
  51. .test_ctl_hi2_val = 0x00000034,
  52. .user_ctl_val = 0x00000000,
  53. .user_ctl_hi_val = 0x00000005,
  54. };
  55. static const struct alpha_pll_config video_cc_pll0_config_kalama_v2 = {
  56. .l = 0x25,
  57. .cal_l = 0x44,
  58. .cal_l_ringosc = 0x44,
  59. .alpha = 0x8000,
  60. .config_ctl_val = 0x20485699,
  61. .config_ctl_hi_val = 0x00182261,
  62. .config_ctl_hi1_val = 0x82AA299C,
  63. .test_ctl_val = 0x00000000,
  64. .test_ctl_hi_val = 0x00000003,
  65. .test_ctl_hi1_val = 0x00009000,
  66. .test_ctl_hi2_val = 0x00000034,
  67. .user_ctl_val = 0x00000000,
  68. .user_ctl_hi_val = 0x00000005,
  69. };
  70. static struct clk_alpha_pll video_cc_pll0 = {
  71. .offset = 0x0,
  72. .vco_table = lucid_ole_vco,
  73. .num_vco = ARRAY_SIZE(lucid_ole_vco),
  74. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
  75. .clkr = {
  76. .hw.init = &(struct clk_init_data){
  77. .name = "video_cc_pll0",
  78. .parent_data = &(const struct clk_parent_data){
  79. .fw_name = "bi_tcxo",
  80. },
  81. .num_parents = 1,
  82. .ops = &clk_alpha_pll_lucid_ole_ops,
  83. },
  84. .vdd_data = {
  85. .vdd_class = &vdd_mxc,
  86. .num_rate_max = VDD_NUM,
  87. .rate_max = (unsigned long[VDD_NUM]) {
  88. [VDD_LOWER_D1] = 615000000,
  89. [VDD_LOW] = 1100000000,
  90. [VDD_LOW_L1] = 1600000000,
  91. [VDD_NOMINAL] = 2000000000},
  92. },
  93. },
  94. };
  95. static const struct alpha_pll_config video_cc_pll1_config = {
  96. .l = 0x2B,
  97. .cal_l = 0x44,
  98. .cal_l_ringosc = 0x44,
  99. .alpha = 0xC000,
  100. .config_ctl_val = 0x20485699,
  101. .config_ctl_hi_val = 0x00182261,
  102. .config_ctl_hi1_val = 0x82AA299C,
  103. .test_ctl_val = 0x00000000,
  104. .test_ctl_hi_val = 0x00000003,
  105. .test_ctl_hi1_val = 0x00009000,
  106. .test_ctl_hi2_val = 0x00000034,
  107. .user_ctl_val = 0x00000000,
  108. .user_ctl_hi_val = 0x00000005,
  109. };
  110. static const struct alpha_pll_config video_cc_pll1_config_kalama_v2 = {
  111. .l = 0x36,
  112. .cal_l = 0x44,
  113. .cal_l_ringosc = 0x44,
  114. .alpha = 0xB000,
  115. .config_ctl_val = 0x20485699,
  116. .config_ctl_hi_val = 0x00182261,
  117. .config_ctl_hi1_val = 0x82AA299C,
  118. .test_ctl_val = 0x00000000,
  119. .test_ctl_hi_val = 0x00000003,
  120. .test_ctl_hi1_val = 0x00009000,
  121. .test_ctl_hi2_val = 0x00000034,
  122. .user_ctl_val = 0x00000000,
  123. .user_ctl_hi_val = 0x00000005,
  124. };
  125. static struct clk_alpha_pll video_cc_pll1 = {
  126. .offset = 0x1000,
  127. .vco_table = lucid_ole_vco,
  128. .num_vco = ARRAY_SIZE(lucid_ole_vco),
  129. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
  130. .clkr = {
  131. .hw.init = &(struct clk_init_data){
  132. .name = "video_cc_pll1",
  133. .parent_data = &(const struct clk_parent_data){
  134. .fw_name = "bi_tcxo",
  135. },
  136. .num_parents = 1,
  137. .ops = &clk_alpha_pll_lucid_ole_ops,
  138. },
  139. .vdd_data = {
  140. .vdd_class = &vdd_mxc,
  141. .num_rate_max = VDD_NUM,
  142. .rate_max = (unsigned long[VDD_NUM]) {
  143. [VDD_LOWER_D1] = 615000000,
  144. [VDD_LOW] = 1100000000,
  145. [VDD_LOW_L1] = 1600000000,
  146. [VDD_NOMINAL] = 2000000000},
  147. },
  148. },
  149. };
  150. static const struct parent_map video_cc_parent_map_0[] = {
  151. { P_BI_TCXO, 0 },
  152. };
  153. static const struct clk_parent_data video_cc_parent_data_0_ao[] = {
  154. { .fw_name = "bi_tcxo_ao" },
  155. };
  156. static const struct parent_map video_cc_parent_map_1[] = {
  157. { P_BI_TCXO, 0 },
  158. { P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
  159. };
  160. static const struct clk_parent_data video_cc_parent_data_1[] = {
  161. { .fw_name = "bi_tcxo" },
  162. { .hw = &video_cc_pll0.clkr.hw },
  163. };
  164. static const struct parent_map video_cc_parent_map_2[] = {
  165. { P_BI_TCXO, 0 },
  166. { P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
  167. };
  168. static const struct clk_parent_data video_cc_parent_data_2[] = {
  169. { .fw_name = "bi_tcxo" },
  170. { .hw = &video_cc_pll1.clkr.hw },
  171. };
  172. static const struct parent_map video_cc_parent_map_3[] = {
  173. { P_SLEEP_CLK, 0 },
  174. };
  175. static const struct clk_parent_data video_cc_parent_data_3[] = {
  176. { .fw_name = "sleep_clk" },
  177. };
  178. static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
  179. F(19200000, P_BI_TCXO, 1, 0, 0),
  180. { }
  181. };
  182. static struct clk_rcg2 video_cc_ahb_clk_src = {
  183. .cmd_rcgr = 0x8030,
  184. .mnd_width = 0,
  185. .hid_width = 5,
  186. .parent_map = video_cc_parent_map_0,
  187. .freq_tbl = ftbl_video_cc_ahb_clk_src,
  188. .enable_safe_config = true,
  189. .flags = HW_CLK_CTRL_MODE,
  190. .clkr.hw.init = &(struct clk_init_data){
  191. .name = "video_cc_ahb_clk_src",
  192. .parent_data = video_cc_parent_data_0_ao,
  193. .num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao),
  194. .flags = CLK_SET_RATE_PARENT,
  195. .ops = &clk_rcg2_ops,
  196. },
  197. };
  198. static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
  199. F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
  200. F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
  201. F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
  202. F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
  203. F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
  204. F(1443000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
  205. { }
  206. };
  207. static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_kalama_v2[] = {
  208. F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
  209. F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
  210. F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
  211. F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
  212. F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
  213. { }
  214. };
  215. static struct clk_rcg2 video_cc_mvs0_clk_src = {
  216. .cmd_rcgr = 0x8000,
  217. .mnd_width = 0,
  218. .hid_width = 5,
  219. .parent_map = video_cc_parent_map_1,
  220. .freq_tbl = ftbl_video_cc_mvs0_clk_src,
  221. .enable_safe_config = true,
  222. .flags = HW_CLK_CTRL_MODE,
  223. .clkr.hw.init = &(struct clk_init_data){
  224. .name = "video_cc_mvs0_clk_src",
  225. .parent_data = video_cc_parent_data_1,
  226. .num_parents = ARRAY_SIZE(video_cc_parent_data_1),
  227. .flags = CLK_SET_RATE_PARENT,
  228. .ops = &clk_rcg2_ops,
  229. },
  230. .clkr.vdd_data = {
  231. .vdd_classes = video_cc_kalama_regulators,
  232. .num_vdd_classes = ARRAY_SIZE(video_cc_kalama_regulators),
  233. .num_rate_max = VDD_NUM,
  234. .rate_max = (unsigned long[VDD_NUM]) {
  235. [VDD_LOWER_D1] = 576000000,
  236. [VDD_LOWER] = 720000000,
  237. [VDD_LOW] = 1014000000,
  238. [VDD_LOW_L1] = 1098000000,
  239. [VDD_NOMINAL] = 1332000000,
  240. [VDD_HIGH] = 1443000000},
  241. },
  242. };
  243. static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
  244. F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
  245. F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
  246. F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
  247. F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
  248. F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
  249. { }
  250. };
  251. static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_kalama_v2[] = {
  252. F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
  253. F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
  254. F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
  255. F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
  256. { }
  257. };
  258. static struct clk_rcg2 video_cc_mvs1_clk_src = {
  259. .cmd_rcgr = 0x8018,
  260. .mnd_width = 0,
  261. .hid_width = 5,
  262. .parent_map = video_cc_parent_map_2,
  263. .freq_tbl = ftbl_video_cc_mvs1_clk_src,
  264. .enable_safe_config = true,
  265. .flags = HW_CLK_CTRL_MODE,
  266. .clkr.hw.init = &(struct clk_init_data){
  267. .name = "video_cc_mvs1_clk_src",
  268. .parent_data = video_cc_parent_data_2,
  269. .num_parents = ARRAY_SIZE(video_cc_parent_data_2),
  270. .flags = CLK_SET_RATE_PARENT,
  271. .ops = &clk_rcg2_ops,
  272. },
  273. .clkr.vdd_data = {
  274. .vdd_classes = video_cc_kalama_regulators,
  275. .num_vdd_classes = ARRAY_SIZE(video_cc_kalama_regulators),
  276. .num_rate_max = VDD_NUM,
  277. .rate_max = (unsigned long[VDD_NUM]) {
  278. [VDD_LOWER_D1] = 840000000,
  279. [VDD_LOWER] = 1050000000,
  280. [VDD_LOW] = 1350000000,
  281. [VDD_LOW_L1] = 1500000000,
  282. [VDD_NOMINAL] = 1650000000},
  283. },
  284. };
  285. static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
  286. F(32000, P_SLEEP_CLK, 1, 0, 0),
  287. { }
  288. };
  289. static struct clk_rcg2 video_cc_sleep_clk_src = {
  290. .cmd_rcgr = 0x8128,
  291. .mnd_width = 0,
  292. .hid_width = 5,
  293. .parent_map = video_cc_parent_map_3,
  294. .freq_tbl = ftbl_video_cc_sleep_clk_src,
  295. .clkr.hw.init = &(struct clk_init_data){
  296. .name = "video_cc_sleep_clk_src",
  297. .parent_data = video_cc_parent_data_3,
  298. .num_parents = ARRAY_SIZE(video_cc_parent_data_3),
  299. .flags = CLK_SET_RATE_PARENT,
  300. .ops = &clk_rcg2_ops,
  301. },
  302. .clkr.vdd_data = {
  303. .vdd_class = &vdd_mm,
  304. .num_rate_max = VDD_NUM,
  305. .rate_max = (unsigned long[VDD_NUM]) {
  306. [VDD_LOWER_D1] = 32000},
  307. },
  308. };
  309. static struct clk_rcg2 video_cc_xo_clk_src = {
  310. .cmd_rcgr = 0x810c,
  311. .mnd_width = 0,
  312. .hid_width = 5,
  313. .parent_map = video_cc_parent_map_0,
  314. .freq_tbl = ftbl_video_cc_ahb_clk_src,
  315. .clkr.hw.init = &(struct clk_init_data){
  316. .name = "video_cc_xo_clk_src",
  317. .parent_data = video_cc_parent_data_0_ao,
  318. .num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao),
  319. .flags = CLK_SET_RATE_PARENT,
  320. .ops = &clk_rcg2_ops,
  321. },
  322. };
  323. static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
  324. .reg = 0x80c4,
  325. .shift = 0,
  326. .width = 4,
  327. .clkr.hw.init = &(struct clk_init_data) {
  328. .name = "video_cc_mvs0_div_clk_src",
  329. .parent_hws = (const struct clk_hw*[]){
  330. &video_cc_mvs0_clk_src.clkr.hw,
  331. },
  332. .num_parents = 1,
  333. .flags = CLK_SET_RATE_PARENT,
  334. .ops = &clk_regmap_div_ro_ops,
  335. },
  336. };
  337. static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
  338. .reg = 0x8070,
  339. .shift = 0,
  340. .width = 4,
  341. .clkr.hw.init = &(struct clk_init_data) {
  342. .name = "video_cc_mvs0c_div2_div_clk_src",
  343. .parent_hws = (const struct clk_hw*[]){
  344. &video_cc_mvs0_clk_src.clkr.hw,
  345. },
  346. .num_parents = 1,
  347. .flags = CLK_SET_RATE_PARENT,
  348. .ops = &clk_regmap_div_ro_ops,
  349. },
  350. };
  351. static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
  352. .reg = 0x80ec,
  353. .shift = 0,
  354. .width = 4,
  355. .clkr.hw.init = &(struct clk_init_data) {
  356. .name = "video_cc_mvs1_div_clk_src",
  357. .parent_hws = (const struct clk_hw*[]){
  358. &video_cc_mvs1_clk_src.clkr.hw,
  359. },
  360. .num_parents = 1,
  361. .flags = CLK_SET_RATE_PARENT,
  362. .ops = &clk_regmap_div_ro_ops,
  363. },
  364. };
  365. static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
  366. .reg = 0x809c,
  367. .shift = 0,
  368. .width = 4,
  369. .clkr.hw.init = &(struct clk_init_data) {
  370. .name = "video_cc_mvs1c_div2_div_clk_src",
  371. .parent_hws = (const struct clk_hw*[]){
  372. &video_cc_mvs1_clk_src.clkr.hw,
  373. },
  374. .num_parents = 1,
  375. .flags = CLK_SET_RATE_PARENT,
  376. .ops = &clk_regmap_div_ro_ops,
  377. },
  378. };
  379. static struct clk_branch video_cc_mvs0_clk = {
  380. .halt_reg = 0x80b8,
  381. .halt_check = BRANCH_HALT_VOTED,
  382. .hwcg_reg = 0x80b8,
  383. .hwcg_bit = 1,
  384. .clkr = {
  385. .enable_reg = 0x80b8,
  386. .enable_mask = BIT(0),
  387. .hw.init = &(struct clk_init_data){
  388. .name = "video_cc_mvs0_clk",
  389. .parent_hws = (const struct clk_hw*[]){
  390. &video_cc_mvs0_div_clk_src.clkr.hw,
  391. },
  392. .num_parents = 1,
  393. .flags = CLK_SET_RATE_PARENT,
  394. .ops = &clk_branch2_ops,
  395. },
  396. },
  397. };
  398. static struct clk_branch video_cc_mvs0c_clk = {
  399. .halt_reg = 0x8064,
  400. .halt_check = BRANCH_HALT,
  401. .clkr = {
  402. .enable_reg = 0x8064,
  403. .enable_mask = BIT(0),
  404. .hw.init = &(struct clk_init_data){
  405. .name = "video_cc_mvs0c_clk",
  406. .parent_hws = (const struct clk_hw*[]){
  407. &video_cc_mvs0c_div2_div_clk_src.clkr.hw,
  408. },
  409. .num_parents = 1,
  410. .flags = CLK_SET_RATE_PARENT,
  411. .ops = &clk_branch2_ops,
  412. },
  413. },
  414. };
  415. static struct clk_branch video_cc_mvs1_clk = {
  416. .halt_reg = 0x80e0,
  417. .halt_check = BRANCH_HALT_VOTED,
  418. .hwcg_reg = 0x80e0,
  419. .hwcg_bit = 1,
  420. .clkr = {
  421. .enable_reg = 0x80e0,
  422. .enable_mask = BIT(0),
  423. .hw.init = &(struct clk_init_data){
  424. .name = "video_cc_mvs1_clk",
  425. .parent_hws = (const struct clk_hw*[]){
  426. &video_cc_mvs1_div_clk_src.clkr.hw,
  427. },
  428. .num_parents = 1,
  429. .flags = CLK_SET_RATE_PARENT,
  430. .ops = &clk_branch2_ops,
  431. },
  432. },
  433. };
  434. static struct clk_branch video_cc_mvs1c_clk = {
  435. .halt_reg = 0x8090,
  436. .halt_check = BRANCH_HALT,
  437. .clkr = {
  438. .enable_reg = 0x8090,
  439. .enable_mask = BIT(0),
  440. .hw.init = &(struct clk_init_data){
  441. .name = "video_cc_mvs1c_clk",
  442. .parent_hws = (const struct clk_hw*[]){
  443. &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
  444. },
  445. .num_parents = 1,
  446. .flags = CLK_SET_RATE_PARENT,
  447. .ops = &clk_branch2_ops,
  448. },
  449. },
  450. };
  451. static struct clk_branch video_cc_sleep_clk = {
  452. .halt_reg = 0x8140,
  453. .halt_check = BRANCH_HALT,
  454. .clkr = {
  455. .enable_reg = 0x8140,
  456. .enable_mask = BIT(0),
  457. .hw.init = &(struct clk_init_data){
  458. .name = "video_cc_sleep_clk",
  459. .parent_hws = (const struct clk_hw*[]){
  460. &video_cc_sleep_clk_src.clkr.hw,
  461. },
  462. .num_parents = 1,
  463. .flags = CLK_SET_RATE_PARENT,
  464. .ops = &clk_branch2_ops,
  465. },
  466. },
  467. };
  468. static struct clk_regmap *video_cc_kalama_clocks[] = {
  469. [VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
  470. [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
  471. [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
  472. [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
  473. [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
  474. [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
  475. [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
  476. [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
  477. [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
  478. [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
  479. [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
  480. [VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
  481. [VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
  482. [VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
  483. [VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
  484. [VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
  485. };
  486. static const struct qcom_reset_map video_cc_kalama_resets[] = {
  487. [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },
  488. [CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 },
  489. [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
  490. [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
  491. [CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
  492. [VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
  493. [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
  494. };
  495. static const struct regmap_config video_cc_kalama_regmap_config = {
  496. .reg_bits = 32,
  497. .reg_stride = 4,
  498. .val_bits = 32,
  499. .max_register = 0x9f4c,
  500. .fast_io = true,
  501. };
  502. static struct qcom_cc_desc video_cc_kalama_desc = {
  503. .config = &video_cc_kalama_regmap_config,
  504. .clks = video_cc_kalama_clocks,
  505. .num_clks = ARRAY_SIZE(video_cc_kalama_clocks),
  506. .resets = video_cc_kalama_resets,
  507. .num_resets = ARRAY_SIZE(video_cc_kalama_resets),
  508. .clk_regulators = video_cc_kalama_regulators,
  509. .num_clk_regulators = ARRAY_SIZE(video_cc_kalama_regulators),
  510. };
  511. static const struct of_device_id video_cc_kalama_match_table[] = {
  512. { .compatible = "qcom,kalama-videocc" },
  513. { .compatible = "qcom,kalama-videocc-v2" },
  514. { }
  515. };
  516. MODULE_DEVICE_TABLE(of, video_cc_kalama_match_table);
  517. static void video_cc_kalama_fixup_kalamav2(struct regmap *regmap)
  518. {
  519. clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config_kalama_v2);
  520. clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config_kalama_v2);
  521. video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_kalama_v2;
  522. video_cc_mvs0_clk_src.clkr.vdd_data.rate_max[VDD_LOWER_D1] = 0;
  523. video_cc_mvs0_clk_src.clkr.vdd_data.rate_max[VDD_HIGH] = 1600000000;
  524. video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_kalama_v2;
  525. video_cc_mvs1_clk_src.clkr.vdd_data.rate_max[VDD_LOWER_D1] = 0;
  526. video_cc_sleep_clk_src.clkr.vdd_data.rate_max[VDD_LOWER_D1] = 0;
  527. video_cc_sleep_clk_src.clkr.vdd_data.rate_max[VDD_LOWER] = 32000;
  528. }
  529. static int video_cc_kalama_fixup(struct platform_device *pdev, struct regmap *regmap)
  530. {
  531. const char *compat = NULL;
  532. int compatlen = 0;
  533. compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);
  534. if (!compat || compatlen <= 0)
  535. return -EINVAL;
  536. if (!strcmp(compat, "qcom,kalama-videocc-v2"))
  537. video_cc_kalama_fixup_kalamav2(regmap);
  538. return 0;
  539. }
  540. static int video_cc_kalama_probe(struct platform_device *pdev)
  541. {
  542. struct regmap *regmap;
  543. int ret;
  544. regmap = qcom_cc_map(pdev, &video_cc_kalama_desc);
  545. if (IS_ERR(regmap))
  546. return PTR_ERR(regmap);
  547. ret = qcom_cc_runtime_init(pdev, &video_cc_kalama_desc);
  548. if (ret)
  549. return ret;
  550. ret = pm_runtime_get_sync(&pdev->dev);
  551. if (ret)
  552. return ret;
  553. clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
  554. clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
  555. ret = video_cc_kalama_fixup(pdev, regmap);
  556. if (ret)
  557. return ret;
  558. /*
  559. * Keep clocks always enabled:
  560. * video_cc_ahb_clk
  561. * video_cc_xo_clk
  562. */
  563. regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0));
  564. regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0));
  565. ret = qcom_cc_really_probe(pdev, &video_cc_kalama_desc, regmap);
  566. if (ret) {
  567. dev_err(&pdev->dev, "Failed to register VIDEO CC clocks\n");
  568. return ret;
  569. }
  570. pm_runtime_put_sync(&pdev->dev);
  571. dev_info(&pdev->dev, "Registered VIDEO CC clocks\n");
  572. return ret;
  573. }
  574. static void video_cc_kalama_sync_state(struct device *dev)
  575. {
  576. qcom_cc_sync_state(dev, &video_cc_kalama_desc);
  577. }
  578. static const struct dev_pm_ops video_cc_kalama_pm_ops = {
  579. SET_RUNTIME_PM_OPS(qcom_cc_runtime_suspend, qcom_cc_runtime_resume, NULL)
  580. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  581. pm_runtime_force_resume)
  582. };
  583. static struct platform_driver video_cc_kalama_driver = {
  584. .probe = video_cc_kalama_probe,
  585. .driver = {
  586. .name = "video_cc-kalama",
  587. .of_match_table = video_cc_kalama_match_table,
  588. .sync_state = video_cc_kalama_sync_state,
  589. .pm = &video_cc_kalama_pm_ops,
  590. },
  591. };
  592. static int __init video_cc_kalama_init(void)
  593. {
  594. return platform_driver_register(&video_cc_kalama_driver);
  595. }
  596. subsys_initcall(video_cc_kalama_init);
  597. static void __exit video_cc_kalama_exit(void)
  598. {
  599. platform_driver_unregister(&video_cc_kalama_driver);
  600. }
  601. module_exit(video_cc_kalama_exit);
  602. MODULE_DESCRIPTION("QTI VIDEO_CC KALAMA Driver");
  603. MODULE_LICENSE("GPL");