lcc-msm8960.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/bitops.h>
  7. #include <linux/err.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/regmap.h>
  14. #include <dt-bindings/clock/qcom,lcc-msm8960.h>
  15. #include "common.h"
  16. #include "clk-regmap.h"
  17. #include "clk-pll.h"
  18. #include "clk-rcg.h"
  19. #include "clk-branch.h"
  20. #include "clk-regmap-divider.h"
  21. #include "clk-regmap-mux.h"
  22. static struct clk_pll pll4 = {
  23. .l_reg = 0x4,
  24. .m_reg = 0x8,
  25. .n_reg = 0xc,
  26. .config_reg = 0x14,
  27. .mode_reg = 0x0,
  28. .status_reg = 0x18,
  29. .status_bit = 16,
  30. .clkr.hw.init = &(struct clk_init_data){
  31. .name = "pll4",
  32. .parent_data = (const struct clk_parent_data[]){
  33. { .fw_name = "pxo", .name = "pxo_board" },
  34. },
  35. .num_parents = 1,
  36. .ops = &clk_pll_ops,
  37. },
  38. };
  39. enum {
  40. P_PXO,
  41. P_PLL4,
  42. };
  43. static const struct parent_map lcc_pxo_pll4_map[] = {
  44. { P_PXO, 0 },
  45. { P_PLL4, 2 }
  46. };
  47. static const struct clk_parent_data lcc_pxo_pll4[] = {
  48. { .fw_name = "pxo", .name = "pxo_board" },
  49. { .fw_name = "pll4_vote", .name = "pll4_vote" },
  50. };
  51. static struct freq_tbl clk_tbl_aif_osr_492[] = {
  52. { 512000, P_PLL4, 4, 1, 240 },
  53. { 768000, P_PLL4, 4, 1, 160 },
  54. { 1024000, P_PLL4, 4, 1, 120 },
  55. { 1536000, P_PLL4, 4, 1, 80 },
  56. { 2048000, P_PLL4, 4, 1, 60 },
  57. { 3072000, P_PLL4, 4, 1, 40 },
  58. { 4096000, P_PLL4, 4, 1, 30 },
  59. { 6144000, P_PLL4, 4, 1, 20 },
  60. { 8192000, P_PLL4, 4, 1, 15 },
  61. { 12288000, P_PLL4, 4, 1, 10 },
  62. { 24576000, P_PLL4, 4, 1, 5 },
  63. { 27000000, P_PXO, 1, 0, 0 },
  64. { }
  65. };
  66. static struct freq_tbl clk_tbl_aif_osr_393[] = {
  67. { 512000, P_PLL4, 4, 1, 192 },
  68. { 768000, P_PLL4, 4, 1, 128 },
  69. { 1024000, P_PLL4, 4, 1, 96 },
  70. { 1536000, P_PLL4, 4, 1, 64 },
  71. { 2048000, P_PLL4, 4, 1, 48 },
  72. { 3072000, P_PLL4, 4, 1, 32 },
  73. { 4096000, P_PLL4, 4, 1, 24 },
  74. { 6144000, P_PLL4, 4, 1, 16 },
  75. { 8192000, P_PLL4, 4, 1, 12 },
  76. { 12288000, P_PLL4, 4, 1, 8 },
  77. { 24576000, P_PLL4, 4, 1, 4 },
  78. { 27000000, P_PXO, 1, 0, 0 },
  79. { }
  80. };
  81. #define CLK_AIF_OSR_SRC(prefix, _ns, _md) \
  82. static struct clk_rcg prefix##_osr_src = { \
  83. .ns_reg = _ns, \
  84. .md_reg = _md, \
  85. .mn = { \
  86. .mnctr_en_bit = 8, \
  87. .mnctr_reset_bit = 7, \
  88. .mnctr_mode_shift = 5, \
  89. .n_val_shift = 24, \
  90. .m_val_shift = 8, \
  91. .width = 8, \
  92. }, \
  93. .p = { \
  94. .pre_div_shift = 3, \
  95. .pre_div_width = 2, \
  96. }, \
  97. .s = { \
  98. .src_sel_shift = 0, \
  99. .parent_map = lcc_pxo_pll4_map, \
  100. }, \
  101. .freq_tbl = clk_tbl_aif_osr_393, \
  102. .clkr = { \
  103. .enable_reg = _ns, \
  104. .enable_mask = BIT(9), \
  105. .hw.init = &(struct clk_init_data){ \
  106. .name = #prefix "_osr_src", \
  107. .parent_data = lcc_pxo_pll4, \
  108. .num_parents = ARRAY_SIZE(lcc_pxo_pll4), \
  109. .ops = &clk_rcg_ops, \
  110. .flags = CLK_SET_RATE_GATE, \
  111. }, \
  112. }, \
  113. }; \
  114. #define CLK_AIF_OSR_CLK(prefix, _ns, hr, en_bit) \
  115. static struct clk_branch prefix##_osr_clk = { \
  116. .halt_reg = hr, \
  117. .halt_bit = 1, \
  118. .halt_check = BRANCH_HALT_ENABLE, \
  119. .clkr = { \
  120. .enable_reg = _ns, \
  121. .enable_mask = BIT(en_bit), \
  122. .hw.init = &(struct clk_init_data){ \
  123. .name = #prefix "_osr_clk", \
  124. .parent_hws = (const struct clk_hw*[]){ \
  125. &prefix##_osr_src.clkr.hw, \
  126. }, \
  127. .num_parents = 1, \
  128. .ops = &clk_branch_ops, \
  129. .flags = CLK_SET_RATE_PARENT, \
  130. }, \
  131. }, \
  132. }; \
  133. #define CLK_AIF_OSR_DIV_CLK(prefix, _ns, _width) \
  134. static struct clk_regmap_div prefix##_div_clk = { \
  135. .reg = _ns, \
  136. .shift = 10, \
  137. .width = _width, \
  138. .clkr = { \
  139. .hw.init = &(struct clk_init_data){ \
  140. .name = #prefix "_div_clk", \
  141. .parent_hws = (const struct clk_hw*[]){ \
  142. &prefix##_osr_src.clkr.hw, \
  143. }, \
  144. .num_parents = 1, \
  145. .ops = &clk_regmap_div_ops, \
  146. }, \
  147. }, \
  148. }; \
  149. #define CLK_AIF_OSR_BIT_DIV_CLK(prefix, _ns, hr, en_bit) \
  150. static struct clk_branch prefix##_bit_div_clk = { \
  151. .halt_reg = hr, \
  152. .halt_bit = 0, \
  153. .halt_check = BRANCH_HALT_ENABLE, \
  154. .clkr = { \
  155. .enable_reg = _ns, \
  156. .enable_mask = BIT(en_bit), \
  157. .hw.init = &(struct clk_init_data){ \
  158. .name = #prefix "_bit_div_clk", \
  159. .parent_hws = (const struct clk_hw*[]){ \
  160. &prefix##_div_clk.clkr.hw, \
  161. }, \
  162. .num_parents = 1, \
  163. .ops = &clk_branch_ops, \
  164. .flags = CLK_SET_RATE_PARENT, \
  165. }, \
  166. }, \
  167. }; \
  168. #define CLK_AIF_OSR_BIT_CLK(prefix, _ns, _shift) \
  169. static struct clk_regmap_mux prefix##_bit_clk = { \
  170. .reg = _ns, \
  171. .shift = _shift, \
  172. .width = 1, \
  173. .clkr = { \
  174. .hw.init = &(struct clk_init_data){ \
  175. .name = #prefix "_bit_clk", \
  176. .parent_data = (const struct clk_parent_data[]){ \
  177. { .hw = &prefix##_bit_div_clk.clkr.hw, }, \
  178. { .fw_name = #prefix "_codec_clk", \
  179. .name = #prefix "_codec_clk", }, \
  180. }, \
  181. .num_parents = 2, \
  182. .ops = &clk_regmap_mux_closest_ops, \
  183. .flags = CLK_SET_RATE_PARENT, \
  184. }, \
  185. }, \
  186. };
  187. CLK_AIF_OSR_SRC(mi2s, 0x48, 0x4c)
  188. CLK_AIF_OSR_CLK(mi2s, 0x48, 0x50, 17)
  189. CLK_AIF_OSR_DIV_CLK(mi2s, 0x48, 4)
  190. CLK_AIF_OSR_BIT_DIV_CLK(mi2s, 0x48, 0x50, 15)
  191. CLK_AIF_OSR_BIT_CLK(mi2s, 0x48, 14)
  192. #define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
  193. CLK_AIF_OSR_SRC(prefix, _ns, _md) \
  194. CLK_AIF_OSR_CLK(prefix, _ns, hr, 21) \
  195. CLK_AIF_OSR_DIV_CLK(prefix, _ns, 8) \
  196. CLK_AIF_OSR_BIT_DIV_CLK(prefix, _ns, hr, 19) \
  197. CLK_AIF_OSR_BIT_CLK(prefix, _ns, 18)
  198. CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
  199. CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
  200. CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
  201. CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
  202. static struct freq_tbl clk_tbl_pcm_492[] = {
  203. { 256000, P_PLL4, 4, 1, 480 },
  204. { 512000, P_PLL4, 4, 1, 240 },
  205. { 768000, P_PLL4, 4, 1, 160 },
  206. { 1024000, P_PLL4, 4, 1, 120 },
  207. { 1536000, P_PLL4, 4, 1, 80 },
  208. { 2048000, P_PLL4, 4, 1, 60 },
  209. { 3072000, P_PLL4, 4, 1, 40 },
  210. { 4096000, P_PLL4, 4, 1, 30 },
  211. { 6144000, P_PLL4, 4, 1, 20 },
  212. { 8192000, P_PLL4, 4, 1, 15 },
  213. { 12288000, P_PLL4, 4, 1, 10 },
  214. { 24576000, P_PLL4, 4, 1, 5 },
  215. { 27000000, P_PXO, 1, 0, 0 },
  216. { }
  217. };
  218. static struct freq_tbl clk_tbl_pcm_393[] = {
  219. { 256000, P_PLL4, 4, 1, 384 },
  220. { 512000, P_PLL4, 4, 1, 192 },
  221. { 768000, P_PLL4, 4, 1, 128 },
  222. { 1024000, P_PLL4, 4, 1, 96 },
  223. { 1536000, P_PLL4, 4, 1, 64 },
  224. { 2048000, P_PLL4, 4, 1, 48 },
  225. { 3072000, P_PLL4, 4, 1, 32 },
  226. { 4096000, P_PLL4, 4, 1, 24 },
  227. { 6144000, P_PLL4, 4, 1, 16 },
  228. { 8192000, P_PLL4, 4, 1, 12 },
  229. { 12288000, P_PLL4, 4, 1, 8 },
  230. { 24576000, P_PLL4, 4, 1, 4 },
  231. { 27000000, P_PXO, 1, 0, 0 },
  232. { }
  233. };
  234. static struct clk_rcg pcm_src = {
  235. .ns_reg = 0x54,
  236. .md_reg = 0x58,
  237. .mn = {
  238. .mnctr_en_bit = 8,
  239. .mnctr_reset_bit = 7,
  240. .mnctr_mode_shift = 5,
  241. .n_val_shift = 16,
  242. .m_val_shift = 16,
  243. .width = 16,
  244. },
  245. .p = {
  246. .pre_div_shift = 3,
  247. .pre_div_width = 2,
  248. },
  249. .s = {
  250. .src_sel_shift = 0,
  251. .parent_map = lcc_pxo_pll4_map,
  252. },
  253. .freq_tbl = clk_tbl_pcm_393,
  254. .clkr = {
  255. .enable_reg = 0x54,
  256. .enable_mask = BIT(9),
  257. .hw.init = &(struct clk_init_data){
  258. .name = "pcm_src",
  259. .parent_data = lcc_pxo_pll4,
  260. .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
  261. .ops = &clk_rcg_ops,
  262. .flags = CLK_SET_RATE_GATE,
  263. },
  264. },
  265. };
  266. static struct clk_branch pcm_clk_out = {
  267. .halt_reg = 0x5c,
  268. .halt_bit = 0,
  269. .halt_check = BRANCH_HALT_ENABLE,
  270. .clkr = {
  271. .enable_reg = 0x54,
  272. .enable_mask = BIT(11),
  273. .hw.init = &(struct clk_init_data){
  274. .name = "pcm_clk_out",
  275. .parent_hws = (const struct clk_hw*[]){
  276. &pcm_src.clkr.hw
  277. },
  278. .num_parents = 1,
  279. .ops = &clk_branch_ops,
  280. .flags = CLK_SET_RATE_PARENT,
  281. },
  282. },
  283. };
  284. static struct clk_regmap_mux pcm_clk = {
  285. .reg = 0x54,
  286. .shift = 10,
  287. .width = 1,
  288. .clkr = {
  289. .hw.init = &(struct clk_init_data){
  290. .name = "pcm_clk",
  291. .parent_data = (const struct clk_parent_data[]){
  292. { .hw = &pcm_clk_out.clkr.hw },
  293. { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
  294. },
  295. .num_parents = 2,
  296. .ops = &clk_regmap_mux_closest_ops,
  297. .flags = CLK_SET_RATE_PARENT,
  298. },
  299. },
  300. };
  301. static struct clk_rcg slimbus_src = {
  302. .ns_reg = 0xcc,
  303. .md_reg = 0xd0,
  304. .mn = {
  305. .mnctr_en_bit = 8,
  306. .mnctr_reset_bit = 7,
  307. .mnctr_mode_shift = 5,
  308. .n_val_shift = 24,
  309. .m_val_shift = 8,
  310. .width = 8,
  311. },
  312. .p = {
  313. .pre_div_shift = 3,
  314. .pre_div_width = 2,
  315. },
  316. .s = {
  317. .src_sel_shift = 0,
  318. .parent_map = lcc_pxo_pll4_map,
  319. },
  320. .freq_tbl = clk_tbl_aif_osr_393,
  321. .clkr = {
  322. .enable_reg = 0xcc,
  323. .enable_mask = BIT(9),
  324. .hw.init = &(struct clk_init_data){
  325. .name = "slimbus_src",
  326. .parent_data = lcc_pxo_pll4,
  327. .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
  328. .ops = &clk_rcg_ops,
  329. .flags = CLK_SET_RATE_GATE,
  330. },
  331. },
  332. };
  333. static struct clk_branch audio_slimbus_clk = {
  334. .halt_reg = 0xd4,
  335. .halt_bit = 0,
  336. .halt_check = BRANCH_HALT_ENABLE,
  337. .clkr = {
  338. .enable_reg = 0xcc,
  339. .enable_mask = BIT(10),
  340. .hw.init = &(struct clk_init_data){
  341. .name = "audio_slimbus_clk",
  342. .parent_hws = (const struct clk_hw*[]){
  343. &slimbus_src.clkr.hw,
  344. },
  345. .num_parents = 1,
  346. .ops = &clk_branch_ops,
  347. .flags = CLK_SET_RATE_PARENT,
  348. },
  349. },
  350. };
  351. static struct clk_branch sps_slimbus_clk = {
  352. .halt_reg = 0xd4,
  353. .halt_bit = 1,
  354. .halt_check = BRANCH_HALT_ENABLE,
  355. .clkr = {
  356. .enable_reg = 0xcc,
  357. .enable_mask = BIT(12),
  358. .hw.init = &(struct clk_init_data){
  359. .name = "sps_slimbus_clk",
  360. .parent_hws = (const struct clk_hw*[]){
  361. &slimbus_src.clkr.hw,
  362. },
  363. .num_parents = 1,
  364. .ops = &clk_branch_ops,
  365. .flags = CLK_SET_RATE_PARENT,
  366. },
  367. },
  368. };
  369. static struct clk_regmap *lcc_msm8960_clks[] = {
  370. [PLL4] = &pll4.clkr,
  371. [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
  372. [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
  373. [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
  374. [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
  375. [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
  376. [PCM_SRC] = &pcm_src.clkr,
  377. [PCM_CLK_OUT] = &pcm_clk_out.clkr,
  378. [PCM_CLK] = &pcm_clk.clkr,
  379. [SLIMBUS_SRC] = &slimbus_src.clkr,
  380. [AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
  381. [SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
  382. [CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
  383. [CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
  384. [CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
  385. [CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
  386. [CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
  387. [SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
  388. [SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
  389. [SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
  390. [SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
  391. [SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
  392. [CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
  393. [CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
  394. [CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
  395. [CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
  396. [CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
  397. [SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
  398. [SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
  399. [SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
  400. [SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
  401. [SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,
  402. };
  403. static const struct regmap_config lcc_msm8960_regmap_config = {
  404. .reg_bits = 32,
  405. .reg_stride = 4,
  406. .val_bits = 32,
  407. .max_register = 0xfc,
  408. .fast_io = true,
  409. };
  410. static const struct qcom_cc_desc lcc_msm8960_desc = {
  411. .config = &lcc_msm8960_regmap_config,
  412. .clks = lcc_msm8960_clks,
  413. .num_clks = ARRAY_SIZE(lcc_msm8960_clks),
  414. };
  415. static const struct of_device_id lcc_msm8960_match_table[] = {
  416. { .compatible = "qcom,lcc-msm8960" },
  417. { .compatible = "qcom,lcc-apq8064" },
  418. { }
  419. };
  420. MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table);
  421. static int lcc_msm8960_probe(struct platform_device *pdev)
  422. {
  423. u32 val;
  424. struct regmap *regmap;
  425. regmap = qcom_cc_map(pdev, &lcc_msm8960_desc);
  426. if (IS_ERR(regmap))
  427. return PTR_ERR(regmap);
  428. /* Use the correct frequency plan depending on speed of PLL4 */
  429. regmap_read(regmap, 0x4, &val);
  430. if (val == 0x12) {
  431. slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
  432. mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
  433. codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
  434. spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
  435. codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
  436. spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
  437. pcm_src.freq_tbl = clk_tbl_pcm_492;
  438. }
  439. /* Enable PLL4 source on the LPASS Primary PLL Mux */
  440. regmap_write(regmap, 0xc4, 0x1);
  441. return qcom_cc_really_probe(pdev, &lcc_msm8960_desc, regmap);
  442. }
  443. static struct platform_driver lcc_msm8960_driver = {
  444. .probe = lcc_msm8960_probe,
  445. .driver = {
  446. .name = "lcc-msm8960",
  447. .of_match_table = lcc_msm8960_match_table,
  448. },
  449. };
  450. module_platform_driver(lcc_msm8960_driver);
  451. MODULE_DESCRIPTION("QCOM LCC MSM8960 Driver");
  452. MODULE_LICENSE("GPL v2");
  453. MODULE_ALIAS("platform:lcc-msm8960");