lcc-ipq806x.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/bitops.h>
  7. #include <linux/err.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/regmap.h>
  14. #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
  15. #include "common.h"
  16. #include "clk-regmap.h"
  17. #include "clk-pll.h"
  18. #include "clk-rcg.h"
  19. #include "clk-branch.h"
  20. #include "clk-regmap-divider.h"
  21. #include "clk-regmap-mux.h"
  22. #include "reset.h"
  23. static struct clk_pll pll4 = {
  24. .l_reg = 0x4,
  25. .m_reg = 0x8,
  26. .n_reg = 0xc,
  27. .config_reg = 0x14,
  28. .mode_reg = 0x0,
  29. .status_reg = 0x18,
  30. .status_bit = 16,
  31. .clkr.hw.init = &(struct clk_init_data){
  32. .name = "pll4",
  33. .parent_data = &(const struct clk_parent_data) {
  34. .fw_name = "pxo", .name = "pxo_board",
  35. },
  36. .num_parents = 1,
  37. .ops = &clk_pll_ops,
  38. },
  39. };
  40. static const struct pll_config pll4_config = {
  41. .l = 0xf,
  42. .m = 0x91,
  43. .n = 0xc7,
  44. .vco_val = 0x0,
  45. .vco_mask = BIT(17) | BIT(16),
  46. .pre_div_val = 0x0,
  47. .pre_div_mask = BIT(19),
  48. .post_div_val = 0x0,
  49. .post_div_mask = BIT(21) | BIT(20),
  50. .mn_ena_mask = BIT(22),
  51. .main_output_mask = BIT(23),
  52. };
  53. enum {
  54. P_PXO,
  55. P_PLL4,
  56. };
  57. static const struct parent_map lcc_pxo_pll4_map[] = {
  58. { P_PXO, 0 },
  59. { P_PLL4, 2 }
  60. };
  61. static const struct clk_parent_data lcc_pxo_pll4[] = {
  62. { .fw_name = "pxo", .name = "pxo_board" },
  63. { .fw_name = "pll4_vote", .name = "pll4_vote" },
  64. };
  65. static struct freq_tbl clk_tbl_aif_mi2s[] = {
  66. { 1024000, P_PLL4, 4, 1, 96 },
  67. { 1411200, P_PLL4, 4, 2, 139 },
  68. { 1536000, P_PLL4, 4, 1, 64 },
  69. { 2048000, P_PLL4, 4, 1, 48 },
  70. { 2116800, P_PLL4, 4, 2, 93 },
  71. { 2304000, P_PLL4, 4, 2, 85 },
  72. { 2822400, P_PLL4, 4, 6, 209 },
  73. { 3072000, P_PLL4, 4, 1, 32 },
  74. { 3175200, P_PLL4, 4, 1, 31 },
  75. { 4096000, P_PLL4, 4, 1, 24 },
  76. { 4233600, P_PLL4, 4, 9, 209 },
  77. { 4608000, P_PLL4, 4, 3, 64 },
  78. { 5644800, P_PLL4, 4, 12, 209 },
  79. { 6144000, P_PLL4, 4, 1, 16 },
  80. { 6350400, P_PLL4, 4, 2, 31 },
  81. { 8192000, P_PLL4, 4, 1, 12 },
  82. { 8467200, P_PLL4, 4, 18, 209 },
  83. { 9216000, P_PLL4, 4, 3, 32 },
  84. { 11289600, P_PLL4, 4, 24, 209 },
  85. { 12288000, P_PLL4, 4, 1, 8 },
  86. { 12700800, P_PLL4, 4, 27, 209 },
  87. { 13824000, P_PLL4, 4, 9, 64 },
  88. { 16384000, P_PLL4, 4, 1, 6 },
  89. { 16934400, P_PLL4, 4, 41, 238 },
  90. { 18432000, P_PLL4, 4, 3, 16 },
  91. { 22579200, P_PLL4, 2, 24, 209 },
  92. { 24576000, P_PLL4, 4, 1, 4 },
  93. { 27648000, P_PLL4, 4, 9, 32 },
  94. { 33868800, P_PLL4, 4, 41, 119 },
  95. { 36864000, P_PLL4, 4, 3, 8 },
  96. { 45158400, P_PLL4, 1, 24, 209 },
  97. { 49152000, P_PLL4, 4, 1, 2 },
  98. { 50803200, P_PLL4, 1, 27, 209 },
  99. { }
  100. };
  101. static struct clk_rcg mi2s_osr_src = {
  102. .ns_reg = 0x48,
  103. .md_reg = 0x4c,
  104. .mn = {
  105. .mnctr_en_bit = 8,
  106. .mnctr_reset_bit = 7,
  107. .mnctr_mode_shift = 5,
  108. .n_val_shift = 24,
  109. .m_val_shift = 8,
  110. .width = 8,
  111. },
  112. .p = {
  113. .pre_div_shift = 3,
  114. .pre_div_width = 2,
  115. },
  116. .s = {
  117. .src_sel_shift = 0,
  118. .parent_map = lcc_pxo_pll4_map,
  119. },
  120. .freq_tbl = clk_tbl_aif_mi2s,
  121. .clkr = {
  122. .enable_reg = 0x48,
  123. .enable_mask = BIT(9),
  124. .hw.init = &(struct clk_init_data){
  125. .name = "mi2s_osr_src",
  126. .parent_data = lcc_pxo_pll4,
  127. .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
  128. .ops = &clk_rcg_ops,
  129. .flags = CLK_SET_RATE_GATE,
  130. },
  131. },
  132. };
  133. static struct clk_branch mi2s_osr_clk = {
  134. .halt_reg = 0x50,
  135. .halt_bit = 1,
  136. .halt_check = BRANCH_HALT_ENABLE,
  137. .clkr = {
  138. .enable_reg = 0x48,
  139. .enable_mask = BIT(17),
  140. .hw.init = &(struct clk_init_data){
  141. .name = "mi2s_osr_clk",
  142. .parent_hws = (const struct clk_hw*[]) {
  143. &mi2s_osr_src.clkr.hw,
  144. },
  145. .num_parents = 1,
  146. .ops = &clk_branch_ops,
  147. .flags = CLK_SET_RATE_PARENT,
  148. },
  149. },
  150. };
  151. static struct clk_regmap_div mi2s_div_clk = {
  152. .reg = 0x48,
  153. .shift = 10,
  154. .width = 4,
  155. .clkr = {
  156. .hw.init = &(struct clk_init_data){
  157. .name = "mi2s_div_clk",
  158. .parent_hws = (const struct clk_hw*[]) {
  159. &mi2s_osr_src.clkr.hw,
  160. },
  161. .num_parents = 1,
  162. .ops = &clk_regmap_div_ops,
  163. },
  164. },
  165. };
  166. static struct clk_branch mi2s_bit_div_clk = {
  167. .halt_reg = 0x50,
  168. .halt_bit = 0,
  169. .halt_check = BRANCH_HALT_ENABLE,
  170. .clkr = {
  171. .enable_reg = 0x48,
  172. .enable_mask = BIT(15),
  173. .hw.init = &(struct clk_init_data){
  174. .name = "mi2s_bit_div_clk",
  175. .parent_hws = (const struct clk_hw*[]) {
  176. &mi2s_div_clk.clkr.hw,
  177. },
  178. .num_parents = 1,
  179. .ops = &clk_branch_ops,
  180. .flags = CLK_SET_RATE_PARENT,
  181. },
  182. },
  183. };
  184. static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = {
  185. { .hw = &mi2s_bit_div_clk.clkr.hw, },
  186. { .fw_name = "mi2s_codec", .name = "mi2s_codec_clk" },
  187. };
  188. static struct clk_regmap_mux mi2s_bit_clk = {
  189. .reg = 0x48,
  190. .shift = 14,
  191. .width = 1,
  192. .clkr = {
  193. .hw.init = &(struct clk_init_data){
  194. .name = "mi2s_bit_clk",
  195. .parent_data = lcc_mi2s_bit_div_codec_clk,
  196. .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk),
  197. .ops = &clk_regmap_mux_closest_ops,
  198. .flags = CLK_SET_RATE_PARENT,
  199. },
  200. },
  201. };
  202. static struct freq_tbl clk_tbl_pcm[] = {
  203. { 64000, P_PLL4, 4, 1, 1536 },
  204. { 128000, P_PLL4, 4, 1, 768 },
  205. { 256000, P_PLL4, 4, 1, 384 },
  206. { 512000, P_PLL4, 4, 1, 192 },
  207. { 1024000, P_PLL4, 4, 1, 96 },
  208. { 2048000, P_PLL4, 4, 1, 48 },
  209. { },
  210. };
  211. static struct clk_rcg pcm_src = {
  212. .ns_reg = 0x54,
  213. .md_reg = 0x58,
  214. .mn = {
  215. .mnctr_en_bit = 8,
  216. .mnctr_reset_bit = 7,
  217. .mnctr_mode_shift = 5,
  218. .n_val_shift = 16,
  219. .m_val_shift = 16,
  220. .width = 16,
  221. },
  222. .p = {
  223. .pre_div_shift = 3,
  224. .pre_div_width = 2,
  225. },
  226. .s = {
  227. .src_sel_shift = 0,
  228. .parent_map = lcc_pxo_pll4_map,
  229. },
  230. .freq_tbl = clk_tbl_pcm,
  231. .clkr = {
  232. .enable_reg = 0x54,
  233. .enable_mask = BIT(9),
  234. .hw.init = &(struct clk_init_data){
  235. .name = "pcm_src",
  236. .parent_data = lcc_pxo_pll4,
  237. .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
  238. .ops = &clk_rcg_ops,
  239. .flags = CLK_SET_RATE_GATE,
  240. },
  241. },
  242. };
  243. static struct clk_branch pcm_clk_out = {
  244. .halt_reg = 0x5c,
  245. .halt_bit = 0,
  246. .halt_check = BRANCH_HALT_ENABLE,
  247. .clkr = {
  248. .enable_reg = 0x54,
  249. .enable_mask = BIT(11),
  250. .hw.init = &(struct clk_init_data){
  251. .name = "pcm_clk_out",
  252. .parent_hws = (const struct clk_hw*[]) {
  253. &pcm_src.clkr.hw,
  254. },
  255. .num_parents = 1,
  256. .ops = &clk_branch_ops,
  257. .flags = CLK_SET_RATE_PARENT,
  258. },
  259. },
  260. };
  261. static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = {
  262. { .hw = &pcm_clk_out.clkr.hw, },
  263. { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
  264. };
  265. static struct clk_regmap_mux pcm_clk = {
  266. .reg = 0x54,
  267. .shift = 10,
  268. .width = 1,
  269. .clkr = {
  270. .hw.init = &(struct clk_init_data){
  271. .name = "pcm_clk",
  272. .parent_data = lcc_pcm_clk_out_codec_clk,
  273. .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk),
  274. .ops = &clk_regmap_mux_closest_ops,
  275. .flags = CLK_SET_RATE_PARENT,
  276. },
  277. },
  278. };
  279. static struct freq_tbl clk_tbl_aif_osr[] = {
  280. { 2822400, P_PLL4, 1, 147, 20480 },
  281. { 4096000, P_PLL4, 1, 1, 96 },
  282. { 5644800, P_PLL4, 1, 147, 10240 },
  283. { 6144000, P_PLL4, 1, 1, 64 },
  284. { 11289600, P_PLL4, 1, 147, 5120 },
  285. { 12288000, P_PLL4, 1, 1, 32 },
  286. { 22579200, P_PLL4, 1, 147, 2560 },
  287. { 24576000, P_PLL4, 1, 1, 16 },
  288. { },
  289. };
  290. static struct clk_rcg spdif_src = {
  291. .ns_reg = 0xcc,
  292. .md_reg = 0xd0,
  293. .mn = {
  294. .mnctr_en_bit = 8,
  295. .mnctr_reset_bit = 7,
  296. .mnctr_mode_shift = 5,
  297. .n_val_shift = 16,
  298. .m_val_shift = 16,
  299. .width = 8,
  300. },
  301. .p = {
  302. .pre_div_shift = 3,
  303. .pre_div_width = 2,
  304. },
  305. .s = {
  306. .src_sel_shift = 0,
  307. .parent_map = lcc_pxo_pll4_map,
  308. },
  309. .freq_tbl = clk_tbl_aif_osr,
  310. .clkr = {
  311. .enable_reg = 0xcc,
  312. .enable_mask = BIT(9),
  313. .hw.init = &(struct clk_init_data){
  314. .name = "spdif_src",
  315. .parent_data = lcc_pxo_pll4,
  316. .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
  317. .ops = &clk_rcg_ops,
  318. .flags = CLK_SET_RATE_GATE,
  319. },
  320. },
  321. };
  322. static struct clk_branch spdif_clk = {
  323. .halt_reg = 0xd4,
  324. .halt_bit = 1,
  325. .halt_check = BRANCH_HALT_ENABLE,
  326. .clkr = {
  327. .enable_reg = 0xcc,
  328. .enable_mask = BIT(12),
  329. .hw.init = &(struct clk_init_data){
  330. .name = "spdif_clk",
  331. .parent_hws = (const struct clk_hw*[]) {
  332. &spdif_src.clkr.hw,
  333. },
  334. .num_parents = 1,
  335. .ops = &clk_branch_ops,
  336. .flags = CLK_SET_RATE_PARENT,
  337. },
  338. },
  339. };
  340. static struct freq_tbl clk_tbl_ahbix[] = {
  341. { 131072000, P_PLL4, 1, 1, 3 },
  342. { },
  343. };
  344. static struct clk_rcg ahbix_clk = {
  345. .ns_reg = 0x38,
  346. .md_reg = 0x3c,
  347. .mn = {
  348. .mnctr_en_bit = 8,
  349. .mnctr_reset_bit = 7,
  350. .mnctr_mode_shift = 5,
  351. .n_val_shift = 24,
  352. .m_val_shift = 8,
  353. .width = 8,
  354. },
  355. .p = {
  356. .pre_div_shift = 3,
  357. .pre_div_width = 2,
  358. },
  359. .s = {
  360. .src_sel_shift = 0,
  361. .parent_map = lcc_pxo_pll4_map,
  362. },
  363. .freq_tbl = clk_tbl_ahbix,
  364. .clkr = {
  365. .enable_reg = 0x38,
  366. .enable_mask = BIT(11),
  367. .hw.init = &(struct clk_init_data){
  368. .name = "ahbix",
  369. .parent_data = lcc_pxo_pll4,
  370. .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
  371. .ops = &clk_rcg_lcc_ops,
  372. },
  373. },
  374. };
  375. static struct clk_regmap *lcc_ipq806x_clks[] = {
  376. [PLL4] = &pll4.clkr,
  377. [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
  378. [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
  379. [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
  380. [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
  381. [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
  382. [PCM_SRC] = &pcm_src.clkr,
  383. [PCM_CLK_OUT] = &pcm_clk_out.clkr,
  384. [PCM_CLK] = &pcm_clk.clkr,
  385. [SPDIF_SRC] = &spdif_src.clkr,
  386. [SPDIF_CLK] = &spdif_clk.clkr,
  387. [AHBIX_CLK] = &ahbix_clk.clkr,
  388. };
  389. static const struct qcom_reset_map lcc_ipq806x_resets[] = {
  390. [LCC_PCM_RESET] = { 0x54, 13 },
  391. };
  392. static const struct regmap_config lcc_ipq806x_regmap_config = {
  393. .reg_bits = 32,
  394. .reg_stride = 4,
  395. .val_bits = 32,
  396. .max_register = 0xfc,
  397. .fast_io = true,
  398. };
  399. static const struct qcom_cc_desc lcc_ipq806x_desc = {
  400. .config = &lcc_ipq806x_regmap_config,
  401. .clks = lcc_ipq806x_clks,
  402. .num_clks = ARRAY_SIZE(lcc_ipq806x_clks),
  403. .resets = lcc_ipq806x_resets,
  404. .num_resets = ARRAY_SIZE(lcc_ipq806x_resets),
  405. };
  406. static const struct of_device_id lcc_ipq806x_match_table[] = {
  407. { .compatible = "qcom,lcc-ipq8064" },
  408. { }
  409. };
  410. MODULE_DEVICE_TABLE(of, lcc_ipq806x_match_table);
  411. static int lcc_ipq806x_probe(struct platform_device *pdev)
  412. {
  413. u32 val;
  414. struct regmap *regmap;
  415. regmap = qcom_cc_map(pdev, &lcc_ipq806x_desc);
  416. if (IS_ERR(regmap))
  417. return PTR_ERR(regmap);
  418. /* Configure the rate of PLL4 if the bootloader hasn't already */
  419. regmap_read(regmap, 0x0, &val);
  420. if (!val)
  421. clk_pll_configure_sr(&pll4, regmap, &pll4_config, true);
  422. /* Enable PLL4 source on the LPASS Primary PLL Mux */
  423. regmap_write(regmap, 0xc4, 0x1);
  424. return qcom_cc_really_probe(pdev, &lcc_ipq806x_desc, regmap);
  425. }
  426. static struct platform_driver lcc_ipq806x_driver = {
  427. .probe = lcc_ipq806x_probe,
  428. .driver = {
  429. .name = "lcc-ipq806x",
  430. .of_match_table = lcc_ipq806x_match_table,
  431. },
  432. };
  433. module_platform_driver(lcc_ipq806x_driver);
  434. MODULE_DESCRIPTION("QCOM LCC IPQ806x Driver");
  435. MODULE_LICENSE("GPL v2");
  436. MODULE_ALIAS("platform:lcc-ipq806x");