gcc-sc7180.c 64 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk-provider.h>
  6. #include <linux/err.h>
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/of.h>
  10. #include <linux/of_device.h>
  11. #include <linux/regmap.h>
  12. #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  13. #include "clk-alpha-pll.h"
  14. #include "clk-branch.h"
  15. #include "clk-rcg.h"
  16. #include "clk-regmap.h"
  17. #include "common.h"
  18. #include "gdsc.h"
  19. #include "reset.h"
  20. enum {
  21. P_BI_TCXO,
  22. P_CORE_BI_PLL_TEST_SE,
  23. P_GPLL0_OUT_EVEN,
  24. P_GPLL0_OUT_MAIN,
  25. P_GPLL1_OUT_MAIN,
  26. P_GPLL4_OUT_MAIN,
  27. P_GPLL6_OUT_MAIN,
  28. P_GPLL7_OUT_MAIN,
  29. P_SLEEP_CLK,
  30. };
  31. static struct clk_alpha_pll gpll0 = {
  32. .offset = 0x0,
  33. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  34. .clkr = {
  35. .enable_reg = 0x52010,
  36. .enable_mask = BIT(0),
  37. .hw.init = &(struct clk_init_data){
  38. .name = "gpll0",
  39. .parent_data = &(const struct clk_parent_data){
  40. .fw_name = "bi_tcxo",
  41. .name = "bi_tcxo",
  42. },
  43. .num_parents = 1,
  44. .ops = &clk_alpha_pll_fixed_fabia_ops,
  45. },
  46. },
  47. };
  48. static const struct clk_div_table post_div_table_gpll0_out_even[] = {
  49. { 0x1, 2 },
  50. { }
  51. };
  52. static struct clk_alpha_pll_postdiv gpll0_out_even = {
  53. .offset = 0x0,
  54. .post_div_shift = 8,
  55. .post_div_table = post_div_table_gpll0_out_even,
  56. .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
  57. .width = 4,
  58. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  59. .clkr.hw.init = &(struct clk_init_data){
  60. .name = "gpll0_out_even",
  61. .parent_hws = (const struct clk_hw*[]){
  62. &gpll0.clkr.hw,
  63. },
  64. .num_parents = 1,
  65. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  66. },
  67. };
  68. static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
  69. .mult = 1,
  70. .div = 2,
  71. .hw.init = &(struct clk_init_data){
  72. .name = "gcc_pll0_main_div_cdiv",
  73. .parent_hws = (const struct clk_hw*[]){
  74. &gpll0.clkr.hw,
  75. },
  76. .num_parents = 1,
  77. .ops = &clk_fixed_factor_ops,
  78. },
  79. };
  80. static struct clk_alpha_pll gpll1 = {
  81. .offset = 0x01000,
  82. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  83. .clkr = {
  84. .enable_reg = 0x52010,
  85. .enable_mask = BIT(1),
  86. .hw.init = &(struct clk_init_data){
  87. .name = "gpll1",
  88. .parent_data = &(const struct clk_parent_data){
  89. .fw_name = "bi_tcxo",
  90. .name = "bi_tcxo",
  91. },
  92. .num_parents = 1,
  93. .ops = &clk_alpha_pll_fixed_fabia_ops,
  94. },
  95. },
  96. };
  97. static struct clk_alpha_pll gpll4 = {
  98. .offset = 0x76000,
  99. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  100. .clkr = {
  101. .enable_reg = 0x52010,
  102. .enable_mask = BIT(4),
  103. .hw.init = &(struct clk_init_data){
  104. .name = "gpll4",
  105. .parent_data = &(const struct clk_parent_data){
  106. .fw_name = "bi_tcxo",
  107. .name = "bi_tcxo",
  108. },
  109. .num_parents = 1,
  110. .ops = &clk_alpha_pll_fixed_fabia_ops,
  111. },
  112. },
  113. };
  114. static struct clk_alpha_pll gpll6 = {
  115. .offset = 0x13000,
  116. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  117. .clkr = {
  118. .enable_reg = 0x52010,
  119. .enable_mask = BIT(6),
  120. .hw.init = &(struct clk_init_data){
  121. .name = "gpll6",
  122. .parent_data = &(const struct clk_parent_data){
  123. .fw_name = "bi_tcxo",
  124. .name = "bi_tcxo",
  125. },
  126. .num_parents = 1,
  127. .ops = &clk_alpha_pll_fixed_fabia_ops,
  128. },
  129. },
  130. };
  131. static struct clk_alpha_pll gpll7 = {
  132. .offset = 0x27000,
  133. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  134. .clkr = {
  135. .enable_reg = 0x52010,
  136. .enable_mask = BIT(7),
  137. .hw.init = &(struct clk_init_data){
  138. .name = "gpll7",
  139. .parent_data = &(const struct clk_parent_data){
  140. .fw_name = "bi_tcxo",
  141. .name = "bi_tcxo",
  142. },
  143. .num_parents = 1,
  144. .ops = &clk_alpha_pll_fixed_fabia_ops,
  145. },
  146. },
  147. };
  148. static const struct parent_map gcc_parent_map_0[] = {
  149. { P_BI_TCXO, 0 },
  150. { P_GPLL0_OUT_MAIN, 1 },
  151. { P_GPLL0_OUT_EVEN, 6 },
  152. { P_CORE_BI_PLL_TEST_SE, 7 },
  153. };
  154. static const struct clk_parent_data gcc_parent_data_0[] = {
  155. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  156. { .hw = &gpll0.clkr.hw },
  157. { .hw = &gpll0_out_even.clkr.hw },
  158. { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
  159. };
  160. static const struct clk_parent_data gcc_parent_data_0_ao[] = {
  161. { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
  162. { .hw = &gpll0.clkr.hw },
  163. { .hw = &gpll0_out_even.clkr.hw },
  164. { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
  165. };
  166. static const struct parent_map gcc_parent_map_1[] = {
  167. { P_BI_TCXO, 0 },
  168. { P_GPLL0_OUT_MAIN, 1 },
  169. { P_GPLL6_OUT_MAIN, 2 },
  170. { P_GPLL0_OUT_EVEN, 6 },
  171. { P_CORE_BI_PLL_TEST_SE, 7 },
  172. };
  173. static const struct clk_parent_data gcc_parent_data_1[] = {
  174. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  175. { .hw = &gpll0.clkr.hw },
  176. { .hw = &gpll6.clkr.hw },
  177. { .hw = &gpll0_out_even.clkr.hw },
  178. { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
  179. };
  180. static const struct parent_map gcc_parent_map_2[] = {
  181. { P_BI_TCXO, 0 },
  182. { P_GPLL0_OUT_MAIN, 1 },
  183. { P_GPLL1_OUT_MAIN, 4 },
  184. { P_GPLL4_OUT_MAIN, 5 },
  185. { P_GPLL0_OUT_EVEN, 6 },
  186. { P_CORE_BI_PLL_TEST_SE, 7 },
  187. };
  188. static const struct clk_parent_data gcc_parent_data_2[] = {
  189. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  190. { .hw = &gpll0.clkr.hw },
  191. { .hw = &gpll1.clkr.hw },
  192. { .hw = &gpll4.clkr.hw },
  193. { .hw = &gpll0_out_even.clkr.hw },
  194. { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
  195. };
  196. static const struct parent_map gcc_parent_map_3[] = {
  197. { P_BI_TCXO, 0 },
  198. { P_GPLL0_OUT_MAIN, 1 },
  199. { P_CORE_BI_PLL_TEST_SE, 7 },
  200. };
  201. static const struct clk_parent_data gcc_parent_data_3[] = {
  202. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  203. { .hw = &gpll0.clkr.hw },
  204. { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
  205. };
  206. static const struct parent_map gcc_parent_map_4[] = {
  207. { P_BI_TCXO, 0 },
  208. { P_GPLL0_OUT_MAIN, 1 },
  209. { P_SLEEP_CLK, 5 },
  210. { P_GPLL0_OUT_EVEN, 6 },
  211. { P_CORE_BI_PLL_TEST_SE, 7 },
  212. };
  213. static const struct clk_parent_data gcc_parent_data_4[] = {
  214. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  215. { .hw = &gpll0.clkr.hw },
  216. { .fw_name = "sleep_clk", .name = "sleep_clk" },
  217. { .hw = &gpll0_out_even.clkr.hw },
  218. { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
  219. };
  220. static const struct parent_map gcc_parent_map_5[] = {
  221. { P_BI_TCXO, 0 },
  222. { P_GPLL0_OUT_MAIN, 1 },
  223. { P_GPLL7_OUT_MAIN, 3 },
  224. { P_GPLL0_OUT_EVEN, 6 },
  225. { P_CORE_BI_PLL_TEST_SE, 7 },
  226. };
  227. static const struct clk_parent_data gcc_parent_data_5[] = {
  228. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  229. { .hw = &gpll0.clkr.hw },
  230. { .hw = &gpll7.clkr.hw },
  231. { .hw = &gpll0_out_even.clkr.hw },
  232. { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
  233. };
  234. static const struct parent_map gcc_parent_map_6[] = {
  235. { P_BI_TCXO, 0 },
  236. { P_GPLL0_OUT_MAIN, 1 },
  237. { P_SLEEP_CLK, 5 },
  238. { P_CORE_BI_PLL_TEST_SE, 7 },
  239. };
  240. static const struct clk_parent_data gcc_parent_data_6[] = {
  241. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  242. { .hw = &gpll0.clkr.hw },
  243. { .fw_name = "sleep_clk", .name = "sleep_clk" },
  244. { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
  245. };
  246. static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
  247. F(19200000, P_BI_TCXO, 1, 0, 0),
  248. { }
  249. };
  250. static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
  251. .cmd_rcgr = 0x48014,
  252. .mnd_width = 0,
  253. .hid_width = 5,
  254. .parent_map = gcc_parent_map_0,
  255. .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
  256. .clkr.hw.init = &(struct clk_init_data){
  257. .name = "gcc_cpuss_ahb_clk_src",
  258. .parent_data = gcc_parent_data_0_ao,
  259. .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
  260. .flags = CLK_SET_RATE_PARENT,
  261. .ops = &clk_rcg2_ops,
  262. },
  263. };
  264. static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
  265. F(19200000, P_BI_TCXO, 1, 0, 0),
  266. F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
  267. F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
  268. F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
  269. F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
  270. { }
  271. };
  272. static struct clk_rcg2 gcc_gp1_clk_src = {
  273. .cmd_rcgr = 0x64004,
  274. .mnd_width = 8,
  275. .hid_width = 5,
  276. .parent_map = gcc_parent_map_4,
  277. .freq_tbl = ftbl_gcc_gp1_clk_src,
  278. .clkr.hw.init = &(struct clk_init_data){
  279. .name = "gcc_gp1_clk_src",
  280. .parent_data = gcc_parent_data_4,
  281. .num_parents = ARRAY_SIZE(gcc_parent_data_4),
  282. .ops = &clk_rcg2_ops,
  283. },
  284. };
  285. static struct clk_rcg2 gcc_gp2_clk_src = {
  286. .cmd_rcgr = 0x65004,
  287. .mnd_width = 8,
  288. .hid_width = 5,
  289. .parent_map = gcc_parent_map_4,
  290. .freq_tbl = ftbl_gcc_gp1_clk_src,
  291. .clkr.hw.init = &(struct clk_init_data){
  292. .name = "gcc_gp2_clk_src",
  293. .parent_data = gcc_parent_data_4,
  294. .num_parents = ARRAY_SIZE(gcc_parent_data_4),
  295. .ops = &clk_rcg2_ops,
  296. },
  297. };
  298. static struct clk_rcg2 gcc_gp3_clk_src = {
  299. .cmd_rcgr = 0x66004,
  300. .mnd_width = 8,
  301. .hid_width = 5,
  302. .parent_map = gcc_parent_map_4,
  303. .freq_tbl = ftbl_gcc_gp1_clk_src,
  304. .clkr.hw.init = &(struct clk_init_data){
  305. .name = "gcc_gp3_clk_src",
  306. .parent_data = gcc_parent_data_4,
  307. .num_parents = ARRAY_SIZE(gcc_parent_data_4),
  308. .ops = &clk_rcg2_ops,
  309. },
  310. };
  311. static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
  312. F(19200000, P_BI_TCXO, 1, 0, 0),
  313. F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
  314. { }
  315. };
  316. static struct clk_rcg2 gcc_pdm2_clk_src = {
  317. .cmd_rcgr = 0x33010,
  318. .mnd_width = 0,
  319. .hid_width = 5,
  320. .parent_map = gcc_parent_map_0,
  321. .freq_tbl = ftbl_gcc_pdm2_clk_src,
  322. .clkr.hw.init = &(struct clk_init_data){
  323. .name = "gcc_pdm2_clk_src",
  324. .parent_data = gcc_parent_data_0,
  325. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  326. .ops = &clk_rcg2_ops,
  327. },
  328. };
  329. static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
  330. F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
  331. F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
  332. F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
  333. { }
  334. };
  335. static struct clk_rcg2 gcc_qspi_core_clk_src = {
  336. .cmd_rcgr = 0x4b00c,
  337. .mnd_width = 0,
  338. .hid_width = 5,
  339. .parent_map = gcc_parent_map_2,
  340. .freq_tbl = ftbl_gcc_qspi_core_clk_src,
  341. .clkr.hw.init = &(struct clk_init_data){
  342. .name = "gcc_qspi_core_clk_src",
  343. .parent_data = gcc_parent_data_2,
  344. .num_parents = ARRAY_SIZE(gcc_parent_data_2),
  345. .ops = &clk_rcg2_ops,
  346. },
  347. };
  348. static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
  349. F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
  350. F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
  351. F(19200000, P_BI_TCXO, 1, 0, 0),
  352. F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
  353. F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
  354. F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
  355. F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
  356. F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
  357. F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
  358. F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
  359. F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
  360. F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
  361. F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
  362. F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
  363. F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
  364. F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
  365. F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
  366. { }
  367. };
  368. static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
  369. .name = "gcc_qupv3_wrap0_s0_clk_src",
  370. .parent_data = gcc_parent_data_1,
  371. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  372. .ops = &clk_rcg2_ops,
  373. };
  374. static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
  375. .cmd_rcgr = 0x17034,
  376. .mnd_width = 16,
  377. .hid_width = 5,
  378. .parent_map = gcc_parent_map_1,
  379. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  380. .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
  381. };
  382. static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
  383. .name = "gcc_qupv3_wrap0_s1_clk_src",
  384. .parent_data = gcc_parent_data_1,
  385. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  386. .ops = &clk_rcg2_ops,
  387. };
  388. static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
  389. .cmd_rcgr = 0x17164,
  390. .mnd_width = 16,
  391. .hid_width = 5,
  392. .parent_map = gcc_parent_map_1,
  393. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  394. .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
  395. };
  396. static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
  397. .name = "gcc_qupv3_wrap0_s2_clk_src",
  398. .parent_data = gcc_parent_data_1,
  399. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  400. .ops = &clk_rcg2_ops,
  401. };
  402. static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
  403. .cmd_rcgr = 0x17294,
  404. .mnd_width = 16,
  405. .hid_width = 5,
  406. .parent_map = gcc_parent_map_1,
  407. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  408. .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
  409. };
  410. static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
  411. .name = "gcc_qupv3_wrap0_s3_clk_src",
  412. .parent_data = gcc_parent_data_1,
  413. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  414. .ops = &clk_rcg2_ops,
  415. };
  416. static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
  417. .cmd_rcgr = 0x173c4,
  418. .mnd_width = 16,
  419. .hid_width = 5,
  420. .parent_map = gcc_parent_map_1,
  421. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  422. .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
  423. };
  424. static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
  425. .name = "gcc_qupv3_wrap0_s4_clk_src",
  426. .parent_data = gcc_parent_data_1,
  427. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  428. .ops = &clk_rcg2_ops,
  429. };
  430. static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
  431. .cmd_rcgr = 0x174f4,
  432. .mnd_width = 16,
  433. .hid_width = 5,
  434. .parent_map = gcc_parent_map_1,
  435. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  436. .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
  437. };
  438. static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
  439. .name = "gcc_qupv3_wrap0_s5_clk_src",
  440. .parent_data = gcc_parent_data_1,
  441. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  442. .ops = &clk_rcg2_ops,
  443. };
  444. static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
  445. .cmd_rcgr = 0x17624,
  446. .mnd_width = 16,
  447. .hid_width = 5,
  448. .parent_map = gcc_parent_map_1,
  449. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  450. .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
  451. };
  452. static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
  453. .name = "gcc_qupv3_wrap1_s0_clk_src",
  454. .parent_data = gcc_parent_data_1,
  455. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  456. .ops = &clk_rcg2_ops,
  457. };
  458. static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
  459. .cmd_rcgr = 0x18018,
  460. .mnd_width = 16,
  461. .hid_width = 5,
  462. .parent_map = gcc_parent_map_1,
  463. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  464. .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
  465. };
  466. static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
  467. .name = "gcc_qupv3_wrap1_s1_clk_src",
  468. .parent_data = gcc_parent_data_1,
  469. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  470. .ops = &clk_rcg2_ops,
  471. };
  472. static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
  473. .cmd_rcgr = 0x18148,
  474. .mnd_width = 16,
  475. .hid_width = 5,
  476. .parent_map = gcc_parent_map_1,
  477. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  478. .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
  479. };
  480. static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
  481. .name = "gcc_qupv3_wrap1_s2_clk_src",
  482. .parent_data = gcc_parent_data_1,
  483. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  484. .ops = &clk_rcg2_ops,
  485. };
  486. static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
  487. .cmd_rcgr = 0x18278,
  488. .mnd_width = 16,
  489. .hid_width = 5,
  490. .parent_map = gcc_parent_map_1,
  491. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  492. .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
  493. };
  494. static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
  495. .name = "gcc_qupv3_wrap1_s3_clk_src",
  496. .parent_data = gcc_parent_data_1,
  497. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  498. .ops = &clk_rcg2_ops,
  499. };
  500. static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
  501. .cmd_rcgr = 0x183a8,
  502. .mnd_width = 16,
  503. .hid_width = 5,
  504. .parent_map = gcc_parent_map_1,
  505. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  506. .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
  507. };
  508. static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
  509. .name = "gcc_qupv3_wrap1_s4_clk_src",
  510. .parent_data = gcc_parent_data_1,
  511. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  512. .ops = &clk_rcg2_ops,
  513. };
  514. static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
  515. .cmd_rcgr = 0x184d8,
  516. .mnd_width = 16,
  517. .hid_width = 5,
  518. .parent_map = gcc_parent_map_1,
  519. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  520. .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
  521. };
  522. static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
  523. .name = "gcc_qupv3_wrap1_s5_clk_src",
  524. .parent_data = gcc_parent_data_1,
  525. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  526. .ops = &clk_rcg2_ops,
  527. };
  528. static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
  529. .cmd_rcgr = 0x18608,
  530. .mnd_width = 16,
  531. .hid_width = 5,
  532. .parent_map = gcc_parent_map_1,
  533. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  534. .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
  535. };
  536. static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
  537. F(144000, P_BI_TCXO, 16, 3, 25),
  538. F(400000, P_BI_TCXO, 12, 1, 4),
  539. F(19200000, P_BI_TCXO, 1, 0, 0),
  540. F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
  541. F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
  542. F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
  543. F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
  544. F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
  545. F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
  546. { }
  547. };
  548. static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
  549. .cmd_rcgr = 0x12028,
  550. .mnd_width = 8,
  551. .hid_width = 5,
  552. .parent_map = gcc_parent_map_1,
  553. .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
  554. .clkr.hw.init = &(struct clk_init_data){
  555. .name = "gcc_sdcc1_apps_clk_src",
  556. .parent_data = gcc_parent_data_1,
  557. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  558. .ops = &clk_rcg2_floor_ops,
  559. },
  560. };
  561. static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
  562. F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
  563. F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
  564. F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
  565. F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
  566. { }
  567. };
  568. static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
  569. .cmd_rcgr = 0x12010,
  570. .mnd_width = 0,
  571. .hid_width = 5,
  572. .parent_map = gcc_parent_map_0,
  573. .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
  574. .clkr.hw.init = &(struct clk_init_data){
  575. .name = "gcc_sdcc1_ice_core_clk_src",
  576. .parent_data = gcc_parent_data_0,
  577. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  578. .ops = &clk_rcg2_ops,
  579. },
  580. };
  581. static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
  582. F(400000, P_BI_TCXO, 12, 1, 4),
  583. F(9600000, P_BI_TCXO, 2, 0, 0),
  584. F(19200000, P_BI_TCXO, 1, 0, 0),
  585. F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
  586. F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
  587. F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
  588. F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
  589. { }
  590. };
  591. static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
  592. .cmd_rcgr = 0x1400c,
  593. .mnd_width = 8,
  594. .hid_width = 5,
  595. .parent_map = gcc_parent_map_5,
  596. .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
  597. .clkr.hw.init = &(struct clk_init_data){
  598. .name = "gcc_sdcc2_apps_clk_src",
  599. .parent_data = gcc_parent_data_5,
  600. .num_parents = ARRAY_SIZE(gcc_parent_data_5),
  601. .flags = CLK_OPS_PARENT_ENABLE,
  602. .ops = &clk_rcg2_floor_ops,
  603. },
  604. };
  605. static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
  606. F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
  607. F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
  608. F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
  609. F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
  610. F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
  611. { }
  612. };
  613. static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
  614. .cmd_rcgr = 0x77020,
  615. .mnd_width = 8,
  616. .hid_width = 5,
  617. .parent_map = gcc_parent_map_0,
  618. .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
  619. .clkr.hw.init = &(struct clk_init_data){
  620. .name = "gcc_ufs_phy_axi_clk_src",
  621. .parent_data = gcc_parent_data_0,
  622. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  623. .ops = &clk_rcg2_ops,
  624. },
  625. };
  626. static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
  627. F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
  628. F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
  629. F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
  630. F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
  631. { }
  632. };
  633. static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
  634. .cmd_rcgr = 0x77048,
  635. .mnd_width = 0,
  636. .hid_width = 5,
  637. .parent_map = gcc_parent_map_0,
  638. .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
  639. .clkr.hw.init = &(struct clk_init_data){
  640. .name = "gcc_ufs_phy_ice_core_clk_src",
  641. .parent_data = gcc_parent_data_0,
  642. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  643. .ops = &clk_rcg2_ops,
  644. },
  645. };
  646. static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
  647. F(9600000, P_BI_TCXO, 2, 0, 0),
  648. F(19200000, P_BI_TCXO, 1, 0, 0),
  649. { }
  650. };
  651. static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
  652. .cmd_rcgr = 0x77098,
  653. .mnd_width = 0,
  654. .hid_width = 5,
  655. .parent_map = gcc_parent_map_3,
  656. .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
  657. .clkr.hw.init = &(struct clk_init_data){
  658. .name = "gcc_ufs_phy_phy_aux_clk_src",
  659. .parent_data = gcc_parent_data_3,
  660. .num_parents = ARRAY_SIZE(gcc_parent_data_3),
  661. .ops = &clk_rcg2_ops,
  662. },
  663. };
  664. static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
  665. F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
  666. F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
  667. F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
  668. { }
  669. };
  670. static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
  671. .cmd_rcgr = 0x77060,
  672. .mnd_width = 0,
  673. .hid_width = 5,
  674. .parent_map = gcc_parent_map_0,
  675. .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
  676. .clkr.hw.init = &(struct clk_init_data){
  677. .name = "gcc_ufs_phy_unipro_core_clk_src",
  678. .parent_data = gcc_parent_data_0,
  679. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  680. .ops = &clk_rcg2_ops,
  681. },
  682. };
  683. static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
  684. F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
  685. F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
  686. F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
  687. F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
  688. { }
  689. };
  690. static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
  691. .cmd_rcgr = 0xf01c,
  692. .mnd_width = 8,
  693. .hid_width = 5,
  694. .parent_map = gcc_parent_map_0,
  695. .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
  696. .clkr.hw.init = &(struct clk_init_data){
  697. .name = "gcc_usb30_prim_master_clk_src",
  698. .parent_data = gcc_parent_data_0,
  699. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  700. .ops = &clk_rcg2_ops,
  701. },
  702. };
  703. static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
  704. F(19200000, P_BI_TCXO, 1, 0, 0),
  705. F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
  706. { }
  707. };
  708. static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
  709. .cmd_rcgr = 0xf034,
  710. .mnd_width = 0,
  711. .hid_width = 5,
  712. .parent_map = gcc_parent_map_0,
  713. .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
  714. .clkr.hw.init = &(struct clk_init_data){
  715. .name = "gcc_usb30_prim_mock_utmi_clk_src",
  716. .parent_data = gcc_parent_data_0,
  717. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  718. .ops = &clk_rcg2_ops,
  719. },
  720. };
  721. static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
  722. F(19200000, P_BI_TCXO, 1, 0, 0),
  723. { }
  724. };
  725. static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
  726. .cmd_rcgr = 0xf060,
  727. .mnd_width = 0,
  728. .hid_width = 5,
  729. .parent_map = gcc_parent_map_6,
  730. .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
  731. .clkr.hw.init = &(struct clk_init_data){
  732. .name = "gcc_usb3_prim_phy_aux_clk_src",
  733. .parent_data = gcc_parent_data_6,
  734. .num_parents = ARRAY_SIZE(gcc_parent_data_6),
  735. .ops = &clk_rcg2_ops,
  736. },
  737. };
  738. static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
  739. F(4800000, P_BI_TCXO, 4, 0, 0),
  740. F(19200000, P_BI_TCXO, 1, 0, 0),
  741. { }
  742. };
  743. static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
  744. .cmd_rcgr = 0x3d030,
  745. .mnd_width = 0,
  746. .hid_width = 5,
  747. .parent_map = gcc_parent_map_3,
  748. .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
  749. .clkr.hw.init = &(struct clk_init_data){
  750. .name = "gcc_sec_ctrl_clk_src",
  751. .parent_data = gcc_parent_data_3,
  752. .num_parents = ARRAY_SIZE(gcc_parent_data_3),
  753. .ops = &clk_rcg2_ops,
  754. },
  755. };
  756. static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
  757. .halt_reg = 0x82024,
  758. .halt_check = BRANCH_HALT_DELAY,
  759. .hwcg_reg = 0x82024,
  760. .hwcg_bit = 1,
  761. .clkr = {
  762. .enable_reg = 0x82024,
  763. .enable_mask = BIT(0),
  764. .hw.init = &(struct clk_init_data){
  765. .name = "gcc_aggre_ufs_phy_axi_clk",
  766. .parent_hws = (const struct clk_hw*[]){
  767. &gcc_ufs_phy_axi_clk_src.clkr.hw,
  768. },
  769. .num_parents = 1,
  770. .flags = CLK_SET_RATE_PARENT,
  771. .ops = &clk_branch2_ops,
  772. },
  773. },
  774. };
  775. static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
  776. .halt_reg = 0x8201c,
  777. .halt_check = BRANCH_HALT,
  778. .clkr = {
  779. .enable_reg = 0x8201c,
  780. .enable_mask = BIT(0),
  781. .hw.init = &(struct clk_init_data){
  782. .name = "gcc_aggre_usb3_prim_axi_clk",
  783. .parent_hws = (const struct clk_hw*[]){
  784. &gcc_usb30_prim_master_clk_src.clkr.hw,
  785. },
  786. .num_parents = 1,
  787. .flags = CLK_SET_RATE_PARENT,
  788. .ops = &clk_branch2_ops,
  789. },
  790. },
  791. };
  792. static struct clk_branch gcc_boot_rom_ahb_clk = {
  793. .halt_reg = 0x38004,
  794. .halt_check = BRANCH_HALT_VOTED,
  795. .hwcg_reg = 0x38004,
  796. .hwcg_bit = 1,
  797. .clkr = {
  798. .enable_reg = 0x52000,
  799. .enable_mask = BIT(10),
  800. .hw.init = &(struct clk_init_data){
  801. .name = "gcc_boot_rom_ahb_clk",
  802. .ops = &clk_branch2_ops,
  803. },
  804. },
  805. };
  806. static struct clk_branch gcc_camera_hf_axi_clk = {
  807. .halt_reg = 0xb020,
  808. .halt_check = BRANCH_HALT,
  809. .clkr = {
  810. .enable_reg = 0xb020,
  811. .enable_mask = BIT(0),
  812. .hw.init = &(struct clk_init_data){
  813. .name = "gcc_camera_hf_axi_clk",
  814. .ops = &clk_branch2_ops,
  815. },
  816. },
  817. };
  818. static struct clk_branch gcc_camera_throttle_hf_axi_clk = {
  819. .halt_reg = 0xb080,
  820. .halt_check = BRANCH_HALT,
  821. .hwcg_reg = 0xb080,
  822. .hwcg_bit = 1,
  823. .clkr = {
  824. .enable_reg = 0xb080,
  825. .enable_mask = BIT(0),
  826. .hw.init = &(struct clk_init_data){
  827. .name = "gcc_camera_throttle_hf_axi_clk",
  828. .ops = &clk_branch2_ops,
  829. },
  830. },
  831. };
  832. static struct clk_branch gcc_ce1_ahb_clk = {
  833. .halt_reg = 0x4100c,
  834. .halt_check = BRANCH_HALT_VOTED,
  835. .hwcg_reg = 0x4100c,
  836. .hwcg_bit = 1,
  837. .clkr = {
  838. .enable_reg = 0x52000,
  839. .enable_mask = BIT(3),
  840. .hw.init = &(struct clk_init_data){
  841. .name = "gcc_ce1_ahb_clk",
  842. .ops = &clk_branch2_ops,
  843. },
  844. },
  845. };
  846. static struct clk_branch gcc_ce1_axi_clk = {
  847. .halt_reg = 0x41008,
  848. .halt_check = BRANCH_HALT_VOTED,
  849. .clkr = {
  850. .enable_reg = 0x52000,
  851. .enable_mask = BIT(4),
  852. .hw.init = &(struct clk_init_data){
  853. .name = "gcc_ce1_axi_clk",
  854. .ops = &clk_branch2_ops,
  855. },
  856. },
  857. };
  858. static struct clk_branch gcc_ce1_clk = {
  859. .halt_reg = 0x41004,
  860. .halt_check = BRANCH_HALT_VOTED,
  861. .clkr = {
  862. .enable_reg = 0x52000,
  863. .enable_mask = BIT(5),
  864. .hw.init = &(struct clk_init_data){
  865. .name = "gcc_ce1_clk",
  866. .ops = &clk_branch2_ops,
  867. },
  868. },
  869. };
  870. static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
  871. .halt_reg = 0x502c,
  872. .halt_check = BRANCH_HALT,
  873. .clkr = {
  874. .enable_reg = 0x502c,
  875. .enable_mask = BIT(0),
  876. .hw.init = &(struct clk_init_data){
  877. .name = "gcc_cfg_noc_usb3_prim_axi_clk",
  878. .parent_hws = (const struct clk_hw*[]){
  879. &gcc_usb30_prim_master_clk_src.clkr.hw,
  880. },
  881. .num_parents = 1,
  882. .flags = CLK_SET_RATE_PARENT,
  883. .ops = &clk_branch2_ops,
  884. },
  885. },
  886. };
  887. /* For CPUSS functionality the AHB clock needs to be left enabled */
  888. static struct clk_branch gcc_cpuss_ahb_clk = {
  889. .halt_reg = 0x48000,
  890. .halt_check = BRANCH_HALT_VOTED,
  891. .clkr = {
  892. .enable_reg = 0x52000,
  893. .enable_mask = BIT(21),
  894. .hw.init = &(struct clk_init_data){
  895. .name = "gcc_cpuss_ahb_clk",
  896. .parent_hws = (const struct clk_hw*[]){
  897. &gcc_cpuss_ahb_clk_src.clkr.hw,
  898. },
  899. .num_parents = 1,
  900. .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
  901. .ops = &clk_branch2_ops,
  902. },
  903. },
  904. };
  905. static struct clk_branch gcc_cpuss_rbcpr_clk = {
  906. .halt_reg = 0x48008,
  907. .halt_check = BRANCH_HALT,
  908. .clkr = {
  909. .enable_reg = 0x48008,
  910. .enable_mask = BIT(0),
  911. .hw.init = &(struct clk_init_data){
  912. .name = "gcc_cpuss_rbcpr_clk",
  913. .ops = &clk_branch2_ops,
  914. },
  915. },
  916. };
  917. static struct clk_branch gcc_ddrss_gpu_axi_clk = {
  918. .halt_reg = 0x4452c,
  919. .halt_check = BRANCH_VOTED,
  920. .clkr = {
  921. .enable_reg = 0x4452c,
  922. .enable_mask = BIT(0),
  923. .hw.init = &(struct clk_init_data){
  924. .name = "gcc_ddrss_gpu_axi_clk",
  925. .ops = &clk_branch2_ops,
  926. },
  927. },
  928. };
  929. static struct clk_branch gcc_disp_gpll0_clk_src = {
  930. .halt_check = BRANCH_HALT_DELAY,
  931. .clkr = {
  932. .enable_reg = 0x52000,
  933. .enable_mask = BIT(18),
  934. .hw.init = &(struct clk_init_data){
  935. .name = "gcc_disp_gpll0_clk_src",
  936. .parent_hws = (const struct clk_hw*[]){
  937. &gpll0.clkr.hw,
  938. },
  939. .num_parents = 1,
  940. .ops = &clk_branch2_aon_ops,
  941. },
  942. },
  943. };
  944. static struct clk_branch gcc_disp_gpll0_div_clk_src = {
  945. .halt_check = BRANCH_HALT_DELAY,
  946. .clkr = {
  947. .enable_reg = 0x52000,
  948. .enable_mask = BIT(19),
  949. .hw.init = &(struct clk_init_data){
  950. .name = "gcc_disp_gpll0_div_clk_src",
  951. .parent_hws = (const struct clk_hw*[]){
  952. &gcc_pll0_main_div_cdiv.hw,
  953. },
  954. .num_parents = 1,
  955. .ops = &clk_branch2_ops,
  956. },
  957. },
  958. };
  959. static struct clk_branch gcc_disp_hf_axi_clk = {
  960. .halt_reg = 0xb024,
  961. .halt_check = BRANCH_HALT,
  962. .clkr = {
  963. .enable_reg = 0xb024,
  964. .enable_mask = BIT(0),
  965. .hw.init = &(struct clk_init_data){
  966. .name = "gcc_disp_hf_axi_clk",
  967. .ops = &clk_branch2_ops,
  968. },
  969. },
  970. };
  971. static struct clk_branch gcc_disp_throttle_hf_axi_clk = {
  972. .halt_reg = 0xb084,
  973. .halt_check = BRANCH_HALT,
  974. .hwcg_reg = 0xb084,
  975. .hwcg_bit = 1,
  976. .clkr = {
  977. .enable_reg = 0xb084,
  978. .enable_mask = BIT(0),
  979. .hw.init = &(struct clk_init_data){
  980. .name = "gcc_disp_throttle_hf_axi_clk",
  981. .ops = &clk_branch2_ops,
  982. },
  983. },
  984. };
  985. static struct clk_branch gcc_gp1_clk = {
  986. .halt_reg = 0x64000,
  987. .halt_check = BRANCH_HALT,
  988. .clkr = {
  989. .enable_reg = 0x64000,
  990. .enable_mask = BIT(0),
  991. .hw.init = &(struct clk_init_data){
  992. .name = "gcc_gp1_clk",
  993. .parent_hws = (const struct clk_hw*[]){
  994. &gcc_gp1_clk_src.clkr.hw,
  995. },
  996. .num_parents = 1,
  997. .flags = CLK_SET_RATE_PARENT,
  998. .ops = &clk_branch2_ops,
  999. },
  1000. },
  1001. };
  1002. static struct clk_branch gcc_gp2_clk = {
  1003. .halt_reg = 0x65000,
  1004. .halt_check = BRANCH_HALT,
  1005. .clkr = {
  1006. .enable_reg = 0x65000,
  1007. .enable_mask = BIT(0),
  1008. .hw.init = &(struct clk_init_data){
  1009. .name = "gcc_gp2_clk",
  1010. .parent_hws = (const struct clk_hw*[]){
  1011. &gcc_gp2_clk_src.clkr.hw,
  1012. },
  1013. .num_parents = 1,
  1014. .flags = CLK_SET_RATE_PARENT,
  1015. .ops = &clk_branch2_ops,
  1016. },
  1017. },
  1018. };
  1019. static struct clk_branch gcc_gp3_clk = {
  1020. .halt_reg = 0x66000,
  1021. .halt_check = BRANCH_HALT,
  1022. .clkr = {
  1023. .enable_reg = 0x66000,
  1024. .enable_mask = BIT(0),
  1025. .hw.init = &(struct clk_init_data){
  1026. .name = "gcc_gp3_clk",
  1027. .parent_hws = (const struct clk_hw*[]){
  1028. &gcc_gp3_clk_src.clkr.hw,
  1029. },
  1030. .num_parents = 1,
  1031. .flags = CLK_SET_RATE_PARENT,
  1032. .ops = &clk_branch2_ops,
  1033. },
  1034. },
  1035. };
  1036. static struct clk_branch gcc_gpu_gpll0_clk_src = {
  1037. .halt_check = BRANCH_HALT_DELAY,
  1038. .clkr = {
  1039. .enable_reg = 0x52000,
  1040. .enable_mask = BIT(15),
  1041. .hw.init = &(struct clk_init_data){
  1042. .name = "gcc_gpu_gpll0_clk_src",
  1043. .parent_hws = (const struct clk_hw*[]){
  1044. &gpll0.clkr.hw,
  1045. },
  1046. .num_parents = 1,
  1047. .ops = &clk_branch2_ops,
  1048. },
  1049. },
  1050. };
  1051. static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
  1052. .halt_check = BRANCH_HALT_DELAY,
  1053. .clkr = {
  1054. .enable_reg = 0x52000,
  1055. .enable_mask = BIT(16),
  1056. .hw.init = &(struct clk_init_data){
  1057. .name = "gcc_gpu_gpll0_div_clk_src",
  1058. .parent_hws = (const struct clk_hw*[]){
  1059. &gcc_pll0_main_div_cdiv.hw,
  1060. },
  1061. .num_parents = 1,
  1062. .ops = &clk_branch2_ops,
  1063. },
  1064. },
  1065. };
  1066. static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
  1067. .halt_reg = 0x7100c,
  1068. .halt_check = BRANCH_VOTED,
  1069. .clkr = {
  1070. .enable_reg = 0x7100c,
  1071. .enable_mask = BIT(0),
  1072. .hw.init = &(struct clk_init_data){
  1073. .name = "gcc_gpu_memnoc_gfx_clk",
  1074. .ops = &clk_branch2_ops,
  1075. },
  1076. },
  1077. };
  1078. static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
  1079. .halt_reg = 0x71018,
  1080. .halt_check = BRANCH_HALT,
  1081. .clkr = {
  1082. .enable_reg = 0x71018,
  1083. .enable_mask = BIT(0),
  1084. .hw.init = &(struct clk_init_data){
  1085. .name = "gcc_gpu_snoc_dvm_gfx_clk",
  1086. .ops = &clk_branch2_ops,
  1087. },
  1088. },
  1089. };
  1090. static struct clk_branch gcc_npu_axi_clk = {
  1091. .halt_reg = 0x4d008,
  1092. .halt_check = BRANCH_HALT,
  1093. .clkr = {
  1094. .enable_reg = 0x4d008,
  1095. .enable_mask = BIT(0),
  1096. .hw.init = &(struct clk_init_data){
  1097. .name = "gcc_npu_axi_clk",
  1098. .ops = &clk_branch2_ops,
  1099. },
  1100. },
  1101. };
  1102. static struct clk_branch gcc_npu_bwmon_axi_clk = {
  1103. .halt_reg = 0x73008,
  1104. .halt_check = BRANCH_HALT,
  1105. .clkr = {
  1106. .enable_reg = 0x73008,
  1107. .enable_mask = BIT(0),
  1108. .hw.init = &(struct clk_init_data){
  1109. .name = "gcc_npu_bwmon_axi_clk",
  1110. .ops = &clk_branch2_ops,
  1111. },
  1112. },
  1113. };
  1114. static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
  1115. .halt_reg = 0x73018,
  1116. .halt_check = BRANCH_HALT,
  1117. .clkr = {
  1118. .enable_reg = 0x73018,
  1119. .enable_mask = BIT(0),
  1120. .hw.init = &(struct clk_init_data){
  1121. .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
  1122. .ops = &clk_branch2_ops,
  1123. },
  1124. },
  1125. };
  1126. static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
  1127. .halt_reg = 0x7301c,
  1128. .halt_check = BRANCH_HALT,
  1129. .clkr = {
  1130. .enable_reg = 0x7301c,
  1131. .enable_mask = BIT(0),
  1132. .hw.init = &(struct clk_init_data){
  1133. .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
  1134. .ops = &clk_branch2_ops,
  1135. },
  1136. },
  1137. };
  1138. static struct clk_branch gcc_npu_cfg_ahb_clk = {
  1139. .halt_reg = 0x4d004,
  1140. .halt_check = BRANCH_HALT,
  1141. .hwcg_reg = 0x4d004,
  1142. .hwcg_bit = 1,
  1143. .clkr = {
  1144. .enable_reg = 0x4d004,
  1145. .enable_mask = BIT(0),
  1146. .hw.init = &(struct clk_init_data){
  1147. .name = "gcc_npu_cfg_ahb_clk",
  1148. .ops = &clk_branch2_ops,
  1149. },
  1150. },
  1151. };
  1152. static struct clk_branch gcc_npu_dma_clk = {
  1153. .halt_reg = 0x4d1a0,
  1154. .halt_check = BRANCH_HALT,
  1155. .hwcg_reg = 0x4d1a0,
  1156. .hwcg_bit = 1,
  1157. .clkr = {
  1158. .enable_reg = 0x4d1a0,
  1159. .enable_mask = BIT(0),
  1160. .hw.init = &(struct clk_init_data){
  1161. .name = "gcc_npu_dma_clk",
  1162. .ops = &clk_branch2_ops,
  1163. },
  1164. },
  1165. };
  1166. static struct clk_branch gcc_npu_gpll0_clk_src = {
  1167. .halt_check = BRANCH_HALT_DELAY,
  1168. .clkr = {
  1169. .enable_reg = 0x52000,
  1170. .enable_mask = BIT(25),
  1171. .hw.init = &(struct clk_init_data){
  1172. .name = "gcc_npu_gpll0_clk_src",
  1173. .parent_hws = (const struct clk_hw*[]){
  1174. &gpll0.clkr.hw,
  1175. },
  1176. .num_parents = 1,
  1177. .ops = &clk_branch2_ops,
  1178. },
  1179. },
  1180. };
  1181. static struct clk_branch gcc_npu_gpll0_div_clk_src = {
  1182. .halt_check = BRANCH_HALT_DELAY,
  1183. .clkr = {
  1184. .enable_reg = 0x52000,
  1185. .enable_mask = BIT(26),
  1186. .hw.init = &(struct clk_init_data){
  1187. .name = "gcc_npu_gpll0_div_clk_src",
  1188. .parent_hws = (const struct clk_hw*[]){
  1189. &gcc_pll0_main_div_cdiv.hw,
  1190. },
  1191. .num_parents = 1,
  1192. .flags = CLK_SET_RATE_PARENT,
  1193. .ops = &clk_branch2_ops,
  1194. },
  1195. },
  1196. };
  1197. static struct clk_branch gcc_pdm2_clk = {
  1198. .halt_reg = 0x3300c,
  1199. .halt_check = BRANCH_HALT,
  1200. .clkr = {
  1201. .enable_reg = 0x3300c,
  1202. .enable_mask = BIT(0),
  1203. .hw.init = &(struct clk_init_data){
  1204. .name = "gcc_pdm2_clk",
  1205. .parent_hws = (const struct clk_hw*[]){
  1206. &gcc_pdm2_clk_src.clkr.hw,
  1207. },
  1208. .num_parents = 1,
  1209. .flags = CLK_SET_RATE_PARENT,
  1210. .ops = &clk_branch2_ops,
  1211. },
  1212. },
  1213. };
  1214. static struct clk_branch gcc_pdm_ahb_clk = {
  1215. .halt_reg = 0x33004,
  1216. .halt_check = BRANCH_HALT,
  1217. .hwcg_reg = 0x33004,
  1218. .hwcg_bit = 1,
  1219. .clkr = {
  1220. .enable_reg = 0x33004,
  1221. .enable_mask = BIT(0),
  1222. .hw.init = &(struct clk_init_data){
  1223. .name = "gcc_pdm_ahb_clk",
  1224. .ops = &clk_branch2_ops,
  1225. },
  1226. },
  1227. };
  1228. static struct clk_branch gcc_pdm_xo4_clk = {
  1229. .halt_reg = 0x33008,
  1230. .halt_check = BRANCH_HALT,
  1231. .clkr = {
  1232. .enable_reg = 0x33008,
  1233. .enable_mask = BIT(0),
  1234. .hw.init = &(struct clk_init_data){
  1235. .name = "gcc_pdm_xo4_clk",
  1236. .ops = &clk_branch2_ops,
  1237. },
  1238. },
  1239. };
  1240. static struct clk_branch gcc_prng_ahb_clk = {
  1241. .halt_reg = 0x34004,
  1242. .halt_check = BRANCH_HALT_VOTED,
  1243. .hwcg_reg = 0x34004,
  1244. .hwcg_bit = 1,
  1245. .clkr = {
  1246. .enable_reg = 0x52000,
  1247. .enable_mask = BIT(13),
  1248. .hw.init = &(struct clk_init_data){
  1249. .name = "gcc_prng_ahb_clk",
  1250. .ops = &clk_branch2_ops,
  1251. },
  1252. },
  1253. };
  1254. static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
  1255. .halt_reg = 0x4b004,
  1256. .halt_check = BRANCH_HALT,
  1257. .hwcg_reg = 0x4b004,
  1258. .hwcg_bit = 1,
  1259. .clkr = {
  1260. .enable_reg = 0x4b004,
  1261. .enable_mask = BIT(0),
  1262. .hw.init = &(struct clk_init_data){
  1263. .name = "gcc_qspi_cnoc_periph_ahb_clk",
  1264. .ops = &clk_branch2_ops,
  1265. },
  1266. },
  1267. };
  1268. static struct clk_branch gcc_qspi_core_clk = {
  1269. .halt_reg = 0x4b008,
  1270. .halt_check = BRANCH_HALT,
  1271. .clkr = {
  1272. .enable_reg = 0x4b008,
  1273. .enable_mask = BIT(0),
  1274. .hw.init = &(struct clk_init_data){
  1275. .name = "gcc_qspi_core_clk",
  1276. .parent_hws = (const struct clk_hw*[]){
  1277. &gcc_qspi_core_clk_src.clkr.hw,
  1278. },
  1279. .num_parents = 1,
  1280. .flags = CLK_SET_RATE_PARENT,
  1281. .ops = &clk_branch2_ops,
  1282. },
  1283. },
  1284. };
  1285. static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
  1286. .halt_reg = 0x17014,
  1287. .halt_check = BRANCH_HALT_VOTED,
  1288. .clkr = {
  1289. .enable_reg = 0x52008,
  1290. .enable_mask = BIT(9),
  1291. .hw.init = &(struct clk_init_data){
  1292. .name = "gcc_qupv3_wrap0_core_2x_clk",
  1293. .ops = &clk_branch2_ops,
  1294. },
  1295. },
  1296. };
  1297. static struct clk_branch gcc_qupv3_wrap0_core_clk = {
  1298. .halt_reg = 0x1700c,
  1299. .halt_check = BRANCH_HALT_VOTED,
  1300. .clkr = {
  1301. .enable_reg = 0x52008,
  1302. .enable_mask = BIT(8),
  1303. .hw.init = &(struct clk_init_data){
  1304. .name = "gcc_qupv3_wrap0_core_clk",
  1305. .ops = &clk_branch2_ops,
  1306. },
  1307. },
  1308. };
  1309. static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
  1310. .halt_reg = 0x17030,
  1311. .halt_check = BRANCH_HALT_VOTED,
  1312. .clkr = {
  1313. .enable_reg = 0x52008,
  1314. .enable_mask = BIT(10),
  1315. .hw.init = &(struct clk_init_data){
  1316. .name = "gcc_qupv3_wrap0_s0_clk",
  1317. .parent_hws = (const struct clk_hw*[]){
  1318. &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
  1319. },
  1320. .num_parents = 1,
  1321. .flags = CLK_SET_RATE_PARENT,
  1322. .ops = &clk_branch2_ops,
  1323. },
  1324. },
  1325. };
  1326. static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
  1327. .halt_reg = 0x17160,
  1328. .halt_check = BRANCH_HALT_VOTED,
  1329. .clkr = {
  1330. .enable_reg = 0x52008,
  1331. .enable_mask = BIT(11),
  1332. .hw.init = &(struct clk_init_data){
  1333. .name = "gcc_qupv3_wrap0_s1_clk",
  1334. .parent_hws = (const struct clk_hw*[]){
  1335. &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
  1336. },
  1337. .num_parents = 1,
  1338. .flags = CLK_SET_RATE_PARENT,
  1339. .ops = &clk_branch2_ops,
  1340. },
  1341. },
  1342. };
  1343. static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
  1344. .halt_reg = 0x17290,
  1345. .halt_check = BRANCH_HALT_VOTED,
  1346. .clkr = {
  1347. .enable_reg = 0x52008,
  1348. .enable_mask = BIT(12),
  1349. .hw.init = &(struct clk_init_data){
  1350. .name = "gcc_qupv3_wrap0_s2_clk",
  1351. .parent_hws = (const struct clk_hw*[]){
  1352. &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
  1353. },
  1354. .num_parents = 1,
  1355. .flags = CLK_SET_RATE_PARENT,
  1356. .ops = &clk_branch2_ops,
  1357. },
  1358. },
  1359. };
  1360. static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
  1361. .halt_reg = 0x173c0,
  1362. .halt_check = BRANCH_HALT_VOTED,
  1363. .clkr = {
  1364. .enable_reg = 0x52008,
  1365. .enable_mask = BIT(13),
  1366. .hw.init = &(struct clk_init_data){
  1367. .name = "gcc_qupv3_wrap0_s3_clk",
  1368. .parent_hws = (const struct clk_hw*[]){
  1369. &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
  1370. },
  1371. .num_parents = 1,
  1372. .flags = CLK_SET_RATE_PARENT,
  1373. .ops = &clk_branch2_ops,
  1374. },
  1375. },
  1376. };
  1377. static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
  1378. .halt_reg = 0x174f0,
  1379. .halt_check = BRANCH_HALT_VOTED,
  1380. .clkr = {
  1381. .enable_reg = 0x52008,
  1382. .enable_mask = BIT(14),
  1383. .hw.init = &(struct clk_init_data){
  1384. .name = "gcc_qupv3_wrap0_s4_clk",
  1385. .parent_hws = (const struct clk_hw*[]){
  1386. &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
  1387. },
  1388. .num_parents = 1,
  1389. .flags = CLK_SET_RATE_PARENT,
  1390. .ops = &clk_branch2_ops,
  1391. },
  1392. },
  1393. };
  1394. static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
  1395. .halt_reg = 0x17620,
  1396. .halt_check = BRANCH_HALT_VOTED,
  1397. .clkr = {
  1398. .enable_reg = 0x52008,
  1399. .enable_mask = BIT(15),
  1400. .hw.init = &(struct clk_init_data){
  1401. .name = "gcc_qupv3_wrap0_s5_clk",
  1402. .parent_hws = (const struct clk_hw*[]){
  1403. &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
  1404. },
  1405. .num_parents = 1,
  1406. .flags = CLK_SET_RATE_PARENT,
  1407. .ops = &clk_branch2_ops,
  1408. },
  1409. },
  1410. };
  1411. static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
  1412. .halt_reg = 0x18004,
  1413. .halt_check = BRANCH_HALT_VOTED,
  1414. .clkr = {
  1415. .enable_reg = 0x52008,
  1416. .enable_mask = BIT(18),
  1417. .hw.init = &(struct clk_init_data){
  1418. .name = "gcc_qupv3_wrap1_core_2x_clk",
  1419. .ops = &clk_branch2_ops,
  1420. },
  1421. },
  1422. };
  1423. static struct clk_branch gcc_qupv3_wrap1_core_clk = {
  1424. .halt_reg = 0x18008,
  1425. .halt_check = BRANCH_HALT_VOTED,
  1426. .clkr = {
  1427. .enable_reg = 0x52008,
  1428. .enable_mask = BIT(19),
  1429. .hw.init = &(struct clk_init_data){
  1430. .name = "gcc_qupv3_wrap1_core_clk",
  1431. .ops = &clk_branch2_ops,
  1432. },
  1433. },
  1434. };
  1435. static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
  1436. .halt_reg = 0x18014,
  1437. .halt_check = BRANCH_HALT_VOTED,
  1438. .clkr = {
  1439. .enable_reg = 0x52008,
  1440. .enable_mask = BIT(22),
  1441. .hw.init = &(struct clk_init_data){
  1442. .name = "gcc_qupv3_wrap1_s0_clk",
  1443. .parent_hws = (const struct clk_hw*[]){
  1444. &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
  1445. },
  1446. .num_parents = 1,
  1447. .flags = CLK_SET_RATE_PARENT,
  1448. .ops = &clk_branch2_ops,
  1449. },
  1450. },
  1451. };
  1452. static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
  1453. .halt_reg = 0x18144,
  1454. .halt_check = BRANCH_HALT_VOTED,
  1455. .clkr = {
  1456. .enable_reg = 0x52008,
  1457. .enable_mask = BIT(23),
  1458. .hw.init = &(struct clk_init_data){
  1459. .name = "gcc_qupv3_wrap1_s1_clk",
  1460. .parent_hws = (const struct clk_hw*[]){
  1461. &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
  1462. },
  1463. .num_parents = 1,
  1464. .flags = CLK_SET_RATE_PARENT,
  1465. .ops = &clk_branch2_ops,
  1466. },
  1467. },
  1468. };
  1469. static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
  1470. .halt_reg = 0x18274,
  1471. .halt_check = BRANCH_HALT_VOTED,
  1472. .clkr = {
  1473. .enable_reg = 0x52008,
  1474. .enable_mask = BIT(24),
  1475. .hw.init = &(struct clk_init_data){
  1476. .name = "gcc_qupv3_wrap1_s2_clk",
  1477. .parent_hws = (const struct clk_hw*[]){
  1478. &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
  1479. },
  1480. .num_parents = 1,
  1481. .flags = CLK_SET_RATE_PARENT,
  1482. .ops = &clk_branch2_ops,
  1483. },
  1484. },
  1485. };
  1486. static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
  1487. .halt_reg = 0x183a4,
  1488. .halt_check = BRANCH_HALT_VOTED,
  1489. .clkr = {
  1490. .enable_reg = 0x52008,
  1491. .enable_mask = BIT(25),
  1492. .hw.init = &(struct clk_init_data){
  1493. .name = "gcc_qupv3_wrap1_s3_clk",
  1494. .parent_hws = (const struct clk_hw*[]){
  1495. &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
  1496. },
  1497. .num_parents = 1,
  1498. .flags = CLK_SET_RATE_PARENT,
  1499. .ops = &clk_branch2_ops,
  1500. },
  1501. },
  1502. };
  1503. static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
  1504. .halt_reg = 0x184d4,
  1505. .halt_check = BRANCH_HALT_VOTED,
  1506. .clkr = {
  1507. .enable_reg = 0x52008,
  1508. .enable_mask = BIT(26),
  1509. .hw.init = &(struct clk_init_data){
  1510. .name = "gcc_qupv3_wrap1_s4_clk",
  1511. .parent_hws = (const struct clk_hw*[]){
  1512. &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
  1513. },
  1514. .num_parents = 1,
  1515. .flags = CLK_SET_RATE_PARENT,
  1516. .ops = &clk_branch2_ops,
  1517. },
  1518. },
  1519. };
  1520. static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
  1521. .halt_reg = 0x18604,
  1522. .halt_check = BRANCH_HALT_VOTED,
  1523. .clkr = {
  1524. .enable_reg = 0x52008,
  1525. .enable_mask = BIT(27),
  1526. .hw.init = &(struct clk_init_data){
  1527. .name = "gcc_qupv3_wrap1_s5_clk",
  1528. .parent_hws = (const struct clk_hw*[]){
  1529. &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
  1530. },
  1531. .num_parents = 1,
  1532. .flags = CLK_SET_RATE_PARENT,
  1533. .ops = &clk_branch2_ops,
  1534. },
  1535. },
  1536. };
  1537. static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
  1538. .halt_reg = 0x17004,
  1539. .halt_check = BRANCH_HALT_VOTED,
  1540. .clkr = {
  1541. .enable_reg = 0x52008,
  1542. .enable_mask = BIT(6),
  1543. .hw.init = &(struct clk_init_data){
  1544. .name = "gcc_qupv3_wrap_0_m_ahb_clk",
  1545. .ops = &clk_branch2_ops,
  1546. },
  1547. },
  1548. };
  1549. static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
  1550. .halt_reg = 0x17008,
  1551. .halt_check = BRANCH_HALT_VOTED,
  1552. .hwcg_reg = 0x17008,
  1553. .hwcg_bit = 1,
  1554. .clkr = {
  1555. .enable_reg = 0x52008,
  1556. .enable_mask = BIT(7),
  1557. .hw.init = &(struct clk_init_data){
  1558. .name = "gcc_qupv3_wrap_0_s_ahb_clk",
  1559. .ops = &clk_branch2_ops,
  1560. },
  1561. },
  1562. };
  1563. static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
  1564. .halt_reg = 0x1800c,
  1565. .halt_check = BRANCH_HALT_VOTED,
  1566. .clkr = {
  1567. .enable_reg = 0x52008,
  1568. .enable_mask = BIT(20),
  1569. .hw.init = &(struct clk_init_data){
  1570. .name = "gcc_qupv3_wrap_1_m_ahb_clk",
  1571. .ops = &clk_branch2_ops,
  1572. },
  1573. },
  1574. };
  1575. static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
  1576. .halt_reg = 0x18010,
  1577. .halt_check = BRANCH_HALT_VOTED,
  1578. .hwcg_reg = 0x18010,
  1579. .hwcg_bit = 1,
  1580. .clkr = {
  1581. .enable_reg = 0x52008,
  1582. .enable_mask = BIT(21),
  1583. .hw.init = &(struct clk_init_data){
  1584. .name = "gcc_qupv3_wrap_1_s_ahb_clk",
  1585. .ops = &clk_branch2_ops,
  1586. },
  1587. },
  1588. };
  1589. static struct clk_branch gcc_sdcc1_ahb_clk = {
  1590. .halt_reg = 0x12008,
  1591. .halt_check = BRANCH_HALT,
  1592. .clkr = {
  1593. .enable_reg = 0x12008,
  1594. .enable_mask = BIT(0),
  1595. .hw.init = &(struct clk_init_data){
  1596. .name = "gcc_sdcc1_ahb_clk",
  1597. .ops = &clk_branch2_ops,
  1598. },
  1599. },
  1600. };
  1601. static struct clk_branch gcc_sdcc1_apps_clk = {
  1602. .halt_reg = 0x1200c,
  1603. .halt_check = BRANCH_HALT,
  1604. .clkr = {
  1605. .enable_reg = 0x1200c,
  1606. .enable_mask = BIT(0),
  1607. .hw.init = &(struct clk_init_data){
  1608. .name = "gcc_sdcc1_apps_clk",
  1609. .parent_hws = (const struct clk_hw*[]){
  1610. &gcc_sdcc1_apps_clk_src.clkr.hw,
  1611. },
  1612. .num_parents = 1,
  1613. .flags = CLK_SET_RATE_PARENT,
  1614. .ops = &clk_branch2_ops,
  1615. },
  1616. },
  1617. };
  1618. static struct clk_branch gcc_sdcc1_ice_core_clk = {
  1619. .halt_reg = 0x12040,
  1620. .halt_check = BRANCH_HALT,
  1621. .clkr = {
  1622. .enable_reg = 0x12040,
  1623. .enable_mask = BIT(0),
  1624. .hw.init = &(struct clk_init_data){
  1625. .name = "gcc_sdcc1_ice_core_clk",
  1626. .parent_hws = (const struct clk_hw*[]){
  1627. &gcc_sdcc1_ice_core_clk_src.clkr.hw,
  1628. },
  1629. .num_parents = 1,
  1630. .flags = CLK_SET_RATE_PARENT,
  1631. .ops = &clk_branch2_ops,
  1632. },
  1633. },
  1634. };
  1635. static struct clk_branch gcc_sdcc2_ahb_clk = {
  1636. .halt_reg = 0x14008,
  1637. .halt_check = BRANCH_HALT,
  1638. .clkr = {
  1639. .enable_reg = 0x14008,
  1640. .enable_mask = BIT(0),
  1641. .hw.init = &(struct clk_init_data){
  1642. .name = "gcc_sdcc2_ahb_clk",
  1643. .ops = &clk_branch2_ops,
  1644. },
  1645. },
  1646. };
  1647. static struct clk_branch gcc_sdcc2_apps_clk = {
  1648. .halt_reg = 0x14004,
  1649. .halt_check = BRANCH_HALT,
  1650. .clkr = {
  1651. .enable_reg = 0x14004,
  1652. .enable_mask = BIT(0),
  1653. .hw.init = &(struct clk_init_data){
  1654. .name = "gcc_sdcc2_apps_clk",
  1655. .parent_hws = (const struct clk_hw*[]){
  1656. &gcc_sdcc2_apps_clk_src.clkr.hw,
  1657. },
  1658. .num_parents = 1,
  1659. .flags = CLK_SET_RATE_PARENT,
  1660. .ops = &clk_branch2_ops,
  1661. },
  1662. },
  1663. };
  1664. /* For CPUSS functionality the SYS NOC clock needs to be left enabled */
  1665. static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
  1666. .halt_reg = 0x4144,
  1667. .halt_check = BRANCH_HALT_VOTED,
  1668. .clkr = {
  1669. .enable_reg = 0x52000,
  1670. .enable_mask = BIT(0),
  1671. .hw.init = &(struct clk_init_data){
  1672. .name = "gcc_sys_noc_cpuss_ahb_clk",
  1673. .parent_hws = (const struct clk_hw*[]){
  1674. &gcc_cpuss_ahb_clk_src.clkr.hw,
  1675. },
  1676. .num_parents = 1,
  1677. .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
  1678. .ops = &clk_branch2_ops,
  1679. },
  1680. },
  1681. };
  1682. static struct clk_branch gcc_ufs_mem_clkref_clk = {
  1683. .halt_reg = 0x8c000,
  1684. .halt_check = BRANCH_HALT,
  1685. .clkr = {
  1686. .enable_reg = 0x8c000,
  1687. .enable_mask = BIT(0),
  1688. .hw.init = &(struct clk_init_data){
  1689. .name = "gcc_ufs_mem_clkref_clk",
  1690. .ops = &clk_branch2_ops,
  1691. },
  1692. },
  1693. };
  1694. static struct clk_branch gcc_ufs_phy_ahb_clk = {
  1695. .halt_reg = 0x77014,
  1696. .halt_check = BRANCH_HALT,
  1697. .hwcg_reg = 0x77014,
  1698. .hwcg_bit = 1,
  1699. .clkr = {
  1700. .enable_reg = 0x77014,
  1701. .enable_mask = BIT(0),
  1702. .hw.init = &(struct clk_init_data){
  1703. .name = "gcc_ufs_phy_ahb_clk",
  1704. .ops = &clk_branch2_ops,
  1705. },
  1706. },
  1707. };
  1708. static struct clk_branch gcc_ufs_phy_axi_clk = {
  1709. .halt_reg = 0x77038,
  1710. .halt_check = BRANCH_HALT,
  1711. .hwcg_reg = 0x77038,
  1712. .hwcg_bit = 1,
  1713. .clkr = {
  1714. .enable_reg = 0x77038,
  1715. .enable_mask = BIT(0),
  1716. .hw.init = &(struct clk_init_data){
  1717. .name = "gcc_ufs_phy_axi_clk",
  1718. .parent_hws = (const struct clk_hw*[]){
  1719. &gcc_ufs_phy_axi_clk_src.clkr.hw,
  1720. },
  1721. .num_parents = 1,
  1722. .flags = CLK_SET_RATE_PARENT,
  1723. .ops = &clk_branch2_ops,
  1724. },
  1725. },
  1726. };
  1727. static struct clk_branch gcc_ufs_phy_ice_core_clk = {
  1728. .halt_reg = 0x77090,
  1729. .halt_check = BRANCH_HALT,
  1730. .hwcg_reg = 0x77090,
  1731. .hwcg_bit = 1,
  1732. .clkr = {
  1733. .enable_reg = 0x77090,
  1734. .enable_mask = BIT(0),
  1735. .hw.init = &(struct clk_init_data){
  1736. .name = "gcc_ufs_phy_ice_core_clk",
  1737. .parent_hws = (const struct clk_hw*[]){
  1738. &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
  1739. },
  1740. .num_parents = 1,
  1741. .flags = CLK_SET_RATE_PARENT,
  1742. .ops = &clk_branch2_ops,
  1743. },
  1744. },
  1745. };
  1746. static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
  1747. .halt_reg = 0x77094,
  1748. .halt_check = BRANCH_HALT,
  1749. .hwcg_reg = 0x77094,
  1750. .hwcg_bit = 1,
  1751. .clkr = {
  1752. .enable_reg = 0x77094,
  1753. .enable_mask = BIT(0),
  1754. .hw.init = &(struct clk_init_data){
  1755. .name = "gcc_ufs_phy_phy_aux_clk",
  1756. .parent_hws = (const struct clk_hw*[]){
  1757. &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
  1758. },
  1759. .num_parents = 1,
  1760. .flags = CLK_SET_RATE_PARENT,
  1761. .ops = &clk_branch2_ops,
  1762. },
  1763. },
  1764. };
  1765. static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
  1766. .halt_reg = 0x7701c,
  1767. .halt_check = BRANCH_HALT_SKIP,
  1768. .clkr = {
  1769. .enable_reg = 0x7701c,
  1770. .enable_mask = BIT(0),
  1771. .hw.init = &(struct clk_init_data){
  1772. .name = "gcc_ufs_phy_rx_symbol_0_clk",
  1773. .ops = &clk_branch2_ops,
  1774. },
  1775. },
  1776. };
  1777. static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
  1778. .halt_reg = 0x77018,
  1779. .halt_check = BRANCH_HALT_SKIP,
  1780. .clkr = {
  1781. .enable_reg = 0x77018,
  1782. .enable_mask = BIT(0),
  1783. .hw.init = &(struct clk_init_data){
  1784. .name = "gcc_ufs_phy_tx_symbol_0_clk",
  1785. .ops = &clk_branch2_ops,
  1786. },
  1787. },
  1788. };
  1789. static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
  1790. .halt_reg = 0x7708c,
  1791. .halt_check = BRANCH_HALT,
  1792. .hwcg_reg = 0x7708c,
  1793. .hwcg_bit = 1,
  1794. .clkr = {
  1795. .enable_reg = 0x7708c,
  1796. .enable_mask = BIT(0),
  1797. .hw.init = &(struct clk_init_data){
  1798. .name = "gcc_ufs_phy_unipro_core_clk",
  1799. .parent_hws = (const struct clk_hw*[]){
  1800. &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
  1801. },
  1802. .num_parents = 1,
  1803. .flags = CLK_SET_RATE_PARENT,
  1804. .ops = &clk_branch2_ops,
  1805. },
  1806. },
  1807. };
  1808. static struct clk_branch gcc_usb30_prim_master_clk = {
  1809. .halt_reg = 0xf010,
  1810. .halt_check = BRANCH_HALT,
  1811. .clkr = {
  1812. .enable_reg = 0xf010,
  1813. .enable_mask = BIT(0),
  1814. .hw.init = &(struct clk_init_data){
  1815. .name = "gcc_usb30_prim_master_clk",
  1816. .parent_hws = (const struct clk_hw*[]){
  1817. &gcc_usb30_prim_master_clk_src.clkr.hw,
  1818. },
  1819. .num_parents = 1,
  1820. .flags = CLK_SET_RATE_PARENT,
  1821. .ops = &clk_branch2_ops,
  1822. },
  1823. },
  1824. };
  1825. static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
  1826. .halt_reg = 0xf018,
  1827. .halt_check = BRANCH_HALT,
  1828. .clkr = {
  1829. .enable_reg = 0xf018,
  1830. .enable_mask = BIT(0),
  1831. .hw.init = &(struct clk_init_data){
  1832. .name = "gcc_usb30_prim_mock_utmi_clk",
  1833. .parent_data = &(const struct clk_parent_data){
  1834. .hw =
  1835. &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
  1836. },
  1837. .num_parents = 1,
  1838. .flags = CLK_SET_RATE_PARENT,
  1839. .ops = &clk_branch2_ops,
  1840. },
  1841. },
  1842. };
  1843. static struct clk_branch gcc_usb30_prim_sleep_clk = {
  1844. .halt_reg = 0xf014,
  1845. .halt_check = BRANCH_HALT,
  1846. .clkr = {
  1847. .enable_reg = 0xf014,
  1848. .enable_mask = BIT(0),
  1849. .hw.init = &(struct clk_init_data){
  1850. .name = "gcc_usb30_prim_sleep_clk",
  1851. .ops = &clk_branch2_ops,
  1852. },
  1853. },
  1854. };
  1855. static struct clk_branch gcc_usb3_prim_clkref_clk = {
  1856. .halt_reg = 0x8c010,
  1857. .halt_check = BRANCH_HALT,
  1858. .clkr = {
  1859. .enable_reg = 0x8c010,
  1860. .enable_mask = BIT(0),
  1861. .hw.init = &(struct clk_init_data){
  1862. .name = "gcc_usb3_prim_clkref_clk",
  1863. .ops = &clk_branch2_ops,
  1864. },
  1865. },
  1866. };
  1867. static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
  1868. .halt_reg = 0xf050,
  1869. .halt_check = BRANCH_HALT,
  1870. .clkr = {
  1871. .enable_reg = 0xf050,
  1872. .enable_mask = BIT(0),
  1873. .hw.init = &(struct clk_init_data){
  1874. .name = "gcc_usb3_prim_phy_aux_clk",
  1875. .parent_hws = (const struct clk_hw*[]){
  1876. &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
  1877. },
  1878. .num_parents = 1,
  1879. .flags = CLK_SET_RATE_PARENT,
  1880. .ops = &clk_branch2_ops,
  1881. },
  1882. },
  1883. };
  1884. static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
  1885. .halt_reg = 0xf054,
  1886. .halt_check = BRANCH_HALT,
  1887. .clkr = {
  1888. .enable_reg = 0xf054,
  1889. .enable_mask = BIT(0),
  1890. .hw.init = &(struct clk_init_data){
  1891. .name = "gcc_usb3_prim_phy_com_aux_clk",
  1892. .parent_hws = (const struct clk_hw*[]){
  1893. &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
  1894. },
  1895. .num_parents = 1,
  1896. .flags = CLK_SET_RATE_PARENT,
  1897. .ops = &clk_branch2_ops,
  1898. },
  1899. },
  1900. };
  1901. static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
  1902. .halt_reg = 0xf058,
  1903. .halt_check = BRANCH_HALT_SKIP,
  1904. .clkr = {
  1905. .enable_reg = 0xf058,
  1906. .enable_mask = BIT(0),
  1907. .hw.init = &(struct clk_init_data){
  1908. .name = "gcc_usb3_prim_phy_pipe_clk",
  1909. .ops = &clk_branch2_ops,
  1910. },
  1911. },
  1912. };
  1913. static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
  1914. .halt_reg = 0x6a004,
  1915. .halt_check = BRANCH_HALT,
  1916. .hwcg_reg = 0x6a004,
  1917. .hwcg_bit = 1,
  1918. .clkr = {
  1919. .enable_reg = 0x6a004,
  1920. .enable_mask = BIT(0),
  1921. .hw.init = &(struct clk_init_data){
  1922. .name = "gcc_usb_phy_cfg_ahb2phy_clk",
  1923. .ops = &clk_branch2_ops,
  1924. },
  1925. },
  1926. };
  1927. static struct clk_branch gcc_video_axi_clk = {
  1928. .halt_reg = 0xb01c,
  1929. .halt_check = BRANCH_HALT,
  1930. .clkr = {
  1931. .enable_reg = 0xb01c,
  1932. .enable_mask = BIT(0),
  1933. .hw.init = &(struct clk_init_data){
  1934. .name = "gcc_video_axi_clk",
  1935. .ops = &clk_branch2_ops,
  1936. },
  1937. },
  1938. };
  1939. static struct clk_branch gcc_video_gpll0_div_clk_src = {
  1940. .halt_check = BRANCH_HALT_DELAY,
  1941. .clkr = {
  1942. .enable_reg = 0x52000,
  1943. .enable_mask = BIT(20),
  1944. .hw.init = &(struct clk_init_data){
  1945. .name = "gcc_video_gpll0_div_clk_src",
  1946. .parent_hws = (const struct clk_hw*[]){
  1947. &gcc_pll0_main_div_cdiv.hw,
  1948. },
  1949. .num_parents = 1,
  1950. .flags = CLK_SET_RATE_PARENT,
  1951. .ops = &clk_branch2_ops,
  1952. },
  1953. },
  1954. };
  1955. static struct clk_branch gcc_video_throttle_axi_clk = {
  1956. .halt_reg = 0xb07c,
  1957. .halt_check = BRANCH_HALT,
  1958. .hwcg_reg = 0xb07c,
  1959. .hwcg_bit = 1,
  1960. .clkr = {
  1961. .enable_reg = 0xb07c,
  1962. .enable_mask = BIT(0),
  1963. .hw.init = &(struct clk_init_data){
  1964. .name = "gcc_video_throttle_axi_clk",
  1965. .ops = &clk_branch2_ops,
  1966. },
  1967. },
  1968. };
  1969. static struct clk_branch gcc_mss_cfg_ahb_clk = {
  1970. .halt_reg = 0x8a000,
  1971. .halt_check = BRANCH_HALT,
  1972. .clkr = {
  1973. .enable_reg = 0x8a000,
  1974. .enable_mask = BIT(0),
  1975. .hw.init = &(struct clk_init_data){
  1976. .name = "gcc_mss_cfg_ahb_clk",
  1977. .ops = &clk_branch2_ops,
  1978. },
  1979. },
  1980. };
  1981. static struct clk_branch gcc_mss_mfab_axis_clk = {
  1982. .halt_reg = 0x8a004,
  1983. .halt_check = BRANCH_HALT_VOTED,
  1984. .clkr = {
  1985. .enable_reg = 0x8a004,
  1986. .enable_mask = BIT(0),
  1987. .hw.init = &(struct clk_init_data){
  1988. .name = "gcc_mss_mfab_axis_clk",
  1989. .ops = &clk_branch2_ops,
  1990. },
  1991. },
  1992. };
  1993. static struct clk_branch gcc_mss_nav_axi_clk = {
  1994. .halt_reg = 0x8a00c,
  1995. .halt_check = BRANCH_HALT_VOTED,
  1996. .clkr = {
  1997. .enable_reg = 0x8a00c,
  1998. .enable_mask = BIT(0),
  1999. .hw.init = &(struct clk_init_data){
  2000. .name = "gcc_mss_nav_axi_clk",
  2001. .ops = &clk_branch2_ops,
  2002. },
  2003. },
  2004. };
  2005. static struct clk_branch gcc_mss_snoc_axi_clk = {
  2006. .halt_reg = 0x8a150,
  2007. .halt_check = BRANCH_HALT,
  2008. .clkr = {
  2009. .enable_reg = 0x8a150,
  2010. .enable_mask = BIT(0),
  2011. .hw.init = &(struct clk_init_data){
  2012. .name = "gcc_mss_snoc_axi_clk",
  2013. .ops = &clk_branch2_ops,
  2014. },
  2015. },
  2016. };
  2017. static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
  2018. .halt_reg = 0x8a154,
  2019. .halt_check = BRANCH_HALT,
  2020. .clkr = {
  2021. .enable_reg = 0x8a154,
  2022. .enable_mask = BIT(0),
  2023. .hw.init = &(struct clk_init_data){
  2024. .name = "gcc_mss_q6_memnoc_axi_clk",
  2025. .ops = &clk_branch2_ops,
  2026. },
  2027. },
  2028. };
  2029. static struct clk_branch gcc_lpass_cfg_noc_sway_clk = {
  2030. .halt_reg = 0x47018,
  2031. .halt_check = BRANCH_HALT_DELAY,
  2032. .clkr = {
  2033. .enable_reg = 0x47018,
  2034. .enable_mask = BIT(0),
  2035. .hw.init = &(struct clk_init_data){
  2036. .name = "gcc_lpass_cfg_noc_sway_clk",
  2037. .ops = &clk_branch2_ops,
  2038. },
  2039. },
  2040. };
  2041. static struct gdsc ufs_phy_gdsc = {
  2042. .gdscr = 0x77004,
  2043. .pd = {
  2044. .name = "ufs_phy_gdsc",
  2045. },
  2046. .pwrsts = PWRSTS_OFF_ON,
  2047. };
  2048. static struct gdsc usb30_prim_gdsc = {
  2049. .gdscr = 0x0f004,
  2050. .pd = {
  2051. .name = "usb30_prim_gdsc",
  2052. },
  2053. .pwrsts = PWRSTS_RET_ON,
  2054. };
  2055. static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
  2056. .gdscr = 0x7d040,
  2057. .pd = {
  2058. .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
  2059. },
  2060. .pwrsts = PWRSTS_OFF_ON,
  2061. .flags = VOTABLE,
  2062. };
  2063. static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
  2064. .gdscr = 0x7d044,
  2065. .pd = {
  2066. .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
  2067. },
  2068. .pwrsts = PWRSTS_OFF_ON,
  2069. .flags = VOTABLE,
  2070. };
  2071. static struct gdsc *gcc_sc7180_gdscs[] = {
  2072. [UFS_PHY_GDSC] = &ufs_phy_gdsc,
  2073. [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
  2074. [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
  2075. &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
  2076. [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] =
  2077. &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
  2078. };
  2079. static struct clk_hw *gcc_sc7180_hws[] = {
  2080. [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw,
  2081. };
  2082. static struct clk_regmap *gcc_sc7180_clocks[] = {
  2083. [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
  2084. [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
  2085. [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
  2086. [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
  2087. [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr,
  2088. [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
  2089. [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
  2090. [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
  2091. [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
  2092. [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
  2093. [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
  2094. [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
  2095. [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
  2096. [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
  2097. [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
  2098. [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
  2099. [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr,
  2100. [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
  2101. [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
  2102. [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
  2103. [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
  2104. [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
  2105. [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
  2106. [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
  2107. [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
  2108. [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
  2109. [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
  2110. [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
  2111. [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
  2112. [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
  2113. [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
  2114. [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
  2115. [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
  2116. [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
  2117. [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
  2118. [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
  2119. [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
  2120. [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
  2121. [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
  2122. [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
  2123. [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
  2124. [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
  2125. [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
  2126. [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
  2127. [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
  2128. [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
  2129. [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
  2130. [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
  2131. [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
  2132. [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
  2133. [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
  2134. [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
  2135. [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
  2136. [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
  2137. [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
  2138. [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
  2139. [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
  2140. [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
  2141. [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
  2142. [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
  2143. [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
  2144. [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
  2145. [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
  2146. [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
  2147. [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
  2148. [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
  2149. [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
  2150. [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
  2151. [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
  2152. [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
  2153. [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
  2154. [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
  2155. [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
  2156. [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
  2157. [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
  2158. [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
  2159. [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
  2160. [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
  2161. [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
  2162. [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
  2163. [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
  2164. [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
  2165. [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
  2166. [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
  2167. [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
  2168. [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
  2169. [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
  2170. [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
  2171. [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
  2172. [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
  2173. [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
  2174. [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
  2175. [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
  2176. [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
  2177. [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
  2178. [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
  2179. &gcc_ufs_phy_unipro_core_clk_src.clkr,
  2180. [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
  2181. [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
  2182. [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
  2183. [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
  2184. &gcc_usb30_prim_mock_utmi_clk_src.clkr,
  2185. [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
  2186. [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
  2187. [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
  2188. [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
  2189. [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
  2190. [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
  2191. [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
  2192. [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
  2193. [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr,
  2194. [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
  2195. [GPLL0] = &gpll0.clkr,
  2196. [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
  2197. [GPLL6] = &gpll6.clkr,
  2198. [GPLL7] = &gpll7.clkr,
  2199. [GPLL4] = &gpll4.clkr,
  2200. [GPLL1] = &gpll1.clkr,
  2201. [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
  2202. [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
  2203. [GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr,
  2204. [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
  2205. [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
  2206. [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
  2207. [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr,
  2208. };
  2209. static const struct qcom_reset_map gcc_sc7180_resets[] = {
  2210. [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
  2211. [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
  2212. [GCC_UFS_PHY_BCR] = { 0x77000 },
  2213. [GCC_USB30_PRIM_BCR] = { 0xf000 },
  2214. [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
  2215. [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
  2216. [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
  2217. [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
  2218. [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
  2219. [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
  2220. [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
  2221. };
  2222. static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
  2223. DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
  2224. DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
  2225. DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
  2226. DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
  2227. DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
  2228. DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
  2229. DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
  2230. DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
  2231. DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
  2232. DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
  2233. DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
  2234. DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
  2235. };
  2236. static const struct regmap_config gcc_sc7180_regmap_config = {
  2237. .reg_bits = 32,
  2238. .reg_stride = 4,
  2239. .val_bits = 32,
  2240. .max_register = 0x18208c,
  2241. .fast_io = true,
  2242. };
  2243. static const struct qcom_cc_desc gcc_sc7180_desc = {
  2244. .config = &gcc_sc7180_regmap_config,
  2245. .clk_hws = gcc_sc7180_hws,
  2246. .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
  2247. .clks = gcc_sc7180_clocks,
  2248. .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
  2249. .resets = gcc_sc7180_resets,
  2250. .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
  2251. .gdscs = gcc_sc7180_gdscs,
  2252. .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
  2253. };
  2254. static const struct of_device_id gcc_sc7180_match_table[] = {
  2255. { .compatible = "qcom,gcc-sc7180" },
  2256. { }
  2257. };
  2258. MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
  2259. static int gcc_sc7180_probe(struct platform_device *pdev)
  2260. {
  2261. struct regmap *regmap;
  2262. int ret;
  2263. regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
  2264. if (IS_ERR(regmap))
  2265. return PTR_ERR(regmap);
  2266. /*
  2267. * Disable the GPLL0 active input to MM blocks, NPU
  2268. * and GPU via MISC registers.
  2269. */
  2270. regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
  2271. regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
  2272. regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
  2273. /*
  2274. * Keep the clocks always-ON
  2275. * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK,
  2276. * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK
  2277. */
  2278. regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
  2279. regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
  2280. regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
  2281. regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
  2282. regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0));
  2283. regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0));
  2284. regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0));
  2285. regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
  2286. ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
  2287. ARRAY_SIZE(gcc_dfs_clocks));
  2288. if (ret)
  2289. return ret;
  2290. return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
  2291. }
  2292. static struct platform_driver gcc_sc7180_driver = {
  2293. .probe = gcc_sc7180_probe,
  2294. .driver = {
  2295. .name = "gcc-sc7180",
  2296. .of_match_table = gcc_sc7180_match_table,
  2297. },
  2298. };
  2299. static int __init gcc_sc7180_init(void)
  2300. {
  2301. return platform_driver_register(&gcc_sc7180_driver);
  2302. }
  2303. core_initcall(gcc_sc7180_init);
  2304. static void __exit gcc_sc7180_exit(void)
  2305. {
  2306. platform_driver_unregister(&gcc_sc7180_driver);
  2307. }
  2308. module_exit(gcc_sc7180_exit);
  2309. MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
  2310. MODULE_LICENSE("GPL v2");