123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648 |
- // SPDX-License-Identifier: GPL-2.0-only
- /*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
- */
- #include <linux/kernel.h>
- #include <linux/bitops.h>
- #include <linux/err.h>
- #include <linux/platform_device.h>
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
- #include <linux/clk-provider.h>
- #include <linux/regmap.h>
- #include <linux/reset-controller.h>
- #include <dt-bindings/clock/qcom,gcc-msm8996.h>
- #include "common.h"
- #include "clk-regmap.h"
- #include "clk-alpha-pll.h"
- #include "clk-rcg.h"
- #include "clk-branch.h"
- #include "reset.h"
- #include "gdsc.h"
- enum {
- P_XO,
- P_GPLL0,
- P_GPLL0_EARLY_DIV,
- P_SLEEP_CLK,
- P_GPLL4,
- P_AUD_REF_CLK,
- };
- static struct clk_fixed_factor xo = {
- .mult = 1,
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "xo",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "cxo", .name = "xo_board",
- },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
- };
- static struct clk_alpha_pll gpll0_early = {
- .offset = 0x00000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr = {
- .enable_reg = 0x52000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_early",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "cxo", .name = "xo_board",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
- },
- };
- static struct clk_fixed_factor gpll0_early_div = {
- .mult = 1,
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_early_div",
- .parent_hws = (const struct clk_hw*[]){
- &gpll0_early.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
- };
- static struct clk_alpha_pll_postdiv gpll0 = {
- .offset = 0x00000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll0",
- .parent_hws = (const struct clk_hw*[]){
- &gpll0_early.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ops,
- },
- };
- static struct clk_branch gcc_mmss_gpll0_div_clk = {
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x5200c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mmss_gpll0_div_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gpll0.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mss_gpll0_div_clk = {
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x5200c,
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_gpll0_div_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gpll0.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops
- },
- },
- };
- static struct clk_alpha_pll gpll4_early = {
- .offset = 0x77000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr = {
- .enable_reg = 0x52000,
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "gpll4_early",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "cxo", .name = "xo_board",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
- },
- };
- static struct clk_alpha_pll_postdiv gpll4 = {
- .offset = 0x77000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll4",
- .parent_hws = (const struct clk_hw*[]){
- &gpll4_early.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ops,
- },
- };
- static const struct parent_map gcc_sleep_clk_map[] = {
- { P_SLEEP_CLK, 5 }
- };
- static const struct clk_parent_data gcc_sleep_clk[] = {
- { .fw_name = "sleep_clk", .name = "sleep_clk" }
- };
- static const struct parent_map gcc_xo_gpll0_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 }
- };
- static const struct clk_parent_data gcc_xo_gpll0[] = {
- { .fw_name = "cxo", .name = "xo_board" },
- { .hw = &gpll0.clkr.hw }
- };
- static const struct parent_map gcc_xo_sleep_clk_map[] = {
- { P_XO, 0 },
- { P_SLEEP_CLK, 5 }
- };
- static const struct clk_parent_data gcc_xo_sleep_clk[] = {
- { .fw_name = "cxo", .name = "xo_board" },
- { .fw_name = "sleep_clk", .name = "sleep_clk" }
- };
- static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL0_EARLY_DIV, 6 }
- };
- static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {
- { .fw_name = "cxo", .name = "xo_board" },
- { .hw = &gpll0.clkr.hw },
- { .hw = &gpll0_early_div.hw }
- };
- static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL4, 5 }
- };
- static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
- { .fw_name = "cxo", .name = "xo_board" },
- { .hw = &gpll0.clkr.hw },
- { .hw = &gpll4.clkr.hw }
- };
- static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_AUD_REF_CLK, 2 }
- };
- static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {
- { .fw_name = "cxo", .name = "xo_board" },
- { .hw = &gpll0.clkr.hw },
- { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }
- };
- static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_SLEEP_CLK, 5 },
- { P_GPLL0_EARLY_DIV, 6 }
- };
- static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
- { .fw_name = "cxo", .name = "xo_board" },
- { .hw = &gpll0.clkr.hw },
- { .fw_name = "sleep_clk", .name = "sleep_clk" },
- { .hw = &gpll0_early_div.hw }
- };
- static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL4, 5 },
- { P_GPLL0_EARLY_DIV, 6 }
- };
- static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
- { .fw_name = "cxo", .name = "xo_board" },
- { .hw = &gpll0.clkr.hw },
- { .hw = &gpll4.clkr.hw },
- { .hw = &gpll0_early_div.hw }
- };
- static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(120000000, P_GPLL0, 5, 0, 0),
- F(150000000, P_GPLL0, 4, 0, 0),
- { }
- };
- static struct clk_rcg2 usb30_master_clk_src = {
- .cmd_rcgr = 0x0f014,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
- .freq_tbl = ftbl_usb30_master_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_master_clk_src",
- .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- { }
- };
- static struct clk_rcg2 usb30_mock_utmi_clk_src = {
- .cmd_rcgr = 0x0f028,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
- .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb30_mock_utmi_clk_src",
- .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
- F(1200000, P_XO, 16, 0, 0),
- { }
- };
- static struct clk_rcg2 usb3_phy_aux_clk_src = {
- .cmd_rcgr = 0x5000c,
- .hid_width = 5,
- .parent_map = gcc_xo_sleep_clk_map,
- .freq_tbl = ftbl_usb3_phy_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb3_phy_aux_clk_src",
- .parent_data = gcc_xo_sleep_clk,
- .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
- F(120000000, P_GPLL0, 5, 0, 0),
- { }
- };
- static struct clk_rcg2 usb20_master_clk_src = {
- .cmd_rcgr = 0x12010,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
- .freq_tbl = ftbl_usb20_master_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_master_clk_src",
- .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 usb20_mock_utmi_clk_src = {
- .cmd_rcgr = 0x12024,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
- .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb20_mock_utmi_clk_src",
- .parent_data = gcc_xo_gpll0_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
- F(144000, P_XO, 16, 3, 25),
- F(400000, P_XO, 12, 1, 4),
- F(20000000, P_GPLL0, 15, 1, 2),
- F(25000000, P_GPLL0, 12, 1, 2),
- F(50000000, P_GPLL0, 12, 0, 0),
- F(96000000, P_GPLL4, 4, 0, 0),
- F(192000000, P_GPLL4, 2, 0, 0),
- F(384000000, P_GPLL4, 1, 0, 0),
- { }
- };
- static struct clk_rcg2 sdcc1_apps_clk_src = {
- .cmd_rcgr = 0x13010,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
- .freq_tbl = ftbl_sdcc1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_apps_clk_src",
- .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_floor_ops,
- },
- };
- static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(150000000, P_GPLL0, 4, 0, 0),
- F(300000000, P_GPLL0, 2, 0, 0),
- { }
- };
- static struct clk_rcg2 sdcc1_ice_core_clk_src = {
- .cmd_rcgr = 0x13024,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
- .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_ice_core_clk_src",
- .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
- F(144000, P_XO, 16, 3, 25),
- F(400000, P_XO, 12, 1, 4),
- F(20000000, P_GPLL0, 15, 1, 2),
- F(25000000, P_GPLL0, 12, 1, 2),
- F(50000000, P_GPLL0, 12, 0, 0),
- F(100000000, P_GPLL0, 6, 0, 0),
- F(200000000, P_GPLL0, 3, 0, 0),
- { }
- };
- static struct clk_rcg2 sdcc2_apps_clk_src = {
- .cmd_rcgr = 0x14010,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll4_map,
- .freq_tbl = ftbl_sdcc2_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc2_apps_clk_src",
- .parent_data = gcc_xo_gpll0_gpll4,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
- };
- static struct clk_rcg2 sdcc3_apps_clk_src = {
- .cmd_rcgr = 0x15010,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll4_map,
- .freq_tbl = ftbl_sdcc2_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc3_apps_clk_src",
- .parent_data = gcc_xo_gpll0_gpll4,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_floor_ops,
- },
- };
- static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
- F(144000, P_XO, 16, 3, 25),
- F(400000, P_XO, 12, 1, 4),
- F(20000000, P_GPLL0, 15, 1, 2),
- F(25000000, P_GPLL0, 12, 1, 2),
- F(50000000, P_GPLL0, 12, 0, 0),
- F(100000000, P_GPLL0, 6, 0, 0),
- { }
- };
- static struct clk_rcg2 sdcc4_apps_clk_src = {
- .cmd_rcgr = 0x16010,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_sdcc4_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc4_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_floor_ops,
- },
- };
- static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
- F(960000, P_XO, 10, 1, 2),
- F(4800000, P_XO, 4, 0, 0),
- F(9600000, P_XO, 2, 0, 0),
- F(15000000, P_GPLL0, 10, 1, 4),
- F(19200000, P_XO, 1, 0, 0),
- F(25000000, P_GPLL0, 12, 1, 2),
- F(50000000, P_GPLL0, 12, 0, 0),
- { }
- };
- static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
- .cmd_rcgr = 0x1900c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(50000000, P_GPLL0, 12, 0, 0),
- { }
- };
- static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
- .cmd_rcgr = 0x19020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
- F(3686400, P_GPLL0, 1, 96, 15625),
- F(7372800, P_GPLL0, 1, 192, 15625),
- F(14745600, P_GPLL0, 1, 384, 15625),
- F(16000000, P_GPLL0, 5, 2, 15),
- F(19200000, P_XO, 1, 0, 0),
- F(24000000, P_GPLL0, 5, 1, 5),
- F(32000000, P_GPLL0, 1, 4, 75),
- F(40000000, P_GPLL0, 15, 0, 0),
- F(46400000, P_GPLL0, 1, 29, 375),
- F(48000000, P_GPLL0, 12.5, 0, 0),
- F(51200000, P_GPLL0, 1, 32, 375),
- F(56000000, P_GPLL0, 1, 7, 75),
- F(58982400, P_GPLL0, 1, 1536, 15625),
- F(60000000, P_GPLL0, 10, 0, 0),
- F(63157895, P_GPLL0, 9.5, 0, 0),
- { }
- };
- static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
- .cmd_rcgr = 0x1a00c,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart1_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
- .cmd_rcgr = 0x1b00c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
- .cmd_rcgr = 0x1b020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
- .cmd_rcgr = 0x1c00c,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart2_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
- .cmd_rcgr = 0x1d00c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
- .cmd_rcgr = 0x1d020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
- .cmd_rcgr = 0x1e00c,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart3_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
- .cmd_rcgr = 0x1f00c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
- .cmd_rcgr = 0x1f020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
- .cmd_rcgr = 0x2000c,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart4_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
- .cmd_rcgr = 0x2100c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
- .cmd_rcgr = 0x21020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
- .cmd_rcgr = 0x2200c,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart5_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
- .cmd_rcgr = 0x2300c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
- .cmd_rcgr = 0x23020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
- .cmd_rcgr = 0x2400c,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart6_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
- .cmd_rcgr = 0x2600c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
- .cmd_rcgr = 0x26020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup1_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
- .cmd_rcgr = 0x2700c,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart1_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
- .cmd_rcgr = 0x2800c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
- .cmd_rcgr = 0x28020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup2_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
- .cmd_rcgr = 0x2900c,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart2_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
- .cmd_rcgr = 0x2a00c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
- .cmd_rcgr = 0x2a020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup3_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
- .cmd_rcgr = 0x2b00c,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart3_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
- .cmd_rcgr = 0x2c00c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
- .cmd_rcgr = 0x2c020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup4_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
- .cmd_rcgr = 0x2d00c,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart4_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
- .cmd_rcgr = 0x2e00c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
- .cmd_rcgr = 0x2e020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup5_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
- .cmd_rcgr = 0x2f00c,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart5_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
- .cmd_rcgr = 0x3000c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
- .cmd_rcgr = 0x30020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_qup6_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
- .cmd_rcgr = 0x3100c,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp2_uart6_apps_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_pdm2_clk_src[] = {
- F(60000000, P_GPLL0, 10, 0, 0),
- { }
- };
- static struct clk_rcg2 pdm2_clk_src = {
- .cmd_rcgr = 0x33010,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_pdm2_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pdm2_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
- F(105495, P_XO, 1, 1, 182),
- { }
- };
- static struct clk_rcg2 tsif_ref_clk_src = {
- .cmd_rcgr = 0x36010,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
- .freq_tbl = ftbl_tsif_ref_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "tsif_ref_clk_src",
- .parent_data = gcc_xo_gpll0_aud_ref_clk,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 gcc_sleep_clk_src = {
- .cmd_rcgr = 0x43014,
- .hid_width = 5,
- .parent_map = gcc_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gcc_sleep_clk_src",
- .parent_data = gcc_sleep_clk,
- .num_parents = ARRAY_SIZE(gcc_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 hmss_rbcpr_clk_src = {
- .cmd_rcgr = 0x48040,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_rbcpr_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 hmss_gpll0_clk_src = {
- .cmd_rcgr = 0x48058,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "hmss_gpll0_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gp1_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(100000000, P_GPLL0, 6, 0, 0),
- F(200000000, P_GPLL0, 3, 0, 0),
- { }
- };
- static struct clk_rcg2 gp1_clk_src = {
- .cmd_rcgr = 0x64004,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
- .freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp1_clk_src",
- .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 gp2_clk_src = {
- .cmd_rcgr = 0x65004,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
- .freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp2_clk_src",
- .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 gp3_clk_src = {
- .cmd_rcgr = 0x66004,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
- .freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp3_clk_src",
- .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
- F(1010526, P_XO, 1, 1, 19),
- { }
- };
- static struct clk_rcg2 pcie_aux_clk_src = {
- .cmd_rcgr = 0x6c000,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_sleep_clk_map,
- .freq_tbl = ftbl_pcie_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie_aux_clk_src",
- .parent_data = gcc_xo_sleep_clk,
- .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
- F(100000000, P_GPLL0, 6, 0, 0),
- F(200000000, P_GPLL0, 3, 0, 0),
- F(240000000, P_GPLL0, 2.5, 0, 0),
- { }
- };
- static struct clk_rcg2 ufs_axi_clk_src = {
- .cmd_rcgr = 0x75024,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_ufs_axi_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_axi_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(150000000, P_GPLL0, 4, 0, 0),
- F(300000000, P_GPLL0, 2, 0, 0),
- { }
- };
- static struct clk_rcg2 ufs_ice_core_clk_src = {
- .cmd_rcgr = 0x76014,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_ufs_ice_core_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ufs_ice_core_clk_src",
- .parent_data = gcc_xo_gpll0,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
- F(75000000, P_GPLL0, 8, 0, 0),
- F(150000000, P_GPLL0, 4, 0, 0),
- F(256000000, P_GPLL4, 1.5, 0, 0),
- F(300000000, P_GPLL0, 2, 0, 0),
- { }
- };
- static struct clk_rcg2 qspi_ser_clk_src = {
- .cmd_rcgr = 0x8b00c,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
- .freq_tbl = ftbl_qspi_ser_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "qspi_ser_clk_src",
- .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
- .halt_reg = 0x0f03c,
- .clkr = {
- .enable_reg = 0x0f03c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_usb3_axi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &usb30_master_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
- .halt_reg = 0x75038,
- .clkr = {
- .enable_reg = 0x75038,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_ufs_axi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ufs_axi_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
- .halt_reg = 0x6010,
- .clkr = {
- .enable_reg = 0x6010,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_periph_noc_usb20_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &usb20_master_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
- .halt_reg = 0x9008,
- .clkr = {
- .enable_reg = 0x9008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mmss_noc_cfg_ahb_clk",
- .flags = CLK_IGNORE_UNUSED,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mmss_bimc_gfx_clk = {
- .halt_reg = 0x9010,
- .clkr = {
- .enable_reg = 0x9010,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mmss_bimc_gfx_clk",
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb30_master_clk = {
- .halt_reg = 0x0f008,
- .clkr = {
- .enable_reg = 0x0f008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb30_master_clk",
- .parent_hws = (const struct clk_hw*[]){
- &usb30_master_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb30_sleep_clk = {
- .halt_reg = 0x0f00c,
- .clkr = {
- .enable_reg = 0x0f00c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb30_sleep_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_sleep_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb30_mock_utmi_clk = {
- .halt_reg = 0x0f010,
- .clkr = {
- .enable_reg = 0x0f010,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb30_mock_utmi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &usb30_mock_utmi_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb3_phy_aux_clk = {
- .halt_reg = 0x50000,
- .clkr = {
- .enable_reg = 0x50000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb3_phy_aux_clk",
- .parent_hws = (const struct clk_hw*[]){
- &usb3_phy_aux_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb3_phy_pipe_clk = {
- .halt_reg = 0x50004,
- .halt_check = BRANCH_HALT_SKIP,
- .clkr = {
- .enable_reg = 0x50004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb3_phy_pipe_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb20_master_clk = {
- .halt_reg = 0x12004,
- .clkr = {
- .enable_reg = 0x12004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb20_master_clk",
- .parent_hws = (const struct clk_hw*[]){
- &usb20_master_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb20_sleep_clk = {
- .halt_reg = 0x12008,
- .clkr = {
- .enable_reg = 0x12008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb20_sleep_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_sleep_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb20_mock_utmi_clk = {
- .halt_reg = 0x1200c,
- .clkr = {
- .enable_reg = 0x1200c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb20_mock_utmi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &usb20_mock_utmi_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
- .halt_reg = 0x6a004,
- .clkr = {
- .enable_reg = 0x6a004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_phy_cfg_ahb2phy_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc1_apps_clk = {
- .halt_reg = 0x13004,
- .clkr = {
- .enable_reg = 0x13004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &sdcc1_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc1_ahb_clk = {
- .halt_reg = 0x13008,
- .clkr = {
- .enable_reg = 0x13008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc1_ice_core_clk = {
- .halt_reg = 0x13038,
- .clkr = {
- .enable_reg = 0x13038,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ice_core_clk",
- .parent_hws = (const struct clk_hw*[]){
- &sdcc1_ice_core_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc2_apps_clk = {
- .halt_reg = 0x14004,
- .clkr = {
- .enable_reg = 0x14004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &sdcc2_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc2_ahb_clk = {
- .halt_reg = 0x14008,
- .clkr = {
- .enable_reg = 0x14008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc3_apps_clk = {
- .halt_reg = 0x15004,
- .clkr = {
- .enable_reg = 0x15004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc3_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &sdcc3_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc3_ahb_clk = {
- .halt_reg = 0x15008,
- .clkr = {
- .enable_reg = 0x15008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc3_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc4_apps_clk = {
- .halt_reg = 0x16004,
- .clkr = {
- .enable_reg = 0x16004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc4_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &sdcc4_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc4_ahb_clk = {
- .halt_reg = 0x16008,
- .clkr = {
- .enable_reg = 0x16008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc4_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_ahb_clk = {
- .halt_reg = 0x17004,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x52004,
- .enable_mask = BIT(17),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_sleep_clk = {
- .halt_reg = 0x17008,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x52004,
- .enable_mask = BIT(16),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_sleep_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_sleep_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
- .halt_reg = 0x19004,
- .clkr = {
- .enable_reg = 0x19004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup1_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
- .halt_reg = 0x19008,
- .clkr = {
- .enable_reg = 0x19008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_uart1_apps_clk = {
- .halt_reg = 0x1a004,
- .clkr = {
- .enable_reg = 0x1a004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart1_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_uart1_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
- .halt_reg = 0x1b004,
- .clkr = {
- .enable_reg = 0x1b004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup2_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
- .halt_reg = 0x1b008,
- .clkr = {
- .enable_reg = 0x1b008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_uart2_apps_clk = {
- .halt_reg = 0x1c004,
- .clkr = {
- .enable_reg = 0x1c004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart2_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_uart2_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
- .halt_reg = 0x1d004,
- .clkr = {
- .enable_reg = 0x1d004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup3_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
- .halt_reg = 0x1d008,
- .clkr = {
- .enable_reg = 0x1d008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_uart3_apps_clk = {
- .halt_reg = 0x1e004,
- .clkr = {
- .enable_reg = 0x1e004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart3_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_uart3_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
- .halt_reg = 0x1f004,
- .clkr = {
- .enable_reg = 0x1f004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup4_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
- .halt_reg = 0x1f008,
- .clkr = {
- .enable_reg = 0x1f008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_uart4_apps_clk = {
- .halt_reg = 0x20004,
- .clkr = {
- .enable_reg = 0x20004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart4_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_uart4_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
- .halt_reg = 0x21004,
- .clkr = {
- .enable_reg = 0x21004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup5_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
- .halt_reg = 0x21008,
- .clkr = {
- .enable_reg = 0x21008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_uart5_apps_clk = {
- .halt_reg = 0x22004,
- .clkr = {
- .enable_reg = 0x22004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart5_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_uart5_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
- .halt_reg = 0x23004,
- .clkr = {
- .enable_reg = 0x23004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup6_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
- .halt_reg = 0x23008,
- .clkr = {
- .enable_reg = 0x23008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_uart6_apps_clk = {
- .halt_reg = 0x24004,
- .clkr = {
- .enable_reg = 0x24004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart6_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_uart6_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_ahb_clk = {
- .halt_reg = 0x25004,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x52004,
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_sleep_clk = {
- .halt_reg = 0x25008,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x52004,
- .enable_mask = BIT(14),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_sleep_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_sleep_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
- .halt_reg = 0x26004,
- .clkr = {
- .enable_reg = 0x26004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup1_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_qup1_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
- .halt_reg = 0x26008,
- .clkr = {
- .enable_reg = 0x26008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup1_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_uart1_apps_clk = {
- .halt_reg = 0x27004,
- .clkr = {
- .enable_reg = 0x27004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart1_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_uart1_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
- .halt_reg = 0x28004,
- .clkr = {
- .enable_reg = 0x28004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup2_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_qup2_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
- .halt_reg = 0x28008,
- .clkr = {
- .enable_reg = 0x28008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup2_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_uart2_apps_clk = {
- .halt_reg = 0x29004,
- .clkr = {
- .enable_reg = 0x29004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart2_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_uart2_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
- .halt_reg = 0x2a004,
- .clkr = {
- .enable_reg = 0x2a004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup3_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_qup3_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
- .halt_reg = 0x2a008,
- .clkr = {
- .enable_reg = 0x2a008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup3_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_uart3_apps_clk = {
- .halt_reg = 0x2b004,
- .clkr = {
- .enable_reg = 0x2b004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart3_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_uart3_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
- .halt_reg = 0x2c004,
- .clkr = {
- .enable_reg = 0x2c004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup4_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_qup4_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
- .halt_reg = 0x2c008,
- .clkr = {
- .enable_reg = 0x2c008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup4_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_uart4_apps_clk = {
- .halt_reg = 0x2d004,
- .clkr = {
- .enable_reg = 0x2d004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart4_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_uart4_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
- .halt_reg = 0x2e004,
- .clkr = {
- .enable_reg = 0x2e004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup5_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_qup5_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
- .halt_reg = 0x2e008,
- .clkr = {
- .enable_reg = 0x2e008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup5_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_qup5_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_uart5_apps_clk = {
- .halt_reg = 0x2f004,
- .clkr = {
- .enable_reg = 0x2f004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart5_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_uart5_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
- .halt_reg = 0x30004,
- .clkr = {
- .enable_reg = 0x30004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup6_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_qup6_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
- .halt_reg = 0x30008,
- .clkr = {
- .enable_reg = 0x30008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_qup6_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_qup6_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp2_uart6_apps_clk = {
- .halt_reg = 0x31004,
- .clkr = {
- .enable_reg = 0x31004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp2_uart6_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp2_uart6_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pdm_ahb_clk = {
- .halt_reg = 0x33004,
- .clkr = {
- .enable_reg = 0x33004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pdm2_clk = {
- .halt_reg = 0x3300c,
- .clkr = {
- .enable_reg = 0x3300c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm2_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pdm2_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_prng_ahb_clk = {
- .halt_reg = 0x34004,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x52004,
- .enable_mask = BIT(13),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_prng_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_tsif_ahb_clk = {
- .halt_reg = 0x36004,
- .clkr = {
- .enable_reg = 0x36004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_tsif_ref_clk = {
- .halt_reg = 0x36008,
- .clkr = {
- .enable_reg = 0x36008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_ref_clk",
- .parent_hws = (const struct clk_hw*[]){
- &tsif_ref_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_tsif_inactivity_timers_clk = {
- .halt_reg = 0x3600c,
- .clkr = {
- .enable_reg = 0x3600c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_tsif_inactivity_timers_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_sleep_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_boot_rom_ahb_clk = {
- .halt_reg = 0x38004,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x52004,
- .enable_mask = BIT(10),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_boot_rom_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_bimc_gfx_clk = {
- .halt_reg = 0x46018,
- .clkr = {
- .enable_reg = 0x46018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_bimc_gfx_clk",
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_hmss_rbcpr_clk = {
- .halt_reg = 0x4800c,
- .clkr = {
- .enable_reg = 0x4800c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_hmss_rbcpr_clk",
- .parent_hws = (const struct clk_hw*[]){
- &hmss_rbcpr_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_gp1_clk = {
- .halt_reg = 0x64000,
- .clkr = {
- .enable_reg = 0x64000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp1_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gp1_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_gp2_clk = {
- .halt_reg = 0x65000,
- .clkr = {
- .enable_reg = 0x65000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp2_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gp2_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_gp3_clk = {
- .halt_reg = 0x66000,
- .clkr = {
- .enable_reg = 0x66000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp3_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gp3_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_0_slv_axi_clk = {
- .halt_reg = 0x6b008,
- .clkr = {
- .enable_reg = 0x6b008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_slv_axi_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
- .halt_reg = 0x6b00c,
- .clkr = {
- .enable_reg = 0x6b00c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_mstr_axi_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
- .halt_reg = 0x6b010,
- .clkr = {
- .enable_reg = 0x6b010,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_cfg_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_0_aux_clk = {
- .halt_reg = 0x6b014,
- .clkr = {
- .enable_reg = 0x6b014,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_aux_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcie_aux_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_0_pipe_clk = {
- .halt_reg = 0x6b018,
- .halt_check = BRANCH_HALT_SKIP,
- .clkr = {
- .enable_reg = 0x6b018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_0_pipe_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_1_slv_axi_clk = {
- .halt_reg = 0x6d008,
- .clkr = {
- .enable_reg = 0x6d008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_slv_axi_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
- .halt_reg = 0x6d00c,
- .clkr = {
- .enable_reg = 0x6d00c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_mstr_axi_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
- .halt_reg = 0x6d010,
- .clkr = {
- .enable_reg = 0x6d010,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_cfg_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_1_aux_clk = {
- .halt_reg = 0x6d014,
- .clkr = {
- .enable_reg = 0x6d014,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_aux_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcie_aux_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_1_pipe_clk = {
- .halt_reg = 0x6d018,
- .halt_check = BRANCH_HALT_SKIP,
- .clkr = {
- .enable_reg = 0x6d018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_1_pipe_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_2_slv_axi_clk = {
- .halt_reg = 0x6e008,
- .clkr = {
- .enable_reg = 0x6e008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_slv_axi_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
- .halt_reg = 0x6e00c,
- .clkr = {
- .enable_reg = 0x6e00c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_mstr_axi_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
- .halt_reg = 0x6e010,
- .clkr = {
- .enable_reg = 0x6e010,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_cfg_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_2_aux_clk = {
- .halt_reg = 0x6e014,
- .clkr = {
- .enable_reg = 0x6e014,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_aux_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcie_aux_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_2_pipe_clk = {
- .halt_reg = 0x6e018,
- .halt_check = BRANCH_HALT_SKIP,
- .clkr = {
- .enable_reg = 0x6e018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_2_pipe_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
- .halt_reg = 0x6f004,
- .clkr = {
- .enable_reg = 0x6f004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_phy_cfg_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_phy_aux_clk = {
- .halt_reg = 0x6f008,
- .clkr = {
- .enable_reg = 0x6f008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_phy_aux_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcie_aux_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ufs_axi_clk = {
- .halt_reg = 0x75008,
- .clkr = {
- .enable_reg = 0x75008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_axi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ufs_axi_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ufs_ahb_clk = {
- .halt_reg = 0x7500c,
- .clkr = {
- .enable_reg = 0x7500c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
- .mult = 1,
- .div = 16,
- .hw.init = &(struct clk_init_data){
- .name = "ufs_tx_cfg_clk_src",
- .parent_hws = (const struct clk_hw*[]){
- &ufs_axi_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_fixed_factor_ops,
- },
- };
- static struct clk_branch gcc_ufs_tx_cfg_clk = {
- .halt_reg = 0x75010,
- .clkr = {
- .enable_reg = 0x75010,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_tx_cfg_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ufs_tx_cfg_clk_src.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
- .mult = 1,
- .div = 16,
- .hw.init = &(struct clk_init_data){
- .name = "ufs_rx_cfg_clk_src",
- .parent_hws = (const struct clk_hw*[]){
- &ufs_axi_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_fixed_factor_ops,
- },
- };
- static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
- .halt_reg = 0x7d010,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x7d010,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "hlos1_vote_lpass_core_smmu_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
- .halt_reg = 0x7d014,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x7d014,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "hlos1_vote_lpass_adsp_smmu_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ufs_rx_cfg_clk = {
- .halt_reg = 0x75014,
- .clkr = {
- .enable_reg = 0x75014,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_rx_cfg_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ufs_rx_cfg_clk_src.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
- .halt_reg = 0x75018,
- .halt_check = BRANCH_HALT_SKIP,
- .clkr = {
- .enable_reg = 0x75018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_tx_symbol_0_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
- .halt_reg = 0x7501c,
- .halt_check = BRANCH_HALT_SKIP,
- .clkr = {
- .enable_reg = 0x7501c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_rx_symbol_0_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
- .halt_reg = 0x75020,
- .halt_check = BRANCH_HALT_SKIP,
- .clkr = {
- .enable_reg = 0x75020,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_rx_symbol_1_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
- .mult = 1,
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "ufs_ice_core_postdiv_clk_src",
- .parent_hws = (const struct clk_hw*[]){
- &ufs_ice_core_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_fixed_factor_ops,
- },
- };
- static struct clk_branch gcc_ufs_unipro_core_clk = {
- .halt_reg = 0x7600c,
- .clkr = {
- .enable_reg = 0x7600c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_unipro_core_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ufs_ice_core_postdiv_clk_src.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ufs_ice_core_clk = {
- .halt_reg = 0x76010,
- .clkr = {
- .enable_reg = 0x76010,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_ice_core_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ufs_ice_core_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ufs_sys_clk_core_clk = {
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x76030,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_sys_clk_core_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x76034,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_tx_symbol_clk_core_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_aggre0_snoc_axi_clk = {
- .halt_reg = 0x81008,
- .clkr = {
- .enable_reg = 0x81008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_snoc_axi_clk",
- .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
- .halt_reg = 0x8100c,
- .clkr = {
- .enable_reg = 0x8100c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_cnoc_ahb_clk",
- .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_smmu_aggre0_axi_clk = {
- .halt_reg = 0x81014,
- .clkr = {
- .enable_reg = 0x81014,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_axi_clk",
- .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
- .halt_reg = 0x81018,
- .clkr = {
- .enable_reg = 0x81018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_aggre0_ahb_clk",
- .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_aggre2_ufs_axi_clk = {
- .halt_reg = 0x83014,
- .clkr = {
- .enable_reg = 0x83014,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre2_ufs_axi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ufs_axi_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_aggre2_usb3_axi_clk = {
- .halt_reg = 0x83018,
- .clkr = {
- .enable_reg = 0x83018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre2_usb3_axi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &usb30_master_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_dcc_ahb_clk = {
- .halt_reg = 0x84004,
- .clkr = {
- .enable_reg = 0x84004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_dcc_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
- .halt_reg = 0x85000,
- .clkr = {
- .enable_reg = 0x85000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_qspi_ahb_clk = {
- .halt_reg = 0x8b004,
- .clkr = {
- .enable_reg = 0x8b004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qspi_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_qspi_ser_clk = {
- .halt_reg = 0x8b008,
- .clkr = {
- .enable_reg = 0x8b008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qspi_ser_clk",
- .parent_hws = (const struct clk_hw*[]){
- &qspi_ser_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb3_clkref_clk = {
- .halt_reg = 0x8800C,
- .clkr = {
- .enable_reg = 0x8800C,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb3_clkref_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "cxo2",
- .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_hdmi_clkref_clk = {
- .halt_reg = 0x88000,
- .clkr = {
- .enable_reg = 0x88000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_hdmi_clkref_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "cxo2",
- .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_edp_clkref_clk = {
- .halt_reg = 0x88004,
- .clkr = {
- .enable_reg = 0x88004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_edp_clkref_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "cxo2",
- .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ufs_clkref_clk = {
- .halt_reg = 0x88008,
- .clkr = {
- .enable_reg = 0x88008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ufs_clkref_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "cxo2",
- .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pcie_clkref_clk = {
- .halt_reg = 0x88010,
- .clkr = {
- .enable_reg = 0x88010,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie_clkref_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "cxo2",
- .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_rx2_usb2_clkref_clk = {
- .halt_reg = 0x88014,
- .clkr = {
- .enable_reg = 0x88014,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_rx2_usb2_clkref_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "cxo2",
- .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_rx1_usb2_clkref_clk = {
- .halt_reg = 0x88018,
- .clkr = {
- .enable_reg = 0x88018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_rx1_usb2_clkref_clk",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "cxo2",
- .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mss_cfg_ahb_clk = {
- .halt_reg = 0x8a000,
- .clkr = {
- .enable_reg = 0x8a000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_cfg_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
- .halt_reg = 0x8a004,
- .clkr = {
- .enable_reg = 0x8a004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_mnoc_bimc_axi_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mss_snoc_axi_clk = {
- .halt_reg = 0x8a024,
- .clkr = {
- .enable_reg = 0x8a024,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_snoc_axi_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
- .halt_reg = 0x8a028,
- .clkr = {
- .enable_reg = 0x8a028,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_q6_bimc_axi_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_hw *gcc_msm8996_hws[] = {
- &xo.hw,
- &gpll0_early_div.hw,
- &ufs_tx_cfg_clk_src.hw,
- &ufs_rx_cfg_clk_src.hw,
- &ufs_ice_core_postdiv_clk_src.hw,
- };
- static struct gdsc aggre0_noc_gdsc = {
- .gdscr = 0x81004,
- .gds_hw_ctrl = 0x81028,
- .pd = {
- .name = "aggre0_noc",
- },
- .pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE | ALWAYS_ON,
- };
- static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
- .gdscr = 0x7d024,
- .pd = {
- .name = "hlos1_vote_aggre0_noc",
- },
- .pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE,
- };
- static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
- .gdscr = 0x7d034,
- .pd = {
- .name = "hlos1_vote_lpass_adsp",
- },
- .pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE,
- };
- static struct gdsc hlos1_vote_lpass_core_gdsc = {
- .gdscr = 0x7d038,
- .pd = {
- .name = "hlos1_vote_lpass_core",
- },
- .pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE,
- };
- static struct gdsc usb30_gdsc = {
- .gdscr = 0xf004,
- .pd = {
- .name = "usb30",
- },
- .pwrsts = PWRSTS_OFF_ON,
- };
- static struct gdsc pcie0_gdsc = {
- .gdscr = 0x6b004,
- .pd = {
- .name = "pcie0",
- },
- .pwrsts = PWRSTS_OFF_ON,
- };
- static struct gdsc pcie1_gdsc = {
- .gdscr = 0x6d004,
- .pd = {
- .name = "pcie1",
- },
- .pwrsts = PWRSTS_OFF_ON,
- };
- static struct gdsc pcie2_gdsc = {
- .gdscr = 0x6e004,
- .pd = {
- .name = "pcie2",
- },
- .pwrsts = PWRSTS_OFF_ON,
- };
- static struct gdsc ufs_gdsc = {
- .gdscr = 0x75004,
- .pd = {
- .name = "ufs",
- },
- .pwrsts = PWRSTS_OFF_ON,
- };
- static struct clk_regmap *gcc_msm8996_clocks[] = {
- [GPLL0_EARLY] = &gpll0_early.clkr,
- [GPLL0] = &gpll0.clkr,
- [GPLL4_EARLY] = &gpll4_early.clkr,
- [GPLL4] = &gpll4.clkr,
- [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
- [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
- [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
- [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
- [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
- [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
- [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
- [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
- [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
- [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
- [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
- [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
- [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
- [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
- [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
- [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
- [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
- [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
- [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
- [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
- [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
- [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
- [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
- [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
- [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
- [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
- [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
- [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
- [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
- [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
- [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
- [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
- [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
- [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
- [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
- [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
- [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
- [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
- [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
- [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
- [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
- [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
- [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
- [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
- [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
- [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
- [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
- [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
- [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
- [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
- [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
- [GP1_CLK_SRC] = &gp1_clk_src.clkr,
- [GP2_CLK_SRC] = &gp2_clk_src.clkr,
- [GP3_CLK_SRC] = &gp3_clk_src.clkr,
- [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
- [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
- [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
- [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
- [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
- [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
- [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
- [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
- [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
- [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
- [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
- [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
- [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
- [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
- [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
- [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
- [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
- [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
- [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
- [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
- [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
- [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
- [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
- [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
- [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
- [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
- [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
- [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
- [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
- [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
- [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
- [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
- [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
- [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
- [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
- [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
- [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
- [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
- [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
- [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
- [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
- [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
- [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
- [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
- [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
- [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
- [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
- [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
- [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
- [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
- [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
- [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
- [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
- [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
- [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
- [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
- [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
- [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
- [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
- [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
- [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
- [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
- [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
- [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
- [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
- [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
- [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
- [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
- [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
- [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
- [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
- [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
- [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
- [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
- [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
- [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
- [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
- [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
- [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
- [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
- [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
- [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
- [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
- [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
- [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
- [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
- [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
- [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
- [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
- [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
- [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
- [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
- [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
- [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
- [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
- [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
- [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
- [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
- [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
- [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
- [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
- [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
- [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
- [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
- [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
- [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
- [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
- [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
- [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
- [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
- [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
- [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
- [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
- [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
- [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
- [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
- [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
- [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
- [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
- [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
- [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
- [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
- [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
- [GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,
- [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
- [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
- [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
- [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
- [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
- [GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
- [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
- [GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,
- };
- static struct gdsc *gcc_msm8996_gdscs[] = {
- [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
- [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
- [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
- [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
- [USB30_GDSC] = &usb30_gdsc,
- [PCIE0_GDSC] = &pcie0_gdsc,
- [PCIE1_GDSC] = &pcie1_gdsc,
- [PCIE2_GDSC] = &pcie2_gdsc,
- [UFS_GDSC] = &ufs_gdsc,
- };
- static const struct qcom_reset_map gcc_msm8996_resets[] = {
- [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
- [GCC_CONFIG_NOC_BCR] = { 0x5000 },
- [GCC_PERIPH_NOC_BCR] = { 0x6000 },
- [GCC_IMEM_BCR] = { 0x8000 },
- [GCC_MMSS_BCR] = { 0x9000 },
- [GCC_PIMEM_BCR] = { 0x0a000 },
- [GCC_QDSS_BCR] = { 0x0c000 },
- [GCC_USB_30_BCR] = { 0x0f000 },
- [GCC_USB_20_BCR] = { 0x12000 },
- [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
- [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
- [GCC_USB3_PHY_BCR] = { 0x50020 },
- [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
- [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
- [GCC_SDCC1_BCR] = { 0x13000 },
- [GCC_SDCC2_BCR] = { 0x14000 },
- [GCC_SDCC3_BCR] = { 0x15000 },
- [GCC_SDCC4_BCR] = { 0x16000 },
- [GCC_BLSP1_BCR] = { 0x17000 },
- [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
- [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
- [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
- [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
- [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
- [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
- [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
- [GCC_BLSP1_UART4_BCR] = { 0x20000 },
- [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
- [GCC_BLSP1_UART5_BCR] = { 0x22000 },
- [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
- [GCC_BLSP1_UART6_BCR] = { 0x24000 },
- [GCC_BLSP2_BCR] = { 0x25000 },
- [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
- [GCC_BLSP2_UART1_BCR] = { 0x27000 },
- [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
- [GCC_BLSP2_UART2_BCR] = { 0x29000 },
- [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
- [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
- [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
- [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
- [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
- [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
- [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
- [GCC_BLSP2_UART6_BCR] = { 0x31000 },
- [GCC_PDM_BCR] = { 0x33000 },
- [GCC_PRNG_BCR] = { 0x34000 },
- [GCC_TSIF_BCR] = { 0x36000 },
- [GCC_TCSR_BCR] = { 0x37000 },
- [GCC_BOOT_ROM_BCR] = { 0x38000 },
- [GCC_MSG_RAM_BCR] = { 0x39000 },
- [GCC_TLMM_BCR] = { 0x3a000 },
- [GCC_MPM_BCR] = { 0x3b000 },
- [GCC_SEC_CTRL_BCR] = { 0x3d000 },
- [GCC_SPMI_BCR] = { 0x3f000 },
- [GCC_SPDM_BCR] = { 0x40000 },
- [GCC_CE1_BCR] = { 0x41000 },
- [GCC_BIMC_BCR] = { 0x44000 },
- [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
- [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
- [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
- [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
- [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
- [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
- [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
- [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
- [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
- [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
- [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
- [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
- [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
- [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
- [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
- [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
- [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
- [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
- [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
- [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
- [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
- [GCC_APB2JTAG_BCR] = { 0x4c000 },
- [GCC_RBCPR_CX_BCR] = { 0x4e000 },
- [GCC_RBCPR_MX_BCR] = { 0x4f000 },
- [GCC_PCIE_0_BCR] = { 0x6b000 },
- [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
- [GCC_PCIE_1_BCR] = { 0x6d000 },
- [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
- [GCC_PCIE_2_BCR] = { 0x6e000 },
- [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
- [GCC_PCIE_PHY_BCR] = { 0x6f000 },
- [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
- [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
- [GCC_DCD_BCR] = { 0x70000 },
- [GCC_OBT_ODT_BCR] = { 0x73000 },
- [GCC_UFS_BCR] = { 0x75000 },
- [GCC_SSC_BCR] = { 0x63000 },
- [GCC_VS_BCR] = { 0x7a000 },
- [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
- [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
- [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
- [GCC_DCC_BCR] = { 0x84000 },
- [GCC_IPA_BCR] = { 0x89000 },
- [GCC_QSPI_BCR] = { 0x8b000 },
- [GCC_SKL_BCR] = { 0x8c000 },
- [GCC_MSMPU_BCR] = { 0x8d000 },
- [GCC_MSS_Q6_BCR] = { 0x8e000 },
- [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
- [GCC_MSS_RESTART] = { 0x8f008 },
- };
- static const struct regmap_config gcc_msm8996_regmap_config = {
- .reg_bits = 32,
- .reg_stride = 4,
- .val_bits = 32,
- .max_register = 0x8f010,
- .fast_io = true,
- };
- static const struct qcom_cc_desc gcc_msm8996_desc = {
- .config = &gcc_msm8996_regmap_config,
- .clks = gcc_msm8996_clocks,
- .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
- .resets = gcc_msm8996_resets,
- .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
- .gdscs = gcc_msm8996_gdscs,
- .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
- .clk_hws = gcc_msm8996_hws,
- .num_clk_hws = ARRAY_SIZE(gcc_msm8996_hws),
- };
- static const struct of_device_id gcc_msm8996_match_table[] = {
- { .compatible = "qcom,gcc-msm8996" },
- { }
- };
- MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
- static int gcc_msm8996_probe(struct platform_device *pdev)
- {
- struct regmap *regmap;
- regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
- if (IS_ERR(regmap))
- return PTR_ERR(regmap);
- /*
- * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
- * turned off by hardware during certain apps low power modes.
- */
- regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
- return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
- }
- static struct platform_driver gcc_msm8996_driver = {
- .probe = gcc_msm8996_probe,
- .driver = {
- .name = "gcc-msm8996",
- .of_match_table = gcc_msm8996_match_table,
- },
- };
- static int __init gcc_msm8996_init(void)
- {
- return platform_driver_register(&gcc_msm8996_driver);
- }
- core_initcall(gcc_msm8996_init);
- static void __exit gcc_msm8996_exit(void)
- {
- platform_driver_unregister(&gcc_msm8996_driver);
- }
- module_exit(gcc_msm8996_exit);
- MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
- MODULE_LICENSE("GPL v2");
- MODULE_ALIAS("platform:gcc-msm8996");
|