gcc-msm8996.c 93 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/bitops.h>
  7. #include <linux/err.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/regmap.h>
  14. #include <linux/reset-controller.h>
  15. #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  16. #include "common.h"
  17. #include "clk-regmap.h"
  18. #include "clk-alpha-pll.h"
  19. #include "clk-rcg.h"
  20. #include "clk-branch.h"
  21. #include "reset.h"
  22. #include "gdsc.h"
  23. enum {
  24. P_XO,
  25. P_GPLL0,
  26. P_GPLL0_EARLY_DIV,
  27. P_SLEEP_CLK,
  28. P_GPLL4,
  29. P_AUD_REF_CLK,
  30. };
  31. static struct clk_fixed_factor xo = {
  32. .mult = 1,
  33. .div = 1,
  34. .hw.init = &(struct clk_init_data){
  35. .name = "xo",
  36. .parent_data = &(const struct clk_parent_data){
  37. .fw_name = "cxo", .name = "xo_board",
  38. },
  39. .num_parents = 1,
  40. .ops = &clk_fixed_factor_ops,
  41. },
  42. };
  43. static struct clk_alpha_pll gpll0_early = {
  44. .offset = 0x00000,
  45. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  46. .clkr = {
  47. .enable_reg = 0x52000,
  48. .enable_mask = BIT(0),
  49. .hw.init = &(struct clk_init_data){
  50. .name = "gpll0_early",
  51. .parent_data = &(const struct clk_parent_data){
  52. .fw_name = "cxo", .name = "xo_board",
  53. },
  54. .num_parents = 1,
  55. .ops = &clk_alpha_pll_ops,
  56. },
  57. },
  58. };
  59. static struct clk_fixed_factor gpll0_early_div = {
  60. .mult = 1,
  61. .div = 2,
  62. .hw.init = &(struct clk_init_data){
  63. .name = "gpll0_early_div",
  64. .parent_hws = (const struct clk_hw*[]){
  65. &gpll0_early.clkr.hw,
  66. },
  67. .num_parents = 1,
  68. .ops = &clk_fixed_factor_ops,
  69. },
  70. };
  71. static struct clk_alpha_pll_postdiv gpll0 = {
  72. .offset = 0x00000,
  73. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  74. .clkr.hw.init = &(struct clk_init_data){
  75. .name = "gpll0",
  76. .parent_hws = (const struct clk_hw*[]){
  77. &gpll0_early.clkr.hw,
  78. },
  79. .num_parents = 1,
  80. .ops = &clk_alpha_pll_postdiv_ops,
  81. },
  82. };
  83. static struct clk_branch gcc_mmss_gpll0_div_clk = {
  84. .halt_check = BRANCH_HALT_DELAY,
  85. .clkr = {
  86. .enable_reg = 0x5200c,
  87. .enable_mask = BIT(0),
  88. .hw.init = &(struct clk_init_data){
  89. .name = "gcc_mmss_gpll0_div_clk",
  90. .parent_hws = (const struct clk_hw*[]){
  91. &gpll0.clkr.hw,
  92. },
  93. .num_parents = 1,
  94. .flags = CLK_SET_RATE_PARENT,
  95. .ops = &clk_branch2_ops,
  96. },
  97. },
  98. };
  99. static struct clk_branch gcc_mss_gpll0_div_clk = {
  100. .halt_check = BRANCH_HALT_DELAY,
  101. .clkr = {
  102. .enable_reg = 0x5200c,
  103. .enable_mask = BIT(2),
  104. .hw.init = &(struct clk_init_data){
  105. .name = "gcc_mss_gpll0_div_clk",
  106. .parent_hws = (const struct clk_hw*[]){
  107. &gpll0.clkr.hw,
  108. },
  109. .num_parents = 1,
  110. .flags = CLK_SET_RATE_PARENT,
  111. .ops = &clk_branch2_ops
  112. },
  113. },
  114. };
  115. static struct clk_alpha_pll gpll4_early = {
  116. .offset = 0x77000,
  117. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  118. .clkr = {
  119. .enable_reg = 0x52000,
  120. .enable_mask = BIT(4),
  121. .hw.init = &(struct clk_init_data){
  122. .name = "gpll4_early",
  123. .parent_data = &(const struct clk_parent_data){
  124. .fw_name = "cxo", .name = "xo_board",
  125. },
  126. .num_parents = 1,
  127. .ops = &clk_alpha_pll_ops,
  128. },
  129. },
  130. };
  131. static struct clk_alpha_pll_postdiv gpll4 = {
  132. .offset = 0x77000,
  133. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  134. .clkr.hw.init = &(struct clk_init_data){
  135. .name = "gpll4",
  136. .parent_hws = (const struct clk_hw*[]){
  137. &gpll4_early.clkr.hw,
  138. },
  139. .num_parents = 1,
  140. .ops = &clk_alpha_pll_postdiv_ops,
  141. },
  142. };
  143. static const struct parent_map gcc_sleep_clk_map[] = {
  144. { P_SLEEP_CLK, 5 }
  145. };
  146. static const struct clk_parent_data gcc_sleep_clk[] = {
  147. { .fw_name = "sleep_clk", .name = "sleep_clk" }
  148. };
  149. static const struct parent_map gcc_xo_gpll0_map[] = {
  150. { P_XO, 0 },
  151. { P_GPLL0, 1 }
  152. };
  153. static const struct clk_parent_data gcc_xo_gpll0[] = {
  154. { .fw_name = "cxo", .name = "xo_board" },
  155. { .hw = &gpll0.clkr.hw }
  156. };
  157. static const struct parent_map gcc_xo_sleep_clk_map[] = {
  158. { P_XO, 0 },
  159. { P_SLEEP_CLK, 5 }
  160. };
  161. static const struct clk_parent_data gcc_xo_sleep_clk[] = {
  162. { .fw_name = "cxo", .name = "xo_board" },
  163. { .fw_name = "sleep_clk", .name = "sleep_clk" }
  164. };
  165. static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
  166. { P_XO, 0 },
  167. { P_GPLL0, 1 },
  168. { P_GPLL0_EARLY_DIV, 6 }
  169. };
  170. static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {
  171. { .fw_name = "cxo", .name = "xo_board" },
  172. { .hw = &gpll0.clkr.hw },
  173. { .hw = &gpll0_early_div.hw }
  174. };
  175. static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  176. { P_XO, 0 },
  177. { P_GPLL0, 1 },
  178. { P_GPLL4, 5 }
  179. };
  180. static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
  181. { .fw_name = "cxo", .name = "xo_board" },
  182. { .hw = &gpll0.clkr.hw },
  183. { .hw = &gpll4.clkr.hw }
  184. };
  185. static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
  186. { P_XO, 0 },
  187. { P_GPLL0, 1 },
  188. { P_AUD_REF_CLK, 2 }
  189. };
  190. static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {
  191. { .fw_name = "cxo", .name = "xo_board" },
  192. { .hw = &gpll0.clkr.hw },
  193. { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }
  194. };
  195. static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
  196. { P_XO, 0 },
  197. { P_GPLL0, 1 },
  198. { P_SLEEP_CLK, 5 },
  199. { P_GPLL0_EARLY_DIV, 6 }
  200. };
  201. static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
  202. { .fw_name = "cxo", .name = "xo_board" },
  203. { .hw = &gpll0.clkr.hw },
  204. { .fw_name = "sleep_clk", .name = "sleep_clk" },
  205. { .hw = &gpll0_early_div.hw }
  206. };
  207. static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
  208. { P_XO, 0 },
  209. { P_GPLL0, 1 },
  210. { P_GPLL4, 5 },
  211. { P_GPLL0_EARLY_DIV, 6 }
  212. };
  213. static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
  214. { .fw_name = "cxo", .name = "xo_board" },
  215. { .hw = &gpll0.clkr.hw },
  216. { .hw = &gpll4.clkr.hw },
  217. { .hw = &gpll0_early_div.hw }
  218. };
  219. static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
  220. F(19200000, P_XO, 1, 0, 0),
  221. F(120000000, P_GPLL0, 5, 0, 0),
  222. F(150000000, P_GPLL0, 4, 0, 0),
  223. { }
  224. };
  225. static struct clk_rcg2 usb30_master_clk_src = {
  226. .cmd_rcgr = 0x0f014,
  227. .mnd_width = 8,
  228. .hid_width = 5,
  229. .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
  230. .freq_tbl = ftbl_usb30_master_clk_src,
  231. .clkr.hw.init = &(struct clk_init_data){
  232. .name = "usb30_master_clk_src",
  233. .parent_data = gcc_xo_gpll0_gpll0_early_div,
  234. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
  235. .ops = &clk_rcg2_ops,
  236. },
  237. };
  238. static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
  239. F(19200000, P_XO, 1, 0, 0),
  240. { }
  241. };
  242. static struct clk_rcg2 usb30_mock_utmi_clk_src = {
  243. .cmd_rcgr = 0x0f028,
  244. .hid_width = 5,
  245. .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
  246. .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
  247. .clkr.hw.init = &(struct clk_init_data){
  248. .name = "usb30_mock_utmi_clk_src",
  249. .parent_data = gcc_xo_gpll0_gpll0_early_div,
  250. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
  251. .ops = &clk_rcg2_ops,
  252. },
  253. };
  254. static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
  255. F(1200000, P_XO, 16, 0, 0),
  256. { }
  257. };
  258. static struct clk_rcg2 usb3_phy_aux_clk_src = {
  259. .cmd_rcgr = 0x5000c,
  260. .hid_width = 5,
  261. .parent_map = gcc_xo_sleep_clk_map,
  262. .freq_tbl = ftbl_usb3_phy_aux_clk_src,
  263. .clkr.hw.init = &(struct clk_init_data){
  264. .name = "usb3_phy_aux_clk_src",
  265. .parent_data = gcc_xo_sleep_clk,
  266. .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
  267. .ops = &clk_rcg2_ops,
  268. },
  269. };
  270. static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
  271. F(120000000, P_GPLL0, 5, 0, 0),
  272. { }
  273. };
  274. static struct clk_rcg2 usb20_master_clk_src = {
  275. .cmd_rcgr = 0x12010,
  276. .mnd_width = 8,
  277. .hid_width = 5,
  278. .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
  279. .freq_tbl = ftbl_usb20_master_clk_src,
  280. .clkr.hw.init = &(struct clk_init_data){
  281. .name = "usb20_master_clk_src",
  282. .parent_data = gcc_xo_gpll0_gpll0_early_div,
  283. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
  284. .ops = &clk_rcg2_ops,
  285. },
  286. };
  287. static struct clk_rcg2 usb20_mock_utmi_clk_src = {
  288. .cmd_rcgr = 0x12024,
  289. .hid_width = 5,
  290. .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
  291. .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
  292. .clkr.hw.init = &(struct clk_init_data){
  293. .name = "usb20_mock_utmi_clk_src",
  294. .parent_data = gcc_xo_gpll0_gpll0_early_div,
  295. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
  296. .ops = &clk_rcg2_ops,
  297. },
  298. };
  299. static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
  300. F(144000, P_XO, 16, 3, 25),
  301. F(400000, P_XO, 12, 1, 4),
  302. F(20000000, P_GPLL0, 15, 1, 2),
  303. F(25000000, P_GPLL0, 12, 1, 2),
  304. F(50000000, P_GPLL0, 12, 0, 0),
  305. F(96000000, P_GPLL4, 4, 0, 0),
  306. F(192000000, P_GPLL4, 2, 0, 0),
  307. F(384000000, P_GPLL4, 1, 0, 0),
  308. { }
  309. };
  310. static struct clk_rcg2 sdcc1_apps_clk_src = {
  311. .cmd_rcgr = 0x13010,
  312. .mnd_width = 8,
  313. .hid_width = 5,
  314. .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
  315. .freq_tbl = ftbl_sdcc1_apps_clk_src,
  316. .clkr.hw.init = &(struct clk_init_data){
  317. .name = "sdcc1_apps_clk_src",
  318. .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
  319. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
  320. .ops = &clk_rcg2_floor_ops,
  321. },
  322. };
  323. static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
  324. F(19200000, P_XO, 1, 0, 0),
  325. F(150000000, P_GPLL0, 4, 0, 0),
  326. F(300000000, P_GPLL0, 2, 0, 0),
  327. { }
  328. };
  329. static struct clk_rcg2 sdcc1_ice_core_clk_src = {
  330. .cmd_rcgr = 0x13024,
  331. .hid_width = 5,
  332. .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
  333. .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
  334. .clkr.hw.init = &(struct clk_init_data){
  335. .name = "sdcc1_ice_core_clk_src",
  336. .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
  337. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
  338. .ops = &clk_rcg2_ops,
  339. },
  340. };
  341. static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
  342. F(144000, P_XO, 16, 3, 25),
  343. F(400000, P_XO, 12, 1, 4),
  344. F(20000000, P_GPLL0, 15, 1, 2),
  345. F(25000000, P_GPLL0, 12, 1, 2),
  346. F(50000000, P_GPLL0, 12, 0, 0),
  347. F(100000000, P_GPLL0, 6, 0, 0),
  348. F(200000000, P_GPLL0, 3, 0, 0),
  349. { }
  350. };
  351. static struct clk_rcg2 sdcc2_apps_clk_src = {
  352. .cmd_rcgr = 0x14010,
  353. .mnd_width = 8,
  354. .hid_width = 5,
  355. .parent_map = gcc_xo_gpll0_gpll4_map,
  356. .freq_tbl = ftbl_sdcc2_apps_clk_src,
  357. .clkr.hw.init = &(struct clk_init_data){
  358. .name = "sdcc2_apps_clk_src",
  359. .parent_data = gcc_xo_gpll0_gpll4,
  360. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
  361. .ops = &clk_rcg2_floor_ops,
  362. },
  363. };
  364. static struct clk_rcg2 sdcc3_apps_clk_src = {
  365. .cmd_rcgr = 0x15010,
  366. .mnd_width = 8,
  367. .hid_width = 5,
  368. .parent_map = gcc_xo_gpll0_gpll4_map,
  369. .freq_tbl = ftbl_sdcc2_apps_clk_src,
  370. .clkr.hw.init = &(struct clk_init_data){
  371. .name = "sdcc3_apps_clk_src",
  372. .parent_data = gcc_xo_gpll0_gpll4,
  373. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
  374. .ops = &clk_rcg2_floor_ops,
  375. },
  376. };
  377. static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
  378. F(144000, P_XO, 16, 3, 25),
  379. F(400000, P_XO, 12, 1, 4),
  380. F(20000000, P_GPLL0, 15, 1, 2),
  381. F(25000000, P_GPLL0, 12, 1, 2),
  382. F(50000000, P_GPLL0, 12, 0, 0),
  383. F(100000000, P_GPLL0, 6, 0, 0),
  384. { }
  385. };
  386. static struct clk_rcg2 sdcc4_apps_clk_src = {
  387. .cmd_rcgr = 0x16010,
  388. .mnd_width = 8,
  389. .hid_width = 5,
  390. .parent_map = gcc_xo_gpll0_map,
  391. .freq_tbl = ftbl_sdcc4_apps_clk_src,
  392. .clkr.hw.init = &(struct clk_init_data){
  393. .name = "sdcc4_apps_clk_src",
  394. .parent_data = gcc_xo_gpll0,
  395. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  396. .ops = &clk_rcg2_floor_ops,
  397. },
  398. };
  399. static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
  400. F(960000, P_XO, 10, 1, 2),
  401. F(4800000, P_XO, 4, 0, 0),
  402. F(9600000, P_XO, 2, 0, 0),
  403. F(15000000, P_GPLL0, 10, 1, 4),
  404. F(19200000, P_XO, 1, 0, 0),
  405. F(25000000, P_GPLL0, 12, 1, 2),
  406. F(50000000, P_GPLL0, 12, 0, 0),
  407. { }
  408. };
  409. static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
  410. .cmd_rcgr = 0x1900c,
  411. .mnd_width = 8,
  412. .hid_width = 5,
  413. .parent_map = gcc_xo_gpll0_map,
  414. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  415. .clkr.hw.init = &(struct clk_init_data){
  416. .name = "blsp1_qup1_spi_apps_clk_src",
  417. .parent_data = gcc_xo_gpll0,
  418. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  419. .ops = &clk_rcg2_ops,
  420. },
  421. };
  422. static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
  423. F(19200000, P_XO, 1, 0, 0),
  424. F(50000000, P_GPLL0, 12, 0, 0),
  425. { }
  426. };
  427. static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
  428. .cmd_rcgr = 0x19020,
  429. .hid_width = 5,
  430. .parent_map = gcc_xo_gpll0_map,
  431. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  432. .clkr.hw.init = &(struct clk_init_data){
  433. .name = "blsp1_qup1_i2c_apps_clk_src",
  434. .parent_data = gcc_xo_gpll0,
  435. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  436. .ops = &clk_rcg2_ops,
  437. },
  438. };
  439. static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
  440. F(3686400, P_GPLL0, 1, 96, 15625),
  441. F(7372800, P_GPLL0, 1, 192, 15625),
  442. F(14745600, P_GPLL0, 1, 384, 15625),
  443. F(16000000, P_GPLL0, 5, 2, 15),
  444. F(19200000, P_XO, 1, 0, 0),
  445. F(24000000, P_GPLL0, 5, 1, 5),
  446. F(32000000, P_GPLL0, 1, 4, 75),
  447. F(40000000, P_GPLL0, 15, 0, 0),
  448. F(46400000, P_GPLL0, 1, 29, 375),
  449. F(48000000, P_GPLL0, 12.5, 0, 0),
  450. F(51200000, P_GPLL0, 1, 32, 375),
  451. F(56000000, P_GPLL0, 1, 7, 75),
  452. F(58982400, P_GPLL0, 1, 1536, 15625),
  453. F(60000000, P_GPLL0, 10, 0, 0),
  454. F(63157895, P_GPLL0, 9.5, 0, 0),
  455. { }
  456. };
  457. static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
  458. .cmd_rcgr = 0x1a00c,
  459. .mnd_width = 16,
  460. .hid_width = 5,
  461. .parent_map = gcc_xo_gpll0_map,
  462. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  463. .clkr.hw.init = &(struct clk_init_data){
  464. .name = "blsp1_uart1_apps_clk_src",
  465. .parent_data = gcc_xo_gpll0,
  466. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  467. .ops = &clk_rcg2_ops,
  468. },
  469. };
  470. static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
  471. .cmd_rcgr = 0x1b00c,
  472. .mnd_width = 8,
  473. .hid_width = 5,
  474. .parent_map = gcc_xo_gpll0_map,
  475. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  476. .clkr.hw.init = &(struct clk_init_data){
  477. .name = "blsp1_qup2_spi_apps_clk_src",
  478. .parent_data = gcc_xo_gpll0,
  479. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  480. .ops = &clk_rcg2_ops,
  481. },
  482. };
  483. static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
  484. .cmd_rcgr = 0x1b020,
  485. .hid_width = 5,
  486. .parent_map = gcc_xo_gpll0_map,
  487. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  488. .clkr.hw.init = &(struct clk_init_data){
  489. .name = "blsp1_qup2_i2c_apps_clk_src",
  490. .parent_data = gcc_xo_gpll0,
  491. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  492. .ops = &clk_rcg2_ops,
  493. },
  494. };
  495. static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
  496. .cmd_rcgr = 0x1c00c,
  497. .mnd_width = 16,
  498. .hid_width = 5,
  499. .parent_map = gcc_xo_gpll0_map,
  500. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  501. .clkr.hw.init = &(struct clk_init_data){
  502. .name = "blsp1_uart2_apps_clk_src",
  503. .parent_data = gcc_xo_gpll0,
  504. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  505. .ops = &clk_rcg2_ops,
  506. },
  507. };
  508. static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
  509. .cmd_rcgr = 0x1d00c,
  510. .mnd_width = 8,
  511. .hid_width = 5,
  512. .parent_map = gcc_xo_gpll0_map,
  513. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  514. .clkr.hw.init = &(struct clk_init_data){
  515. .name = "blsp1_qup3_spi_apps_clk_src",
  516. .parent_data = gcc_xo_gpll0,
  517. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  518. .ops = &clk_rcg2_ops,
  519. },
  520. };
  521. static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
  522. .cmd_rcgr = 0x1d020,
  523. .hid_width = 5,
  524. .parent_map = gcc_xo_gpll0_map,
  525. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  526. .clkr.hw.init = &(struct clk_init_data){
  527. .name = "blsp1_qup3_i2c_apps_clk_src",
  528. .parent_data = gcc_xo_gpll0,
  529. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  530. .ops = &clk_rcg2_ops,
  531. },
  532. };
  533. static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
  534. .cmd_rcgr = 0x1e00c,
  535. .mnd_width = 16,
  536. .hid_width = 5,
  537. .parent_map = gcc_xo_gpll0_map,
  538. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  539. .clkr.hw.init = &(struct clk_init_data){
  540. .name = "blsp1_uart3_apps_clk_src",
  541. .parent_data = gcc_xo_gpll0,
  542. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  543. .ops = &clk_rcg2_ops,
  544. },
  545. };
  546. static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
  547. .cmd_rcgr = 0x1f00c,
  548. .mnd_width = 8,
  549. .hid_width = 5,
  550. .parent_map = gcc_xo_gpll0_map,
  551. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  552. .clkr.hw.init = &(struct clk_init_data){
  553. .name = "blsp1_qup4_spi_apps_clk_src",
  554. .parent_data = gcc_xo_gpll0,
  555. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  556. .ops = &clk_rcg2_ops,
  557. },
  558. };
  559. static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
  560. .cmd_rcgr = 0x1f020,
  561. .hid_width = 5,
  562. .parent_map = gcc_xo_gpll0_map,
  563. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  564. .clkr.hw.init = &(struct clk_init_data){
  565. .name = "blsp1_qup4_i2c_apps_clk_src",
  566. .parent_data = gcc_xo_gpll0,
  567. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  568. .ops = &clk_rcg2_ops,
  569. },
  570. };
  571. static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
  572. .cmd_rcgr = 0x2000c,
  573. .mnd_width = 16,
  574. .hid_width = 5,
  575. .parent_map = gcc_xo_gpll0_map,
  576. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  577. .clkr.hw.init = &(struct clk_init_data){
  578. .name = "blsp1_uart4_apps_clk_src",
  579. .parent_data = gcc_xo_gpll0,
  580. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  581. .ops = &clk_rcg2_ops,
  582. },
  583. };
  584. static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
  585. .cmd_rcgr = 0x2100c,
  586. .mnd_width = 8,
  587. .hid_width = 5,
  588. .parent_map = gcc_xo_gpll0_map,
  589. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  590. .clkr.hw.init = &(struct clk_init_data){
  591. .name = "blsp1_qup5_spi_apps_clk_src",
  592. .parent_data = gcc_xo_gpll0,
  593. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  594. .ops = &clk_rcg2_ops,
  595. },
  596. };
  597. static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
  598. .cmd_rcgr = 0x21020,
  599. .hid_width = 5,
  600. .parent_map = gcc_xo_gpll0_map,
  601. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  602. .clkr.hw.init = &(struct clk_init_data){
  603. .name = "blsp1_qup5_i2c_apps_clk_src",
  604. .parent_data = gcc_xo_gpll0,
  605. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  606. .ops = &clk_rcg2_ops,
  607. },
  608. };
  609. static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
  610. .cmd_rcgr = 0x2200c,
  611. .mnd_width = 16,
  612. .hid_width = 5,
  613. .parent_map = gcc_xo_gpll0_map,
  614. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  615. .clkr.hw.init = &(struct clk_init_data){
  616. .name = "blsp1_uart5_apps_clk_src",
  617. .parent_data = gcc_xo_gpll0,
  618. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  619. .ops = &clk_rcg2_ops,
  620. },
  621. };
  622. static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
  623. .cmd_rcgr = 0x2300c,
  624. .mnd_width = 8,
  625. .hid_width = 5,
  626. .parent_map = gcc_xo_gpll0_map,
  627. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  628. .clkr.hw.init = &(struct clk_init_data){
  629. .name = "blsp1_qup6_spi_apps_clk_src",
  630. .parent_data = gcc_xo_gpll0,
  631. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  632. .ops = &clk_rcg2_ops,
  633. },
  634. };
  635. static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
  636. .cmd_rcgr = 0x23020,
  637. .hid_width = 5,
  638. .parent_map = gcc_xo_gpll0_map,
  639. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  640. .clkr.hw.init = &(struct clk_init_data){
  641. .name = "blsp1_qup6_i2c_apps_clk_src",
  642. .parent_data = gcc_xo_gpll0,
  643. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  644. .ops = &clk_rcg2_ops,
  645. },
  646. };
  647. static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
  648. .cmd_rcgr = 0x2400c,
  649. .mnd_width = 16,
  650. .hid_width = 5,
  651. .parent_map = gcc_xo_gpll0_map,
  652. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  653. .clkr.hw.init = &(struct clk_init_data){
  654. .name = "blsp1_uart6_apps_clk_src",
  655. .parent_data = gcc_xo_gpll0,
  656. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  657. .ops = &clk_rcg2_ops,
  658. },
  659. };
  660. static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
  661. .cmd_rcgr = 0x2600c,
  662. .mnd_width = 8,
  663. .hid_width = 5,
  664. .parent_map = gcc_xo_gpll0_map,
  665. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  666. .clkr.hw.init = &(struct clk_init_data){
  667. .name = "blsp2_qup1_spi_apps_clk_src",
  668. .parent_data = gcc_xo_gpll0,
  669. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  670. .ops = &clk_rcg2_ops,
  671. },
  672. };
  673. static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
  674. .cmd_rcgr = 0x26020,
  675. .hid_width = 5,
  676. .parent_map = gcc_xo_gpll0_map,
  677. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  678. .clkr.hw.init = &(struct clk_init_data){
  679. .name = "blsp2_qup1_i2c_apps_clk_src",
  680. .parent_data = gcc_xo_gpll0,
  681. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  682. .ops = &clk_rcg2_ops,
  683. },
  684. };
  685. static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
  686. .cmd_rcgr = 0x2700c,
  687. .mnd_width = 16,
  688. .hid_width = 5,
  689. .parent_map = gcc_xo_gpll0_map,
  690. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  691. .clkr.hw.init = &(struct clk_init_data){
  692. .name = "blsp2_uart1_apps_clk_src",
  693. .parent_data = gcc_xo_gpll0,
  694. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  695. .ops = &clk_rcg2_ops,
  696. },
  697. };
  698. static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
  699. .cmd_rcgr = 0x2800c,
  700. .mnd_width = 8,
  701. .hid_width = 5,
  702. .parent_map = gcc_xo_gpll0_map,
  703. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  704. .clkr.hw.init = &(struct clk_init_data){
  705. .name = "blsp2_qup2_spi_apps_clk_src",
  706. .parent_data = gcc_xo_gpll0,
  707. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  708. .ops = &clk_rcg2_ops,
  709. },
  710. };
  711. static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
  712. .cmd_rcgr = 0x28020,
  713. .hid_width = 5,
  714. .parent_map = gcc_xo_gpll0_map,
  715. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  716. .clkr.hw.init = &(struct clk_init_data){
  717. .name = "blsp2_qup2_i2c_apps_clk_src",
  718. .parent_data = gcc_xo_gpll0,
  719. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  720. .ops = &clk_rcg2_ops,
  721. },
  722. };
  723. static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
  724. .cmd_rcgr = 0x2900c,
  725. .mnd_width = 16,
  726. .hid_width = 5,
  727. .parent_map = gcc_xo_gpll0_map,
  728. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  729. .clkr.hw.init = &(struct clk_init_data){
  730. .name = "blsp2_uart2_apps_clk_src",
  731. .parent_data = gcc_xo_gpll0,
  732. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  733. .ops = &clk_rcg2_ops,
  734. },
  735. };
  736. static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
  737. .cmd_rcgr = 0x2a00c,
  738. .mnd_width = 8,
  739. .hid_width = 5,
  740. .parent_map = gcc_xo_gpll0_map,
  741. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  742. .clkr.hw.init = &(struct clk_init_data){
  743. .name = "blsp2_qup3_spi_apps_clk_src",
  744. .parent_data = gcc_xo_gpll0,
  745. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  746. .ops = &clk_rcg2_ops,
  747. },
  748. };
  749. static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
  750. .cmd_rcgr = 0x2a020,
  751. .hid_width = 5,
  752. .parent_map = gcc_xo_gpll0_map,
  753. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  754. .clkr.hw.init = &(struct clk_init_data){
  755. .name = "blsp2_qup3_i2c_apps_clk_src",
  756. .parent_data = gcc_xo_gpll0,
  757. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  758. .ops = &clk_rcg2_ops,
  759. },
  760. };
  761. static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
  762. .cmd_rcgr = 0x2b00c,
  763. .mnd_width = 16,
  764. .hid_width = 5,
  765. .parent_map = gcc_xo_gpll0_map,
  766. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  767. .clkr.hw.init = &(struct clk_init_data){
  768. .name = "blsp2_uart3_apps_clk_src",
  769. .parent_data = gcc_xo_gpll0,
  770. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  771. .ops = &clk_rcg2_ops,
  772. },
  773. };
  774. static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
  775. .cmd_rcgr = 0x2c00c,
  776. .mnd_width = 8,
  777. .hid_width = 5,
  778. .parent_map = gcc_xo_gpll0_map,
  779. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  780. .clkr.hw.init = &(struct clk_init_data){
  781. .name = "blsp2_qup4_spi_apps_clk_src",
  782. .parent_data = gcc_xo_gpll0,
  783. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  784. .ops = &clk_rcg2_ops,
  785. },
  786. };
  787. static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
  788. .cmd_rcgr = 0x2c020,
  789. .hid_width = 5,
  790. .parent_map = gcc_xo_gpll0_map,
  791. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  792. .clkr.hw.init = &(struct clk_init_data){
  793. .name = "blsp2_qup4_i2c_apps_clk_src",
  794. .parent_data = gcc_xo_gpll0,
  795. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  796. .ops = &clk_rcg2_ops,
  797. },
  798. };
  799. static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
  800. .cmd_rcgr = 0x2d00c,
  801. .mnd_width = 16,
  802. .hid_width = 5,
  803. .parent_map = gcc_xo_gpll0_map,
  804. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  805. .clkr.hw.init = &(struct clk_init_data){
  806. .name = "blsp2_uart4_apps_clk_src",
  807. .parent_data = gcc_xo_gpll0,
  808. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  809. .ops = &clk_rcg2_ops,
  810. },
  811. };
  812. static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
  813. .cmd_rcgr = 0x2e00c,
  814. .mnd_width = 8,
  815. .hid_width = 5,
  816. .parent_map = gcc_xo_gpll0_map,
  817. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  818. .clkr.hw.init = &(struct clk_init_data){
  819. .name = "blsp2_qup5_spi_apps_clk_src",
  820. .parent_data = gcc_xo_gpll0,
  821. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  822. .ops = &clk_rcg2_ops,
  823. },
  824. };
  825. static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
  826. .cmd_rcgr = 0x2e020,
  827. .hid_width = 5,
  828. .parent_map = gcc_xo_gpll0_map,
  829. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  830. .clkr.hw.init = &(struct clk_init_data){
  831. .name = "blsp2_qup5_i2c_apps_clk_src",
  832. .parent_data = gcc_xo_gpll0,
  833. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  834. .ops = &clk_rcg2_ops,
  835. },
  836. };
  837. static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
  838. .cmd_rcgr = 0x2f00c,
  839. .mnd_width = 16,
  840. .hid_width = 5,
  841. .parent_map = gcc_xo_gpll0_map,
  842. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  843. .clkr.hw.init = &(struct clk_init_data){
  844. .name = "blsp2_uart5_apps_clk_src",
  845. .parent_data = gcc_xo_gpll0,
  846. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  847. .ops = &clk_rcg2_ops,
  848. },
  849. };
  850. static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
  851. .cmd_rcgr = 0x3000c,
  852. .mnd_width = 8,
  853. .hid_width = 5,
  854. .parent_map = gcc_xo_gpll0_map,
  855. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  856. .clkr.hw.init = &(struct clk_init_data){
  857. .name = "blsp2_qup6_spi_apps_clk_src",
  858. .parent_data = gcc_xo_gpll0,
  859. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  860. .ops = &clk_rcg2_ops,
  861. },
  862. };
  863. static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
  864. .cmd_rcgr = 0x30020,
  865. .hid_width = 5,
  866. .parent_map = gcc_xo_gpll0_map,
  867. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  868. .clkr.hw.init = &(struct clk_init_data){
  869. .name = "blsp2_qup6_i2c_apps_clk_src",
  870. .parent_data = gcc_xo_gpll0,
  871. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  872. .ops = &clk_rcg2_ops,
  873. },
  874. };
  875. static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
  876. .cmd_rcgr = 0x3100c,
  877. .mnd_width = 16,
  878. .hid_width = 5,
  879. .parent_map = gcc_xo_gpll0_map,
  880. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  881. .clkr.hw.init = &(struct clk_init_data){
  882. .name = "blsp2_uart6_apps_clk_src",
  883. .parent_data = gcc_xo_gpll0,
  884. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  885. .ops = &clk_rcg2_ops,
  886. },
  887. };
  888. static const struct freq_tbl ftbl_pdm2_clk_src[] = {
  889. F(60000000, P_GPLL0, 10, 0, 0),
  890. { }
  891. };
  892. static struct clk_rcg2 pdm2_clk_src = {
  893. .cmd_rcgr = 0x33010,
  894. .hid_width = 5,
  895. .parent_map = gcc_xo_gpll0_map,
  896. .freq_tbl = ftbl_pdm2_clk_src,
  897. .clkr.hw.init = &(struct clk_init_data){
  898. .name = "pdm2_clk_src",
  899. .parent_data = gcc_xo_gpll0,
  900. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  901. .ops = &clk_rcg2_ops,
  902. },
  903. };
  904. static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
  905. F(105495, P_XO, 1, 1, 182),
  906. { }
  907. };
  908. static struct clk_rcg2 tsif_ref_clk_src = {
  909. .cmd_rcgr = 0x36010,
  910. .mnd_width = 8,
  911. .hid_width = 5,
  912. .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
  913. .freq_tbl = ftbl_tsif_ref_clk_src,
  914. .clkr.hw.init = &(struct clk_init_data){
  915. .name = "tsif_ref_clk_src",
  916. .parent_data = gcc_xo_gpll0_aud_ref_clk,
  917. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),
  918. .ops = &clk_rcg2_ops,
  919. },
  920. };
  921. static struct clk_rcg2 gcc_sleep_clk_src = {
  922. .cmd_rcgr = 0x43014,
  923. .hid_width = 5,
  924. .parent_map = gcc_sleep_clk_map,
  925. .clkr.hw.init = &(struct clk_init_data){
  926. .name = "gcc_sleep_clk_src",
  927. .parent_data = gcc_sleep_clk,
  928. .num_parents = ARRAY_SIZE(gcc_sleep_clk),
  929. .ops = &clk_rcg2_ops,
  930. },
  931. };
  932. static struct clk_rcg2 hmss_rbcpr_clk_src = {
  933. .cmd_rcgr = 0x48040,
  934. .hid_width = 5,
  935. .parent_map = gcc_xo_gpll0_map,
  936. .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
  937. .clkr.hw.init = &(struct clk_init_data){
  938. .name = "hmss_rbcpr_clk_src",
  939. .parent_data = gcc_xo_gpll0,
  940. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  941. .ops = &clk_rcg2_ops,
  942. },
  943. };
  944. static struct clk_rcg2 hmss_gpll0_clk_src = {
  945. .cmd_rcgr = 0x48058,
  946. .hid_width = 5,
  947. .parent_map = gcc_xo_gpll0_map,
  948. .clkr.hw.init = &(struct clk_init_data){
  949. .name = "hmss_gpll0_clk_src",
  950. .parent_data = gcc_xo_gpll0,
  951. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  952. .ops = &clk_rcg2_ops,
  953. },
  954. };
  955. static const struct freq_tbl ftbl_gp1_clk_src[] = {
  956. F(19200000, P_XO, 1, 0, 0),
  957. F(100000000, P_GPLL0, 6, 0, 0),
  958. F(200000000, P_GPLL0, 3, 0, 0),
  959. { }
  960. };
  961. static struct clk_rcg2 gp1_clk_src = {
  962. .cmd_rcgr = 0x64004,
  963. .mnd_width = 8,
  964. .hid_width = 5,
  965. .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
  966. .freq_tbl = ftbl_gp1_clk_src,
  967. .clkr.hw.init = &(struct clk_init_data){
  968. .name = "gp1_clk_src",
  969. .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
  970. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
  971. .ops = &clk_rcg2_ops,
  972. },
  973. };
  974. static struct clk_rcg2 gp2_clk_src = {
  975. .cmd_rcgr = 0x65004,
  976. .mnd_width = 8,
  977. .hid_width = 5,
  978. .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
  979. .freq_tbl = ftbl_gp1_clk_src,
  980. .clkr.hw.init = &(struct clk_init_data){
  981. .name = "gp2_clk_src",
  982. .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
  983. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
  984. .ops = &clk_rcg2_ops,
  985. },
  986. };
  987. static struct clk_rcg2 gp3_clk_src = {
  988. .cmd_rcgr = 0x66004,
  989. .mnd_width = 8,
  990. .hid_width = 5,
  991. .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
  992. .freq_tbl = ftbl_gp1_clk_src,
  993. .clkr.hw.init = &(struct clk_init_data){
  994. .name = "gp3_clk_src",
  995. .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
  996. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
  997. .ops = &clk_rcg2_ops,
  998. },
  999. };
  1000. static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
  1001. F(1010526, P_XO, 1, 1, 19),
  1002. { }
  1003. };
  1004. static struct clk_rcg2 pcie_aux_clk_src = {
  1005. .cmd_rcgr = 0x6c000,
  1006. .mnd_width = 16,
  1007. .hid_width = 5,
  1008. .parent_map = gcc_xo_sleep_clk_map,
  1009. .freq_tbl = ftbl_pcie_aux_clk_src,
  1010. .clkr.hw.init = &(struct clk_init_data){
  1011. .name = "pcie_aux_clk_src",
  1012. .parent_data = gcc_xo_sleep_clk,
  1013. .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
  1014. .ops = &clk_rcg2_ops,
  1015. },
  1016. };
  1017. static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
  1018. F(100000000, P_GPLL0, 6, 0, 0),
  1019. F(200000000, P_GPLL0, 3, 0, 0),
  1020. F(240000000, P_GPLL0, 2.5, 0, 0),
  1021. { }
  1022. };
  1023. static struct clk_rcg2 ufs_axi_clk_src = {
  1024. .cmd_rcgr = 0x75024,
  1025. .mnd_width = 8,
  1026. .hid_width = 5,
  1027. .parent_map = gcc_xo_gpll0_map,
  1028. .freq_tbl = ftbl_ufs_axi_clk_src,
  1029. .clkr.hw.init = &(struct clk_init_data){
  1030. .name = "ufs_axi_clk_src",
  1031. .parent_data = gcc_xo_gpll0,
  1032. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  1033. .ops = &clk_rcg2_ops,
  1034. },
  1035. };
  1036. static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
  1037. F(19200000, P_XO, 1, 0, 0),
  1038. F(150000000, P_GPLL0, 4, 0, 0),
  1039. F(300000000, P_GPLL0, 2, 0, 0),
  1040. { }
  1041. };
  1042. static struct clk_rcg2 ufs_ice_core_clk_src = {
  1043. .cmd_rcgr = 0x76014,
  1044. .hid_width = 5,
  1045. .parent_map = gcc_xo_gpll0_map,
  1046. .freq_tbl = ftbl_ufs_ice_core_clk_src,
  1047. .clkr.hw.init = &(struct clk_init_data){
  1048. .name = "ufs_ice_core_clk_src",
  1049. .parent_data = gcc_xo_gpll0,
  1050. .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
  1051. .ops = &clk_rcg2_ops,
  1052. },
  1053. };
  1054. static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
  1055. F(75000000, P_GPLL0, 8, 0, 0),
  1056. F(150000000, P_GPLL0, 4, 0, 0),
  1057. F(256000000, P_GPLL4, 1.5, 0, 0),
  1058. F(300000000, P_GPLL0, 2, 0, 0),
  1059. { }
  1060. };
  1061. static struct clk_rcg2 qspi_ser_clk_src = {
  1062. .cmd_rcgr = 0x8b00c,
  1063. .hid_width = 5,
  1064. .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
  1065. .freq_tbl = ftbl_qspi_ser_clk_src,
  1066. .clkr.hw.init = &(struct clk_init_data){
  1067. .name = "qspi_ser_clk_src",
  1068. .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
  1069. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
  1070. .ops = &clk_rcg2_ops,
  1071. },
  1072. };
  1073. static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
  1074. .halt_reg = 0x0f03c,
  1075. .clkr = {
  1076. .enable_reg = 0x0f03c,
  1077. .enable_mask = BIT(0),
  1078. .hw.init = &(struct clk_init_data){
  1079. .name = "gcc_sys_noc_usb3_axi_clk",
  1080. .parent_hws = (const struct clk_hw*[]){
  1081. &usb30_master_clk_src.clkr.hw,
  1082. },
  1083. .num_parents = 1,
  1084. .flags = CLK_SET_RATE_PARENT,
  1085. .ops = &clk_branch2_ops,
  1086. },
  1087. },
  1088. };
  1089. static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
  1090. .halt_reg = 0x75038,
  1091. .clkr = {
  1092. .enable_reg = 0x75038,
  1093. .enable_mask = BIT(0),
  1094. .hw.init = &(struct clk_init_data){
  1095. .name = "gcc_sys_noc_ufs_axi_clk",
  1096. .parent_hws = (const struct clk_hw*[]){
  1097. &ufs_axi_clk_src.clkr.hw,
  1098. },
  1099. .num_parents = 1,
  1100. .flags = CLK_SET_RATE_PARENT,
  1101. .ops = &clk_branch2_ops,
  1102. },
  1103. },
  1104. };
  1105. static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
  1106. .halt_reg = 0x6010,
  1107. .clkr = {
  1108. .enable_reg = 0x6010,
  1109. .enable_mask = BIT(0),
  1110. .hw.init = &(struct clk_init_data){
  1111. .name = "gcc_periph_noc_usb20_ahb_clk",
  1112. .parent_hws = (const struct clk_hw*[]){
  1113. &usb20_master_clk_src.clkr.hw,
  1114. },
  1115. .num_parents = 1,
  1116. .flags = CLK_SET_RATE_PARENT,
  1117. .ops = &clk_branch2_ops,
  1118. },
  1119. },
  1120. };
  1121. static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
  1122. .halt_reg = 0x9008,
  1123. .clkr = {
  1124. .enable_reg = 0x9008,
  1125. .enable_mask = BIT(0),
  1126. .hw.init = &(struct clk_init_data){
  1127. .name = "gcc_mmss_noc_cfg_ahb_clk",
  1128. .flags = CLK_IGNORE_UNUSED,
  1129. .ops = &clk_branch2_ops,
  1130. },
  1131. },
  1132. };
  1133. static struct clk_branch gcc_mmss_bimc_gfx_clk = {
  1134. .halt_reg = 0x9010,
  1135. .clkr = {
  1136. .enable_reg = 0x9010,
  1137. .enable_mask = BIT(0),
  1138. .hw.init = &(struct clk_init_data){
  1139. .name = "gcc_mmss_bimc_gfx_clk",
  1140. .flags = CLK_SET_RATE_PARENT,
  1141. .ops = &clk_branch2_ops,
  1142. },
  1143. },
  1144. };
  1145. static struct clk_branch gcc_usb30_master_clk = {
  1146. .halt_reg = 0x0f008,
  1147. .clkr = {
  1148. .enable_reg = 0x0f008,
  1149. .enable_mask = BIT(0),
  1150. .hw.init = &(struct clk_init_data){
  1151. .name = "gcc_usb30_master_clk",
  1152. .parent_hws = (const struct clk_hw*[]){
  1153. &usb30_master_clk_src.clkr.hw,
  1154. },
  1155. .num_parents = 1,
  1156. .flags = CLK_SET_RATE_PARENT,
  1157. .ops = &clk_branch2_ops,
  1158. },
  1159. },
  1160. };
  1161. static struct clk_branch gcc_usb30_sleep_clk = {
  1162. .halt_reg = 0x0f00c,
  1163. .clkr = {
  1164. .enable_reg = 0x0f00c,
  1165. .enable_mask = BIT(0),
  1166. .hw.init = &(struct clk_init_data){
  1167. .name = "gcc_usb30_sleep_clk",
  1168. .parent_hws = (const struct clk_hw*[]){
  1169. &gcc_sleep_clk_src.clkr.hw,
  1170. },
  1171. .num_parents = 1,
  1172. .flags = CLK_SET_RATE_PARENT,
  1173. .ops = &clk_branch2_ops,
  1174. },
  1175. },
  1176. };
  1177. static struct clk_branch gcc_usb30_mock_utmi_clk = {
  1178. .halt_reg = 0x0f010,
  1179. .clkr = {
  1180. .enable_reg = 0x0f010,
  1181. .enable_mask = BIT(0),
  1182. .hw.init = &(struct clk_init_data){
  1183. .name = "gcc_usb30_mock_utmi_clk",
  1184. .parent_hws = (const struct clk_hw*[]){
  1185. &usb30_mock_utmi_clk_src.clkr.hw,
  1186. },
  1187. .num_parents = 1,
  1188. .flags = CLK_SET_RATE_PARENT,
  1189. .ops = &clk_branch2_ops,
  1190. },
  1191. },
  1192. };
  1193. static struct clk_branch gcc_usb3_phy_aux_clk = {
  1194. .halt_reg = 0x50000,
  1195. .clkr = {
  1196. .enable_reg = 0x50000,
  1197. .enable_mask = BIT(0),
  1198. .hw.init = &(struct clk_init_data){
  1199. .name = "gcc_usb3_phy_aux_clk",
  1200. .parent_hws = (const struct clk_hw*[]){
  1201. &usb3_phy_aux_clk_src.clkr.hw,
  1202. },
  1203. .num_parents = 1,
  1204. .flags = CLK_SET_RATE_PARENT,
  1205. .ops = &clk_branch2_ops,
  1206. },
  1207. },
  1208. };
  1209. static struct clk_branch gcc_usb3_phy_pipe_clk = {
  1210. .halt_reg = 0x50004,
  1211. .halt_check = BRANCH_HALT_SKIP,
  1212. .clkr = {
  1213. .enable_reg = 0x50004,
  1214. .enable_mask = BIT(0),
  1215. .hw.init = &(struct clk_init_data){
  1216. .name = "gcc_usb3_phy_pipe_clk",
  1217. .parent_data = &(const struct clk_parent_data){
  1218. .fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src",
  1219. },
  1220. .num_parents = 1,
  1221. .flags = CLK_SET_RATE_PARENT,
  1222. .ops = &clk_branch2_ops,
  1223. },
  1224. },
  1225. };
  1226. static struct clk_branch gcc_usb20_master_clk = {
  1227. .halt_reg = 0x12004,
  1228. .clkr = {
  1229. .enable_reg = 0x12004,
  1230. .enable_mask = BIT(0),
  1231. .hw.init = &(struct clk_init_data){
  1232. .name = "gcc_usb20_master_clk",
  1233. .parent_hws = (const struct clk_hw*[]){
  1234. &usb20_master_clk_src.clkr.hw,
  1235. },
  1236. .num_parents = 1,
  1237. .flags = CLK_SET_RATE_PARENT,
  1238. .ops = &clk_branch2_ops,
  1239. },
  1240. },
  1241. };
  1242. static struct clk_branch gcc_usb20_sleep_clk = {
  1243. .halt_reg = 0x12008,
  1244. .clkr = {
  1245. .enable_reg = 0x12008,
  1246. .enable_mask = BIT(0),
  1247. .hw.init = &(struct clk_init_data){
  1248. .name = "gcc_usb20_sleep_clk",
  1249. .parent_hws = (const struct clk_hw*[]){
  1250. &gcc_sleep_clk_src.clkr.hw,
  1251. },
  1252. .num_parents = 1,
  1253. .flags = CLK_SET_RATE_PARENT,
  1254. .ops = &clk_branch2_ops,
  1255. },
  1256. },
  1257. };
  1258. static struct clk_branch gcc_usb20_mock_utmi_clk = {
  1259. .halt_reg = 0x1200c,
  1260. .clkr = {
  1261. .enable_reg = 0x1200c,
  1262. .enable_mask = BIT(0),
  1263. .hw.init = &(struct clk_init_data){
  1264. .name = "gcc_usb20_mock_utmi_clk",
  1265. .parent_hws = (const struct clk_hw*[]){
  1266. &usb20_mock_utmi_clk_src.clkr.hw,
  1267. },
  1268. .num_parents = 1,
  1269. .flags = CLK_SET_RATE_PARENT,
  1270. .ops = &clk_branch2_ops,
  1271. },
  1272. },
  1273. };
  1274. static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
  1275. .halt_reg = 0x6a004,
  1276. .clkr = {
  1277. .enable_reg = 0x6a004,
  1278. .enable_mask = BIT(0),
  1279. .hw.init = &(struct clk_init_data){
  1280. .name = "gcc_usb_phy_cfg_ahb2phy_clk",
  1281. .ops = &clk_branch2_ops,
  1282. },
  1283. },
  1284. };
  1285. static struct clk_branch gcc_sdcc1_apps_clk = {
  1286. .halt_reg = 0x13004,
  1287. .clkr = {
  1288. .enable_reg = 0x13004,
  1289. .enable_mask = BIT(0),
  1290. .hw.init = &(struct clk_init_data){
  1291. .name = "gcc_sdcc1_apps_clk",
  1292. .parent_hws = (const struct clk_hw*[]){
  1293. &sdcc1_apps_clk_src.clkr.hw,
  1294. },
  1295. .num_parents = 1,
  1296. .flags = CLK_SET_RATE_PARENT,
  1297. .ops = &clk_branch2_ops,
  1298. },
  1299. },
  1300. };
  1301. static struct clk_branch gcc_sdcc1_ahb_clk = {
  1302. .halt_reg = 0x13008,
  1303. .clkr = {
  1304. .enable_reg = 0x13008,
  1305. .enable_mask = BIT(0),
  1306. .hw.init = &(struct clk_init_data){
  1307. .name = "gcc_sdcc1_ahb_clk",
  1308. .ops = &clk_branch2_ops,
  1309. },
  1310. },
  1311. };
  1312. static struct clk_branch gcc_sdcc1_ice_core_clk = {
  1313. .halt_reg = 0x13038,
  1314. .clkr = {
  1315. .enable_reg = 0x13038,
  1316. .enable_mask = BIT(0),
  1317. .hw.init = &(struct clk_init_data){
  1318. .name = "gcc_sdcc1_ice_core_clk",
  1319. .parent_hws = (const struct clk_hw*[]){
  1320. &sdcc1_ice_core_clk_src.clkr.hw,
  1321. },
  1322. .num_parents = 1,
  1323. .flags = CLK_SET_RATE_PARENT,
  1324. .ops = &clk_branch2_ops,
  1325. },
  1326. },
  1327. };
  1328. static struct clk_branch gcc_sdcc2_apps_clk = {
  1329. .halt_reg = 0x14004,
  1330. .clkr = {
  1331. .enable_reg = 0x14004,
  1332. .enable_mask = BIT(0),
  1333. .hw.init = &(struct clk_init_data){
  1334. .name = "gcc_sdcc2_apps_clk",
  1335. .parent_hws = (const struct clk_hw*[]){
  1336. &sdcc2_apps_clk_src.clkr.hw,
  1337. },
  1338. .num_parents = 1,
  1339. .flags = CLK_SET_RATE_PARENT,
  1340. .ops = &clk_branch2_ops,
  1341. },
  1342. },
  1343. };
  1344. static struct clk_branch gcc_sdcc2_ahb_clk = {
  1345. .halt_reg = 0x14008,
  1346. .clkr = {
  1347. .enable_reg = 0x14008,
  1348. .enable_mask = BIT(0),
  1349. .hw.init = &(struct clk_init_data){
  1350. .name = "gcc_sdcc2_ahb_clk",
  1351. .ops = &clk_branch2_ops,
  1352. },
  1353. },
  1354. };
  1355. static struct clk_branch gcc_sdcc3_apps_clk = {
  1356. .halt_reg = 0x15004,
  1357. .clkr = {
  1358. .enable_reg = 0x15004,
  1359. .enable_mask = BIT(0),
  1360. .hw.init = &(struct clk_init_data){
  1361. .name = "gcc_sdcc3_apps_clk",
  1362. .parent_hws = (const struct clk_hw*[]){
  1363. &sdcc3_apps_clk_src.clkr.hw,
  1364. },
  1365. .num_parents = 1,
  1366. .flags = CLK_SET_RATE_PARENT,
  1367. .ops = &clk_branch2_ops,
  1368. },
  1369. },
  1370. };
  1371. static struct clk_branch gcc_sdcc3_ahb_clk = {
  1372. .halt_reg = 0x15008,
  1373. .clkr = {
  1374. .enable_reg = 0x15008,
  1375. .enable_mask = BIT(0),
  1376. .hw.init = &(struct clk_init_data){
  1377. .name = "gcc_sdcc3_ahb_clk",
  1378. .ops = &clk_branch2_ops,
  1379. },
  1380. },
  1381. };
  1382. static struct clk_branch gcc_sdcc4_apps_clk = {
  1383. .halt_reg = 0x16004,
  1384. .clkr = {
  1385. .enable_reg = 0x16004,
  1386. .enable_mask = BIT(0),
  1387. .hw.init = &(struct clk_init_data){
  1388. .name = "gcc_sdcc4_apps_clk",
  1389. .parent_hws = (const struct clk_hw*[]){
  1390. &sdcc4_apps_clk_src.clkr.hw,
  1391. },
  1392. .num_parents = 1,
  1393. .flags = CLK_SET_RATE_PARENT,
  1394. .ops = &clk_branch2_ops,
  1395. },
  1396. },
  1397. };
  1398. static struct clk_branch gcc_sdcc4_ahb_clk = {
  1399. .halt_reg = 0x16008,
  1400. .clkr = {
  1401. .enable_reg = 0x16008,
  1402. .enable_mask = BIT(0),
  1403. .hw.init = &(struct clk_init_data){
  1404. .name = "gcc_sdcc4_ahb_clk",
  1405. .ops = &clk_branch2_ops,
  1406. },
  1407. },
  1408. };
  1409. static struct clk_branch gcc_blsp1_ahb_clk = {
  1410. .halt_reg = 0x17004,
  1411. .halt_check = BRANCH_HALT_VOTED,
  1412. .clkr = {
  1413. .enable_reg = 0x52004,
  1414. .enable_mask = BIT(17),
  1415. .hw.init = &(struct clk_init_data){
  1416. .name = "gcc_blsp1_ahb_clk",
  1417. .ops = &clk_branch2_ops,
  1418. },
  1419. },
  1420. };
  1421. static struct clk_branch gcc_blsp1_sleep_clk = {
  1422. .halt_reg = 0x17008,
  1423. .halt_check = BRANCH_HALT_VOTED,
  1424. .clkr = {
  1425. .enable_reg = 0x52004,
  1426. .enable_mask = BIT(16),
  1427. .hw.init = &(struct clk_init_data){
  1428. .name = "gcc_blsp1_sleep_clk",
  1429. .parent_hws = (const struct clk_hw*[]){
  1430. &gcc_sleep_clk_src.clkr.hw,
  1431. },
  1432. .num_parents = 1,
  1433. .flags = CLK_SET_RATE_PARENT,
  1434. .ops = &clk_branch2_ops,
  1435. },
  1436. },
  1437. };
  1438. static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
  1439. .halt_reg = 0x19004,
  1440. .clkr = {
  1441. .enable_reg = 0x19004,
  1442. .enable_mask = BIT(0),
  1443. .hw.init = &(struct clk_init_data){
  1444. .name = "gcc_blsp1_qup1_spi_apps_clk",
  1445. .parent_hws = (const struct clk_hw*[]){
  1446. &blsp1_qup1_spi_apps_clk_src.clkr.hw,
  1447. },
  1448. .num_parents = 1,
  1449. .flags = CLK_SET_RATE_PARENT,
  1450. .ops = &clk_branch2_ops,
  1451. },
  1452. },
  1453. };
  1454. static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
  1455. .halt_reg = 0x19008,
  1456. .clkr = {
  1457. .enable_reg = 0x19008,
  1458. .enable_mask = BIT(0),
  1459. .hw.init = &(struct clk_init_data){
  1460. .name = "gcc_blsp1_qup1_i2c_apps_clk",
  1461. .parent_hws = (const struct clk_hw*[]){
  1462. &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
  1463. },
  1464. .num_parents = 1,
  1465. .flags = CLK_SET_RATE_PARENT,
  1466. .ops = &clk_branch2_ops,
  1467. },
  1468. },
  1469. };
  1470. static struct clk_branch gcc_blsp1_uart1_apps_clk = {
  1471. .halt_reg = 0x1a004,
  1472. .clkr = {
  1473. .enable_reg = 0x1a004,
  1474. .enable_mask = BIT(0),
  1475. .hw.init = &(struct clk_init_data){
  1476. .name = "gcc_blsp1_uart1_apps_clk",
  1477. .parent_hws = (const struct clk_hw*[]){
  1478. &blsp1_uart1_apps_clk_src.clkr.hw,
  1479. },
  1480. .num_parents = 1,
  1481. .flags = CLK_SET_RATE_PARENT,
  1482. .ops = &clk_branch2_ops,
  1483. },
  1484. },
  1485. };
  1486. static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
  1487. .halt_reg = 0x1b004,
  1488. .clkr = {
  1489. .enable_reg = 0x1b004,
  1490. .enable_mask = BIT(0),
  1491. .hw.init = &(struct clk_init_data){
  1492. .name = "gcc_blsp1_qup2_spi_apps_clk",
  1493. .parent_hws = (const struct clk_hw*[]){
  1494. &blsp1_qup2_spi_apps_clk_src.clkr.hw,
  1495. },
  1496. .num_parents = 1,
  1497. .flags = CLK_SET_RATE_PARENT,
  1498. .ops = &clk_branch2_ops,
  1499. },
  1500. },
  1501. };
  1502. static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
  1503. .halt_reg = 0x1b008,
  1504. .clkr = {
  1505. .enable_reg = 0x1b008,
  1506. .enable_mask = BIT(0),
  1507. .hw.init = &(struct clk_init_data){
  1508. .name = "gcc_blsp1_qup2_i2c_apps_clk",
  1509. .parent_hws = (const struct clk_hw*[]){
  1510. &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
  1511. },
  1512. .num_parents = 1,
  1513. .flags = CLK_SET_RATE_PARENT,
  1514. .ops = &clk_branch2_ops,
  1515. },
  1516. },
  1517. };
  1518. static struct clk_branch gcc_blsp1_uart2_apps_clk = {
  1519. .halt_reg = 0x1c004,
  1520. .clkr = {
  1521. .enable_reg = 0x1c004,
  1522. .enable_mask = BIT(0),
  1523. .hw.init = &(struct clk_init_data){
  1524. .name = "gcc_blsp1_uart2_apps_clk",
  1525. .parent_hws = (const struct clk_hw*[]){
  1526. &blsp1_uart2_apps_clk_src.clkr.hw,
  1527. },
  1528. .num_parents = 1,
  1529. .flags = CLK_SET_RATE_PARENT,
  1530. .ops = &clk_branch2_ops,
  1531. },
  1532. },
  1533. };
  1534. static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
  1535. .halt_reg = 0x1d004,
  1536. .clkr = {
  1537. .enable_reg = 0x1d004,
  1538. .enable_mask = BIT(0),
  1539. .hw.init = &(struct clk_init_data){
  1540. .name = "gcc_blsp1_qup3_spi_apps_clk",
  1541. .parent_hws = (const struct clk_hw*[]){
  1542. &blsp1_qup3_spi_apps_clk_src.clkr.hw,
  1543. },
  1544. .num_parents = 1,
  1545. .flags = CLK_SET_RATE_PARENT,
  1546. .ops = &clk_branch2_ops,
  1547. },
  1548. },
  1549. };
  1550. static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
  1551. .halt_reg = 0x1d008,
  1552. .clkr = {
  1553. .enable_reg = 0x1d008,
  1554. .enable_mask = BIT(0),
  1555. .hw.init = &(struct clk_init_data){
  1556. .name = "gcc_blsp1_qup3_i2c_apps_clk",
  1557. .parent_hws = (const struct clk_hw*[]){
  1558. &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
  1559. },
  1560. .num_parents = 1,
  1561. .flags = CLK_SET_RATE_PARENT,
  1562. .ops = &clk_branch2_ops,
  1563. },
  1564. },
  1565. };
  1566. static struct clk_branch gcc_blsp1_uart3_apps_clk = {
  1567. .halt_reg = 0x1e004,
  1568. .clkr = {
  1569. .enable_reg = 0x1e004,
  1570. .enable_mask = BIT(0),
  1571. .hw.init = &(struct clk_init_data){
  1572. .name = "gcc_blsp1_uart3_apps_clk",
  1573. .parent_hws = (const struct clk_hw*[]){
  1574. &blsp1_uart3_apps_clk_src.clkr.hw,
  1575. },
  1576. .num_parents = 1,
  1577. .flags = CLK_SET_RATE_PARENT,
  1578. .ops = &clk_branch2_ops,
  1579. },
  1580. },
  1581. };
  1582. static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
  1583. .halt_reg = 0x1f004,
  1584. .clkr = {
  1585. .enable_reg = 0x1f004,
  1586. .enable_mask = BIT(0),
  1587. .hw.init = &(struct clk_init_data){
  1588. .name = "gcc_blsp1_qup4_spi_apps_clk",
  1589. .parent_hws = (const struct clk_hw*[]){
  1590. &blsp1_qup4_spi_apps_clk_src.clkr.hw,
  1591. },
  1592. .num_parents = 1,
  1593. .flags = CLK_SET_RATE_PARENT,
  1594. .ops = &clk_branch2_ops,
  1595. },
  1596. },
  1597. };
  1598. static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
  1599. .halt_reg = 0x1f008,
  1600. .clkr = {
  1601. .enable_reg = 0x1f008,
  1602. .enable_mask = BIT(0),
  1603. .hw.init = &(struct clk_init_data){
  1604. .name = "gcc_blsp1_qup4_i2c_apps_clk",
  1605. .parent_hws = (const struct clk_hw*[]){
  1606. &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
  1607. },
  1608. .num_parents = 1,
  1609. .flags = CLK_SET_RATE_PARENT,
  1610. .ops = &clk_branch2_ops,
  1611. },
  1612. },
  1613. };
  1614. static struct clk_branch gcc_blsp1_uart4_apps_clk = {
  1615. .halt_reg = 0x20004,
  1616. .clkr = {
  1617. .enable_reg = 0x20004,
  1618. .enable_mask = BIT(0),
  1619. .hw.init = &(struct clk_init_data){
  1620. .name = "gcc_blsp1_uart4_apps_clk",
  1621. .parent_hws = (const struct clk_hw*[]){
  1622. &blsp1_uart4_apps_clk_src.clkr.hw,
  1623. },
  1624. .num_parents = 1,
  1625. .flags = CLK_SET_RATE_PARENT,
  1626. .ops = &clk_branch2_ops,
  1627. },
  1628. },
  1629. };
  1630. static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
  1631. .halt_reg = 0x21004,
  1632. .clkr = {
  1633. .enable_reg = 0x21004,
  1634. .enable_mask = BIT(0),
  1635. .hw.init = &(struct clk_init_data){
  1636. .name = "gcc_blsp1_qup5_spi_apps_clk",
  1637. .parent_hws = (const struct clk_hw*[]){
  1638. &blsp1_qup5_spi_apps_clk_src.clkr.hw,
  1639. },
  1640. .num_parents = 1,
  1641. .flags = CLK_SET_RATE_PARENT,
  1642. .ops = &clk_branch2_ops,
  1643. },
  1644. },
  1645. };
  1646. static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
  1647. .halt_reg = 0x21008,
  1648. .clkr = {
  1649. .enable_reg = 0x21008,
  1650. .enable_mask = BIT(0),
  1651. .hw.init = &(struct clk_init_data){
  1652. .name = "gcc_blsp1_qup5_i2c_apps_clk",
  1653. .parent_hws = (const struct clk_hw*[]){
  1654. &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
  1655. },
  1656. .num_parents = 1,
  1657. .flags = CLK_SET_RATE_PARENT,
  1658. .ops = &clk_branch2_ops,
  1659. },
  1660. },
  1661. };
  1662. static struct clk_branch gcc_blsp1_uart5_apps_clk = {
  1663. .halt_reg = 0x22004,
  1664. .clkr = {
  1665. .enable_reg = 0x22004,
  1666. .enable_mask = BIT(0),
  1667. .hw.init = &(struct clk_init_data){
  1668. .name = "gcc_blsp1_uart5_apps_clk",
  1669. .parent_hws = (const struct clk_hw*[]){
  1670. &blsp1_uart5_apps_clk_src.clkr.hw,
  1671. },
  1672. .num_parents = 1,
  1673. .flags = CLK_SET_RATE_PARENT,
  1674. .ops = &clk_branch2_ops,
  1675. },
  1676. },
  1677. };
  1678. static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
  1679. .halt_reg = 0x23004,
  1680. .clkr = {
  1681. .enable_reg = 0x23004,
  1682. .enable_mask = BIT(0),
  1683. .hw.init = &(struct clk_init_data){
  1684. .name = "gcc_blsp1_qup6_spi_apps_clk",
  1685. .parent_hws = (const struct clk_hw*[]){
  1686. &blsp1_qup6_spi_apps_clk_src.clkr.hw,
  1687. },
  1688. .num_parents = 1,
  1689. .flags = CLK_SET_RATE_PARENT,
  1690. .ops = &clk_branch2_ops,
  1691. },
  1692. },
  1693. };
  1694. static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
  1695. .halt_reg = 0x23008,
  1696. .clkr = {
  1697. .enable_reg = 0x23008,
  1698. .enable_mask = BIT(0),
  1699. .hw.init = &(struct clk_init_data){
  1700. .name = "gcc_blsp1_qup6_i2c_apps_clk",
  1701. .parent_hws = (const struct clk_hw*[]){
  1702. &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
  1703. },
  1704. .num_parents = 1,
  1705. .flags = CLK_SET_RATE_PARENT,
  1706. .ops = &clk_branch2_ops,
  1707. },
  1708. },
  1709. };
  1710. static struct clk_branch gcc_blsp1_uart6_apps_clk = {
  1711. .halt_reg = 0x24004,
  1712. .clkr = {
  1713. .enable_reg = 0x24004,
  1714. .enable_mask = BIT(0),
  1715. .hw.init = &(struct clk_init_data){
  1716. .name = "gcc_blsp1_uart6_apps_clk",
  1717. .parent_hws = (const struct clk_hw*[]){
  1718. &blsp1_uart6_apps_clk_src.clkr.hw,
  1719. },
  1720. .num_parents = 1,
  1721. .flags = CLK_SET_RATE_PARENT,
  1722. .ops = &clk_branch2_ops,
  1723. },
  1724. },
  1725. };
  1726. static struct clk_branch gcc_blsp2_ahb_clk = {
  1727. .halt_reg = 0x25004,
  1728. .halt_check = BRANCH_HALT_VOTED,
  1729. .clkr = {
  1730. .enable_reg = 0x52004,
  1731. .enable_mask = BIT(15),
  1732. .hw.init = &(struct clk_init_data){
  1733. .name = "gcc_blsp2_ahb_clk",
  1734. .ops = &clk_branch2_ops,
  1735. },
  1736. },
  1737. };
  1738. static struct clk_branch gcc_blsp2_sleep_clk = {
  1739. .halt_reg = 0x25008,
  1740. .halt_check = BRANCH_HALT_VOTED,
  1741. .clkr = {
  1742. .enable_reg = 0x52004,
  1743. .enable_mask = BIT(14),
  1744. .hw.init = &(struct clk_init_data){
  1745. .name = "gcc_blsp2_sleep_clk",
  1746. .parent_hws = (const struct clk_hw*[]){
  1747. &gcc_sleep_clk_src.clkr.hw,
  1748. },
  1749. .num_parents = 1,
  1750. .flags = CLK_SET_RATE_PARENT,
  1751. .ops = &clk_branch2_ops,
  1752. },
  1753. },
  1754. };
  1755. static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
  1756. .halt_reg = 0x26004,
  1757. .clkr = {
  1758. .enable_reg = 0x26004,
  1759. .enable_mask = BIT(0),
  1760. .hw.init = &(struct clk_init_data){
  1761. .name = "gcc_blsp2_qup1_spi_apps_clk",
  1762. .parent_hws = (const struct clk_hw*[]){
  1763. &blsp2_qup1_spi_apps_clk_src.clkr.hw,
  1764. },
  1765. .num_parents = 1,
  1766. .flags = CLK_SET_RATE_PARENT,
  1767. .ops = &clk_branch2_ops,
  1768. },
  1769. },
  1770. };
  1771. static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
  1772. .halt_reg = 0x26008,
  1773. .clkr = {
  1774. .enable_reg = 0x26008,
  1775. .enable_mask = BIT(0),
  1776. .hw.init = &(struct clk_init_data){
  1777. .name = "gcc_blsp2_qup1_i2c_apps_clk",
  1778. .parent_hws = (const struct clk_hw*[]){
  1779. &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
  1780. },
  1781. .num_parents = 1,
  1782. .flags = CLK_SET_RATE_PARENT,
  1783. .ops = &clk_branch2_ops,
  1784. },
  1785. },
  1786. };
  1787. static struct clk_branch gcc_blsp2_uart1_apps_clk = {
  1788. .halt_reg = 0x27004,
  1789. .clkr = {
  1790. .enable_reg = 0x27004,
  1791. .enable_mask = BIT(0),
  1792. .hw.init = &(struct clk_init_data){
  1793. .name = "gcc_blsp2_uart1_apps_clk",
  1794. .parent_hws = (const struct clk_hw*[]){
  1795. &blsp2_uart1_apps_clk_src.clkr.hw,
  1796. },
  1797. .num_parents = 1,
  1798. .flags = CLK_SET_RATE_PARENT,
  1799. .ops = &clk_branch2_ops,
  1800. },
  1801. },
  1802. };
  1803. static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
  1804. .halt_reg = 0x28004,
  1805. .clkr = {
  1806. .enable_reg = 0x28004,
  1807. .enable_mask = BIT(0),
  1808. .hw.init = &(struct clk_init_data){
  1809. .name = "gcc_blsp2_qup2_spi_apps_clk",
  1810. .parent_hws = (const struct clk_hw*[]){
  1811. &blsp2_qup2_spi_apps_clk_src.clkr.hw,
  1812. },
  1813. .num_parents = 1,
  1814. .flags = CLK_SET_RATE_PARENT,
  1815. .ops = &clk_branch2_ops,
  1816. },
  1817. },
  1818. };
  1819. static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
  1820. .halt_reg = 0x28008,
  1821. .clkr = {
  1822. .enable_reg = 0x28008,
  1823. .enable_mask = BIT(0),
  1824. .hw.init = &(struct clk_init_data){
  1825. .name = "gcc_blsp2_qup2_i2c_apps_clk",
  1826. .parent_hws = (const struct clk_hw*[]){
  1827. &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
  1828. },
  1829. .num_parents = 1,
  1830. .flags = CLK_SET_RATE_PARENT,
  1831. .ops = &clk_branch2_ops,
  1832. },
  1833. },
  1834. };
  1835. static struct clk_branch gcc_blsp2_uart2_apps_clk = {
  1836. .halt_reg = 0x29004,
  1837. .clkr = {
  1838. .enable_reg = 0x29004,
  1839. .enable_mask = BIT(0),
  1840. .hw.init = &(struct clk_init_data){
  1841. .name = "gcc_blsp2_uart2_apps_clk",
  1842. .parent_hws = (const struct clk_hw*[]){
  1843. &blsp2_uart2_apps_clk_src.clkr.hw,
  1844. },
  1845. .num_parents = 1,
  1846. .flags = CLK_SET_RATE_PARENT,
  1847. .ops = &clk_branch2_ops,
  1848. },
  1849. },
  1850. };
  1851. static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
  1852. .halt_reg = 0x2a004,
  1853. .clkr = {
  1854. .enable_reg = 0x2a004,
  1855. .enable_mask = BIT(0),
  1856. .hw.init = &(struct clk_init_data){
  1857. .name = "gcc_blsp2_qup3_spi_apps_clk",
  1858. .parent_hws = (const struct clk_hw*[]){
  1859. &blsp2_qup3_spi_apps_clk_src.clkr.hw,
  1860. },
  1861. .num_parents = 1,
  1862. .flags = CLK_SET_RATE_PARENT,
  1863. .ops = &clk_branch2_ops,
  1864. },
  1865. },
  1866. };
  1867. static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
  1868. .halt_reg = 0x2a008,
  1869. .clkr = {
  1870. .enable_reg = 0x2a008,
  1871. .enable_mask = BIT(0),
  1872. .hw.init = &(struct clk_init_data){
  1873. .name = "gcc_blsp2_qup3_i2c_apps_clk",
  1874. .parent_hws = (const struct clk_hw*[]){
  1875. &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
  1876. },
  1877. .num_parents = 1,
  1878. .flags = CLK_SET_RATE_PARENT,
  1879. .ops = &clk_branch2_ops,
  1880. },
  1881. },
  1882. };
  1883. static struct clk_branch gcc_blsp2_uart3_apps_clk = {
  1884. .halt_reg = 0x2b004,
  1885. .clkr = {
  1886. .enable_reg = 0x2b004,
  1887. .enable_mask = BIT(0),
  1888. .hw.init = &(struct clk_init_data){
  1889. .name = "gcc_blsp2_uart3_apps_clk",
  1890. .parent_hws = (const struct clk_hw*[]){
  1891. &blsp2_uart3_apps_clk_src.clkr.hw,
  1892. },
  1893. .num_parents = 1,
  1894. .flags = CLK_SET_RATE_PARENT,
  1895. .ops = &clk_branch2_ops,
  1896. },
  1897. },
  1898. };
  1899. static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
  1900. .halt_reg = 0x2c004,
  1901. .clkr = {
  1902. .enable_reg = 0x2c004,
  1903. .enable_mask = BIT(0),
  1904. .hw.init = &(struct clk_init_data){
  1905. .name = "gcc_blsp2_qup4_spi_apps_clk",
  1906. .parent_hws = (const struct clk_hw*[]){
  1907. &blsp2_qup4_spi_apps_clk_src.clkr.hw,
  1908. },
  1909. .num_parents = 1,
  1910. .flags = CLK_SET_RATE_PARENT,
  1911. .ops = &clk_branch2_ops,
  1912. },
  1913. },
  1914. };
  1915. static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
  1916. .halt_reg = 0x2c008,
  1917. .clkr = {
  1918. .enable_reg = 0x2c008,
  1919. .enable_mask = BIT(0),
  1920. .hw.init = &(struct clk_init_data){
  1921. .name = "gcc_blsp2_qup4_i2c_apps_clk",
  1922. .parent_hws = (const struct clk_hw*[]){
  1923. &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
  1924. },
  1925. .num_parents = 1,
  1926. .flags = CLK_SET_RATE_PARENT,
  1927. .ops = &clk_branch2_ops,
  1928. },
  1929. },
  1930. };
  1931. static struct clk_branch gcc_blsp2_uart4_apps_clk = {
  1932. .halt_reg = 0x2d004,
  1933. .clkr = {
  1934. .enable_reg = 0x2d004,
  1935. .enable_mask = BIT(0),
  1936. .hw.init = &(struct clk_init_data){
  1937. .name = "gcc_blsp2_uart4_apps_clk",
  1938. .parent_hws = (const struct clk_hw*[]){
  1939. &blsp2_uart4_apps_clk_src.clkr.hw,
  1940. },
  1941. .num_parents = 1,
  1942. .flags = CLK_SET_RATE_PARENT,
  1943. .ops = &clk_branch2_ops,
  1944. },
  1945. },
  1946. };
  1947. static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
  1948. .halt_reg = 0x2e004,
  1949. .clkr = {
  1950. .enable_reg = 0x2e004,
  1951. .enable_mask = BIT(0),
  1952. .hw.init = &(struct clk_init_data){
  1953. .name = "gcc_blsp2_qup5_spi_apps_clk",
  1954. .parent_hws = (const struct clk_hw*[]){
  1955. &blsp2_qup5_spi_apps_clk_src.clkr.hw,
  1956. },
  1957. .num_parents = 1,
  1958. .flags = CLK_SET_RATE_PARENT,
  1959. .ops = &clk_branch2_ops,
  1960. },
  1961. },
  1962. };
  1963. static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
  1964. .halt_reg = 0x2e008,
  1965. .clkr = {
  1966. .enable_reg = 0x2e008,
  1967. .enable_mask = BIT(0),
  1968. .hw.init = &(struct clk_init_data){
  1969. .name = "gcc_blsp2_qup5_i2c_apps_clk",
  1970. .parent_hws = (const struct clk_hw*[]){
  1971. &blsp2_qup5_i2c_apps_clk_src.clkr.hw,
  1972. },
  1973. .num_parents = 1,
  1974. .flags = CLK_SET_RATE_PARENT,
  1975. .ops = &clk_branch2_ops,
  1976. },
  1977. },
  1978. };
  1979. static struct clk_branch gcc_blsp2_uart5_apps_clk = {
  1980. .halt_reg = 0x2f004,
  1981. .clkr = {
  1982. .enable_reg = 0x2f004,
  1983. .enable_mask = BIT(0),
  1984. .hw.init = &(struct clk_init_data){
  1985. .name = "gcc_blsp2_uart5_apps_clk",
  1986. .parent_hws = (const struct clk_hw*[]){
  1987. &blsp2_uart5_apps_clk_src.clkr.hw,
  1988. },
  1989. .num_parents = 1,
  1990. .flags = CLK_SET_RATE_PARENT,
  1991. .ops = &clk_branch2_ops,
  1992. },
  1993. },
  1994. };
  1995. static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
  1996. .halt_reg = 0x30004,
  1997. .clkr = {
  1998. .enable_reg = 0x30004,
  1999. .enable_mask = BIT(0),
  2000. .hw.init = &(struct clk_init_data){
  2001. .name = "gcc_blsp2_qup6_spi_apps_clk",
  2002. .parent_hws = (const struct clk_hw*[]){
  2003. &blsp2_qup6_spi_apps_clk_src.clkr.hw,
  2004. },
  2005. .num_parents = 1,
  2006. .flags = CLK_SET_RATE_PARENT,
  2007. .ops = &clk_branch2_ops,
  2008. },
  2009. },
  2010. };
  2011. static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
  2012. .halt_reg = 0x30008,
  2013. .clkr = {
  2014. .enable_reg = 0x30008,
  2015. .enable_mask = BIT(0),
  2016. .hw.init = &(struct clk_init_data){
  2017. .name = "gcc_blsp2_qup6_i2c_apps_clk",
  2018. .parent_hws = (const struct clk_hw*[]){
  2019. &blsp2_qup6_i2c_apps_clk_src.clkr.hw,
  2020. },
  2021. .num_parents = 1,
  2022. .flags = CLK_SET_RATE_PARENT,
  2023. .ops = &clk_branch2_ops,
  2024. },
  2025. },
  2026. };
  2027. static struct clk_branch gcc_blsp2_uart6_apps_clk = {
  2028. .halt_reg = 0x31004,
  2029. .clkr = {
  2030. .enable_reg = 0x31004,
  2031. .enable_mask = BIT(0),
  2032. .hw.init = &(struct clk_init_data){
  2033. .name = "gcc_blsp2_uart6_apps_clk",
  2034. .parent_hws = (const struct clk_hw*[]){
  2035. &blsp2_uart6_apps_clk_src.clkr.hw,
  2036. },
  2037. .num_parents = 1,
  2038. .flags = CLK_SET_RATE_PARENT,
  2039. .ops = &clk_branch2_ops,
  2040. },
  2041. },
  2042. };
  2043. static struct clk_branch gcc_pdm_ahb_clk = {
  2044. .halt_reg = 0x33004,
  2045. .clkr = {
  2046. .enable_reg = 0x33004,
  2047. .enable_mask = BIT(0),
  2048. .hw.init = &(struct clk_init_data){
  2049. .name = "gcc_pdm_ahb_clk",
  2050. .ops = &clk_branch2_ops,
  2051. },
  2052. },
  2053. };
  2054. static struct clk_branch gcc_pdm2_clk = {
  2055. .halt_reg = 0x3300c,
  2056. .clkr = {
  2057. .enable_reg = 0x3300c,
  2058. .enable_mask = BIT(0),
  2059. .hw.init = &(struct clk_init_data){
  2060. .name = "gcc_pdm2_clk",
  2061. .parent_hws = (const struct clk_hw*[]){
  2062. &pdm2_clk_src.clkr.hw,
  2063. },
  2064. .num_parents = 1,
  2065. .flags = CLK_SET_RATE_PARENT,
  2066. .ops = &clk_branch2_ops,
  2067. },
  2068. },
  2069. };
  2070. static struct clk_branch gcc_prng_ahb_clk = {
  2071. .halt_reg = 0x34004,
  2072. .halt_check = BRANCH_HALT_VOTED,
  2073. .clkr = {
  2074. .enable_reg = 0x52004,
  2075. .enable_mask = BIT(13),
  2076. .hw.init = &(struct clk_init_data){
  2077. .name = "gcc_prng_ahb_clk",
  2078. .ops = &clk_branch2_ops,
  2079. },
  2080. },
  2081. };
  2082. static struct clk_branch gcc_tsif_ahb_clk = {
  2083. .halt_reg = 0x36004,
  2084. .clkr = {
  2085. .enable_reg = 0x36004,
  2086. .enable_mask = BIT(0),
  2087. .hw.init = &(struct clk_init_data){
  2088. .name = "gcc_tsif_ahb_clk",
  2089. .ops = &clk_branch2_ops,
  2090. },
  2091. },
  2092. };
  2093. static struct clk_branch gcc_tsif_ref_clk = {
  2094. .halt_reg = 0x36008,
  2095. .clkr = {
  2096. .enable_reg = 0x36008,
  2097. .enable_mask = BIT(0),
  2098. .hw.init = &(struct clk_init_data){
  2099. .name = "gcc_tsif_ref_clk",
  2100. .parent_hws = (const struct clk_hw*[]){
  2101. &tsif_ref_clk_src.clkr.hw,
  2102. },
  2103. .num_parents = 1,
  2104. .flags = CLK_SET_RATE_PARENT,
  2105. .ops = &clk_branch2_ops,
  2106. },
  2107. },
  2108. };
  2109. static struct clk_branch gcc_tsif_inactivity_timers_clk = {
  2110. .halt_reg = 0x3600c,
  2111. .clkr = {
  2112. .enable_reg = 0x3600c,
  2113. .enable_mask = BIT(0),
  2114. .hw.init = &(struct clk_init_data){
  2115. .name = "gcc_tsif_inactivity_timers_clk",
  2116. .parent_hws = (const struct clk_hw*[]){
  2117. &gcc_sleep_clk_src.clkr.hw,
  2118. },
  2119. .num_parents = 1,
  2120. .flags = CLK_SET_RATE_PARENT,
  2121. .ops = &clk_branch2_ops,
  2122. },
  2123. },
  2124. };
  2125. static struct clk_branch gcc_boot_rom_ahb_clk = {
  2126. .halt_reg = 0x38004,
  2127. .halt_check = BRANCH_HALT_VOTED,
  2128. .clkr = {
  2129. .enable_reg = 0x52004,
  2130. .enable_mask = BIT(10),
  2131. .hw.init = &(struct clk_init_data){
  2132. .name = "gcc_boot_rom_ahb_clk",
  2133. .ops = &clk_branch2_ops,
  2134. },
  2135. },
  2136. };
  2137. static struct clk_branch gcc_bimc_gfx_clk = {
  2138. .halt_reg = 0x46018,
  2139. .clkr = {
  2140. .enable_reg = 0x46018,
  2141. .enable_mask = BIT(0),
  2142. .hw.init = &(struct clk_init_data){
  2143. .name = "gcc_bimc_gfx_clk",
  2144. .flags = CLK_SET_RATE_PARENT,
  2145. .ops = &clk_branch2_ops,
  2146. },
  2147. },
  2148. };
  2149. static struct clk_branch gcc_hmss_rbcpr_clk = {
  2150. .halt_reg = 0x4800c,
  2151. .clkr = {
  2152. .enable_reg = 0x4800c,
  2153. .enable_mask = BIT(0),
  2154. .hw.init = &(struct clk_init_data){
  2155. .name = "gcc_hmss_rbcpr_clk",
  2156. .parent_hws = (const struct clk_hw*[]){
  2157. &hmss_rbcpr_clk_src.clkr.hw,
  2158. },
  2159. .num_parents = 1,
  2160. .flags = CLK_SET_RATE_PARENT,
  2161. .ops = &clk_branch2_ops,
  2162. },
  2163. },
  2164. };
  2165. static struct clk_branch gcc_gp1_clk = {
  2166. .halt_reg = 0x64000,
  2167. .clkr = {
  2168. .enable_reg = 0x64000,
  2169. .enable_mask = BIT(0),
  2170. .hw.init = &(struct clk_init_data){
  2171. .name = "gcc_gp1_clk",
  2172. .parent_hws = (const struct clk_hw*[]){
  2173. &gp1_clk_src.clkr.hw,
  2174. },
  2175. .num_parents = 1,
  2176. .flags = CLK_SET_RATE_PARENT,
  2177. .ops = &clk_branch2_ops,
  2178. },
  2179. },
  2180. };
  2181. static struct clk_branch gcc_gp2_clk = {
  2182. .halt_reg = 0x65000,
  2183. .clkr = {
  2184. .enable_reg = 0x65000,
  2185. .enable_mask = BIT(0),
  2186. .hw.init = &(struct clk_init_data){
  2187. .name = "gcc_gp2_clk",
  2188. .parent_hws = (const struct clk_hw*[]){
  2189. &gp2_clk_src.clkr.hw,
  2190. },
  2191. .num_parents = 1,
  2192. .flags = CLK_SET_RATE_PARENT,
  2193. .ops = &clk_branch2_ops,
  2194. },
  2195. },
  2196. };
  2197. static struct clk_branch gcc_gp3_clk = {
  2198. .halt_reg = 0x66000,
  2199. .clkr = {
  2200. .enable_reg = 0x66000,
  2201. .enable_mask = BIT(0),
  2202. .hw.init = &(struct clk_init_data){
  2203. .name = "gcc_gp3_clk",
  2204. .parent_hws = (const struct clk_hw*[]){
  2205. &gp3_clk_src.clkr.hw,
  2206. },
  2207. .num_parents = 1,
  2208. .flags = CLK_SET_RATE_PARENT,
  2209. .ops = &clk_branch2_ops,
  2210. },
  2211. },
  2212. };
  2213. static struct clk_branch gcc_pcie_0_slv_axi_clk = {
  2214. .halt_reg = 0x6b008,
  2215. .clkr = {
  2216. .enable_reg = 0x6b008,
  2217. .enable_mask = BIT(0),
  2218. .hw.init = &(struct clk_init_data){
  2219. .name = "gcc_pcie_0_slv_axi_clk",
  2220. .ops = &clk_branch2_ops,
  2221. },
  2222. },
  2223. };
  2224. static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
  2225. .halt_reg = 0x6b00c,
  2226. .clkr = {
  2227. .enable_reg = 0x6b00c,
  2228. .enable_mask = BIT(0),
  2229. .hw.init = &(struct clk_init_data){
  2230. .name = "gcc_pcie_0_mstr_axi_clk",
  2231. .ops = &clk_branch2_ops,
  2232. },
  2233. },
  2234. };
  2235. static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
  2236. .halt_reg = 0x6b010,
  2237. .clkr = {
  2238. .enable_reg = 0x6b010,
  2239. .enable_mask = BIT(0),
  2240. .hw.init = &(struct clk_init_data){
  2241. .name = "gcc_pcie_0_cfg_ahb_clk",
  2242. .ops = &clk_branch2_ops,
  2243. },
  2244. },
  2245. };
  2246. static struct clk_branch gcc_pcie_0_aux_clk = {
  2247. .halt_reg = 0x6b014,
  2248. .clkr = {
  2249. .enable_reg = 0x6b014,
  2250. .enable_mask = BIT(0),
  2251. .hw.init = &(struct clk_init_data){
  2252. .name = "gcc_pcie_0_aux_clk",
  2253. .parent_hws = (const struct clk_hw*[]){
  2254. &pcie_aux_clk_src.clkr.hw,
  2255. },
  2256. .num_parents = 1,
  2257. .flags = CLK_SET_RATE_PARENT,
  2258. .ops = &clk_branch2_ops,
  2259. },
  2260. },
  2261. };
  2262. static struct clk_branch gcc_pcie_0_pipe_clk = {
  2263. .halt_reg = 0x6b018,
  2264. .halt_check = BRANCH_HALT_SKIP,
  2265. .clkr = {
  2266. .enable_reg = 0x6b018,
  2267. .enable_mask = BIT(0),
  2268. .hw.init = &(struct clk_init_data){
  2269. .name = "gcc_pcie_0_pipe_clk",
  2270. .parent_data = &(const struct clk_parent_data){
  2271. .fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src",
  2272. },
  2273. .num_parents = 1,
  2274. .flags = CLK_SET_RATE_PARENT,
  2275. .ops = &clk_branch2_ops,
  2276. },
  2277. },
  2278. };
  2279. static struct clk_branch gcc_pcie_1_slv_axi_clk = {
  2280. .halt_reg = 0x6d008,
  2281. .clkr = {
  2282. .enable_reg = 0x6d008,
  2283. .enable_mask = BIT(0),
  2284. .hw.init = &(struct clk_init_data){
  2285. .name = "gcc_pcie_1_slv_axi_clk",
  2286. .ops = &clk_branch2_ops,
  2287. },
  2288. },
  2289. };
  2290. static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
  2291. .halt_reg = 0x6d00c,
  2292. .clkr = {
  2293. .enable_reg = 0x6d00c,
  2294. .enable_mask = BIT(0),
  2295. .hw.init = &(struct clk_init_data){
  2296. .name = "gcc_pcie_1_mstr_axi_clk",
  2297. .ops = &clk_branch2_ops,
  2298. },
  2299. },
  2300. };
  2301. static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
  2302. .halt_reg = 0x6d010,
  2303. .clkr = {
  2304. .enable_reg = 0x6d010,
  2305. .enable_mask = BIT(0),
  2306. .hw.init = &(struct clk_init_data){
  2307. .name = "gcc_pcie_1_cfg_ahb_clk",
  2308. .ops = &clk_branch2_ops,
  2309. },
  2310. },
  2311. };
  2312. static struct clk_branch gcc_pcie_1_aux_clk = {
  2313. .halt_reg = 0x6d014,
  2314. .clkr = {
  2315. .enable_reg = 0x6d014,
  2316. .enable_mask = BIT(0),
  2317. .hw.init = &(struct clk_init_data){
  2318. .name = "gcc_pcie_1_aux_clk",
  2319. .parent_hws = (const struct clk_hw*[]){
  2320. &pcie_aux_clk_src.clkr.hw,
  2321. },
  2322. .num_parents = 1,
  2323. .flags = CLK_SET_RATE_PARENT,
  2324. .ops = &clk_branch2_ops,
  2325. },
  2326. },
  2327. };
  2328. static struct clk_branch gcc_pcie_1_pipe_clk = {
  2329. .halt_reg = 0x6d018,
  2330. .halt_check = BRANCH_HALT_SKIP,
  2331. .clkr = {
  2332. .enable_reg = 0x6d018,
  2333. .enable_mask = BIT(0),
  2334. .hw.init = &(struct clk_init_data){
  2335. .name = "gcc_pcie_1_pipe_clk",
  2336. .parent_data = &(const struct clk_parent_data){
  2337. .fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src",
  2338. },
  2339. .num_parents = 1,
  2340. .flags = CLK_SET_RATE_PARENT,
  2341. .ops = &clk_branch2_ops,
  2342. },
  2343. },
  2344. };
  2345. static struct clk_branch gcc_pcie_2_slv_axi_clk = {
  2346. .halt_reg = 0x6e008,
  2347. .clkr = {
  2348. .enable_reg = 0x6e008,
  2349. .enable_mask = BIT(0),
  2350. .hw.init = &(struct clk_init_data){
  2351. .name = "gcc_pcie_2_slv_axi_clk",
  2352. .ops = &clk_branch2_ops,
  2353. },
  2354. },
  2355. };
  2356. static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
  2357. .halt_reg = 0x6e00c,
  2358. .clkr = {
  2359. .enable_reg = 0x6e00c,
  2360. .enable_mask = BIT(0),
  2361. .hw.init = &(struct clk_init_data){
  2362. .name = "gcc_pcie_2_mstr_axi_clk",
  2363. .ops = &clk_branch2_ops,
  2364. },
  2365. },
  2366. };
  2367. static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
  2368. .halt_reg = 0x6e010,
  2369. .clkr = {
  2370. .enable_reg = 0x6e010,
  2371. .enable_mask = BIT(0),
  2372. .hw.init = &(struct clk_init_data){
  2373. .name = "gcc_pcie_2_cfg_ahb_clk",
  2374. .ops = &clk_branch2_ops,
  2375. },
  2376. },
  2377. };
  2378. static struct clk_branch gcc_pcie_2_aux_clk = {
  2379. .halt_reg = 0x6e014,
  2380. .clkr = {
  2381. .enable_reg = 0x6e014,
  2382. .enable_mask = BIT(0),
  2383. .hw.init = &(struct clk_init_data){
  2384. .name = "gcc_pcie_2_aux_clk",
  2385. .parent_hws = (const struct clk_hw*[]){
  2386. &pcie_aux_clk_src.clkr.hw,
  2387. },
  2388. .num_parents = 1,
  2389. .flags = CLK_SET_RATE_PARENT,
  2390. .ops = &clk_branch2_ops,
  2391. },
  2392. },
  2393. };
  2394. static struct clk_branch gcc_pcie_2_pipe_clk = {
  2395. .halt_reg = 0x6e018,
  2396. .halt_check = BRANCH_HALT_SKIP,
  2397. .clkr = {
  2398. .enable_reg = 0x6e018,
  2399. .enable_mask = BIT(0),
  2400. .hw.init = &(struct clk_init_data){
  2401. .name = "gcc_pcie_2_pipe_clk",
  2402. .parent_data = &(const struct clk_parent_data){
  2403. .fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src",
  2404. },
  2405. .num_parents = 1,
  2406. .flags = CLK_SET_RATE_PARENT,
  2407. .ops = &clk_branch2_ops,
  2408. },
  2409. },
  2410. };
  2411. static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
  2412. .halt_reg = 0x6f004,
  2413. .clkr = {
  2414. .enable_reg = 0x6f004,
  2415. .enable_mask = BIT(0),
  2416. .hw.init = &(struct clk_init_data){
  2417. .name = "gcc_pcie_phy_cfg_ahb_clk",
  2418. .ops = &clk_branch2_ops,
  2419. },
  2420. },
  2421. };
  2422. static struct clk_branch gcc_pcie_phy_aux_clk = {
  2423. .halt_reg = 0x6f008,
  2424. .clkr = {
  2425. .enable_reg = 0x6f008,
  2426. .enable_mask = BIT(0),
  2427. .hw.init = &(struct clk_init_data){
  2428. .name = "gcc_pcie_phy_aux_clk",
  2429. .parent_hws = (const struct clk_hw*[]){
  2430. &pcie_aux_clk_src.clkr.hw,
  2431. },
  2432. .num_parents = 1,
  2433. .flags = CLK_SET_RATE_PARENT,
  2434. .ops = &clk_branch2_ops,
  2435. },
  2436. },
  2437. };
  2438. static struct clk_branch gcc_ufs_axi_clk = {
  2439. .halt_reg = 0x75008,
  2440. .clkr = {
  2441. .enable_reg = 0x75008,
  2442. .enable_mask = BIT(0),
  2443. .hw.init = &(struct clk_init_data){
  2444. .name = "gcc_ufs_axi_clk",
  2445. .parent_hws = (const struct clk_hw*[]){
  2446. &ufs_axi_clk_src.clkr.hw,
  2447. },
  2448. .num_parents = 1,
  2449. .flags = CLK_SET_RATE_PARENT,
  2450. .ops = &clk_branch2_ops,
  2451. },
  2452. },
  2453. };
  2454. static struct clk_branch gcc_ufs_ahb_clk = {
  2455. .halt_reg = 0x7500c,
  2456. .clkr = {
  2457. .enable_reg = 0x7500c,
  2458. .enable_mask = BIT(0),
  2459. .hw.init = &(struct clk_init_data){
  2460. .name = "gcc_ufs_ahb_clk",
  2461. .ops = &clk_branch2_ops,
  2462. },
  2463. },
  2464. };
  2465. static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
  2466. .mult = 1,
  2467. .div = 16,
  2468. .hw.init = &(struct clk_init_data){
  2469. .name = "ufs_tx_cfg_clk_src",
  2470. .parent_hws = (const struct clk_hw*[]){
  2471. &ufs_axi_clk_src.clkr.hw,
  2472. },
  2473. .num_parents = 1,
  2474. .flags = CLK_SET_RATE_PARENT,
  2475. .ops = &clk_fixed_factor_ops,
  2476. },
  2477. };
  2478. static struct clk_branch gcc_ufs_tx_cfg_clk = {
  2479. .halt_reg = 0x75010,
  2480. .clkr = {
  2481. .enable_reg = 0x75010,
  2482. .enable_mask = BIT(0),
  2483. .hw.init = &(struct clk_init_data){
  2484. .name = "gcc_ufs_tx_cfg_clk",
  2485. .parent_hws = (const struct clk_hw*[]){
  2486. &ufs_tx_cfg_clk_src.hw,
  2487. },
  2488. .num_parents = 1,
  2489. .flags = CLK_SET_RATE_PARENT,
  2490. .ops = &clk_branch2_ops,
  2491. },
  2492. },
  2493. };
  2494. static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
  2495. .mult = 1,
  2496. .div = 16,
  2497. .hw.init = &(struct clk_init_data){
  2498. .name = "ufs_rx_cfg_clk_src",
  2499. .parent_hws = (const struct clk_hw*[]){
  2500. &ufs_axi_clk_src.clkr.hw,
  2501. },
  2502. .num_parents = 1,
  2503. .flags = CLK_SET_RATE_PARENT,
  2504. .ops = &clk_fixed_factor_ops,
  2505. },
  2506. };
  2507. static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
  2508. .halt_reg = 0x7d010,
  2509. .halt_check = BRANCH_HALT_VOTED,
  2510. .clkr = {
  2511. .enable_reg = 0x7d010,
  2512. .enable_mask = BIT(0),
  2513. .hw.init = &(struct clk_init_data){
  2514. .name = "hlos1_vote_lpass_core_smmu_clk",
  2515. .ops = &clk_branch2_ops,
  2516. },
  2517. },
  2518. };
  2519. static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
  2520. .halt_reg = 0x7d014,
  2521. .halt_check = BRANCH_HALT_VOTED,
  2522. .clkr = {
  2523. .enable_reg = 0x7d014,
  2524. .enable_mask = BIT(0),
  2525. .hw.init = &(struct clk_init_data){
  2526. .name = "hlos1_vote_lpass_adsp_smmu_clk",
  2527. .ops = &clk_branch2_ops,
  2528. },
  2529. },
  2530. };
  2531. static struct clk_branch gcc_ufs_rx_cfg_clk = {
  2532. .halt_reg = 0x75014,
  2533. .clkr = {
  2534. .enable_reg = 0x75014,
  2535. .enable_mask = BIT(0),
  2536. .hw.init = &(struct clk_init_data){
  2537. .name = "gcc_ufs_rx_cfg_clk",
  2538. .parent_hws = (const struct clk_hw*[]){
  2539. &ufs_rx_cfg_clk_src.hw,
  2540. },
  2541. .num_parents = 1,
  2542. .flags = CLK_SET_RATE_PARENT,
  2543. .ops = &clk_branch2_ops,
  2544. },
  2545. },
  2546. };
  2547. static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
  2548. .halt_reg = 0x75018,
  2549. .halt_check = BRANCH_HALT_SKIP,
  2550. .clkr = {
  2551. .enable_reg = 0x75018,
  2552. .enable_mask = BIT(0),
  2553. .hw.init = &(struct clk_init_data){
  2554. .name = "gcc_ufs_tx_symbol_0_clk",
  2555. .parent_data = &(const struct clk_parent_data){
  2556. .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
  2557. },
  2558. .num_parents = 1,
  2559. .flags = CLK_SET_RATE_PARENT,
  2560. .ops = &clk_branch2_ops,
  2561. },
  2562. },
  2563. };
  2564. static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
  2565. .halt_reg = 0x7501c,
  2566. .halt_check = BRANCH_HALT_SKIP,
  2567. .clkr = {
  2568. .enable_reg = 0x7501c,
  2569. .enable_mask = BIT(0),
  2570. .hw.init = &(struct clk_init_data){
  2571. .name = "gcc_ufs_rx_symbol_0_clk",
  2572. .parent_data = &(const struct clk_parent_data){
  2573. .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
  2574. },
  2575. .num_parents = 1,
  2576. .flags = CLK_SET_RATE_PARENT,
  2577. .ops = &clk_branch2_ops,
  2578. },
  2579. },
  2580. };
  2581. static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
  2582. .halt_reg = 0x75020,
  2583. .halt_check = BRANCH_HALT_SKIP,
  2584. .clkr = {
  2585. .enable_reg = 0x75020,
  2586. .enable_mask = BIT(0),
  2587. .hw.init = &(struct clk_init_data){
  2588. .name = "gcc_ufs_rx_symbol_1_clk",
  2589. .parent_data = &(const struct clk_parent_data){
  2590. .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
  2591. },
  2592. .num_parents = 1,
  2593. .flags = CLK_SET_RATE_PARENT,
  2594. .ops = &clk_branch2_ops,
  2595. },
  2596. },
  2597. };
  2598. static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
  2599. .mult = 1,
  2600. .div = 2,
  2601. .hw.init = &(struct clk_init_data){
  2602. .name = "ufs_ice_core_postdiv_clk_src",
  2603. .parent_hws = (const struct clk_hw*[]){
  2604. &ufs_ice_core_clk_src.clkr.hw,
  2605. },
  2606. .num_parents = 1,
  2607. .flags = CLK_SET_RATE_PARENT,
  2608. .ops = &clk_fixed_factor_ops,
  2609. },
  2610. };
  2611. static struct clk_branch gcc_ufs_unipro_core_clk = {
  2612. .halt_reg = 0x7600c,
  2613. .clkr = {
  2614. .enable_reg = 0x7600c,
  2615. .enable_mask = BIT(0),
  2616. .hw.init = &(struct clk_init_data){
  2617. .name = "gcc_ufs_unipro_core_clk",
  2618. .parent_hws = (const struct clk_hw*[]){
  2619. &ufs_ice_core_postdiv_clk_src.hw,
  2620. },
  2621. .num_parents = 1,
  2622. .flags = CLK_SET_RATE_PARENT,
  2623. .ops = &clk_branch2_ops,
  2624. },
  2625. },
  2626. };
  2627. static struct clk_branch gcc_ufs_ice_core_clk = {
  2628. .halt_reg = 0x76010,
  2629. .clkr = {
  2630. .enable_reg = 0x76010,
  2631. .enable_mask = BIT(0),
  2632. .hw.init = &(struct clk_init_data){
  2633. .name = "gcc_ufs_ice_core_clk",
  2634. .parent_hws = (const struct clk_hw*[]){
  2635. &ufs_ice_core_clk_src.clkr.hw,
  2636. },
  2637. .num_parents = 1,
  2638. .flags = CLK_SET_RATE_PARENT,
  2639. .ops = &clk_branch2_ops,
  2640. },
  2641. },
  2642. };
  2643. static struct clk_branch gcc_ufs_sys_clk_core_clk = {
  2644. .halt_check = BRANCH_HALT_DELAY,
  2645. .clkr = {
  2646. .enable_reg = 0x76030,
  2647. .enable_mask = BIT(0),
  2648. .hw.init = &(struct clk_init_data){
  2649. .name = "gcc_ufs_sys_clk_core_clk",
  2650. .ops = &clk_branch2_ops,
  2651. },
  2652. },
  2653. };
  2654. static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
  2655. .halt_check = BRANCH_HALT_DELAY,
  2656. .clkr = {
  2657. .enable_reg = 0x76034,
  2658. .enable_mask = BIT(0),
  2659. .hw.init = &(struct clk_init_data){
  2660. .name = "gcc_ufs_tx_symbol_clk_core_clk",
  2661. .ops = &clk_branch2_ops,
  2662. },
  2663. },
  2664. };
  2665. static struct clk_branch gcc_aggre0_snoc_axi_clk = {
  2666. .halt_reg = 0x81008,
  2667. .clkr = {
  2668. .enable_reg = 0x81008,
  2669. .enable_mask = BIT(0),
  2670. .hw.init = &(struct clk_init_data){
  2671. .name = "gcc_aggre0_snoc_axi_clk",
  2672. .flags = CLK_IS_CRITICAL,
  2673. .ops = &clk_branch2_ops,
  2674. },
  2675. },
  2676. };
  2677. static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
  2678. .halt_reg = 0x8100c,
  2679. .clkr = {
  2680. .enable_reg = 0x8100c,
  2681. .enable_mask = BIT(0),
  2682. .hw.init = &(struct clk_init_data){
  2683. .name = "gcc_aggre0_cnoc_ahb_clk",
  2684. .flags = CLK_IS_CRITICAL,
  2685. .ops = &clk_branch2_ops,
  2686. },
  2687. },
  2688. };
  2689. static struct clk_branch gcc_smmu_aggre0_axi_clk = {
  2690. .halt_reg = 0x81014,
  2691. .clkr = {
  2692. .enable_reg = 0x81014,
  2693. .enable_mask = BIT(0),
  2694. .hw.init = &(struct clk_init_data){
  2695. .name = "gcc_smmu_aggre0_axi_clk",
  2696. .flags = CLK_IS_CRITICAL,
  2697. .ops = &clk_branch2_ops,
  2698. },
  2699. },
  2700. };
  2701. static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
  2702. .halt_reg = 0x81018,
  2703. .clkr = {
  2704. .enable_reg = 0x81018,
  2705. .enable_mask = BIT(0),
  2706. .hw.init = &(struct clk_init_data){
  2707. .name = "gcc_smmu_aggre0_ahb_clk",
  2708. .flags = CLK_IS_CRITICAL,
  2709. .ops = &clk_branch2_ops,
  2710. },
  2711. },
  2712. };
  2713. static struct clk_branch gcc_aggre2_ufs_axi_clk = {
  2714. .halt_reg = 0x83014,
  2715. .clkr = {
  2716. .enable_reg = 0x83014,
  2717. .enable_mask = BIT(0),
  2718. .hw.init = &(struct clk_init_data){
  2719. .name = "gcc_aggre2_ufs_axi_clk",
  2720. .parent_hws = (const struct clk_hw*[]){
  2721. &ufs_axi_clk_src.clkr.hw,
  2722. },
  2723. .num_parents = 1,
  2724. .flags = CLK_SET_RATE_PARENT,
  2725. .ops = &clk_branch2_ops,
  2726. },
  2727. },
  2728. };
  2729. static struct clk_branch gcc_aggre2_usb3_axi_clk = {
  2730. .halt_reg = 0x83018,
  2731. .clkr = {
  2732. .enable_reg = 0x83018,
  2733. .enable_mask = BIT(0),
  2734. .hw.init = &(struct clk_init_data){
  2735. .name = "gcc_aggre2_usb3_axi_clk",
  2736. .parent_hws = (const struct clk_hw*[]){
  2737. &usb30_master_clk_src.clkr.hw,
  2738. },
  2739. .num_parents = 1,
  2740. .flags = CLK_SET_RATE_PARENT,
  2741. .ops = &clk_branch2_ops,
  2742. },
  2743. },
  2744. };
  2745. static struct clk_branch gcc_dcc_ahb_clk = {
  2746. .halt_reg = 0x84004,
  2747. .clkr = {
  2748. .enable_reg = 0x84004,
  2749. .enable_mask = BIT(0),
  2750. .hw.init = &(struct clk_init_data){
  2751. .name = "gcc_dcc_ahb_clk",
  2752. .ops = &clk_branch2_ops,
  2753. },
  2754. },
  2755. };
  2756. static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
  2757. .halt_reg = 0x85000,
  2758. .clkr = {
  2759. .enable_reg = 0x85000,
  2760. .enable_mask = BIT(0),
  2761. .hw.init = &(struct clk_init_data){
  2762. .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
  2763. .ops = &clk_branch2_ops,
  2764. },
  2765. },
  2766. };
  2767. static struct clk_branch gcc_qspi_ahb_clk = {
  2768. .halt_reg = 0x8b004,
  2769. .clkr = {
  2770. .enable_reg = 0x8b004,
  2771. .enable_mask = BIT(0),
  2772. .hw.init = &(struct clk_init_data){
  2773. .name = "gcc_qspi_ahb_clk",
  2774. .ops = &clk_branch2_ops,
  2775. },
  2776. },
  2777. };
  2778. static struct clk_branch gcc_qspi_ser_clk = {
  2779. .halt_reg = 0x8b008,
  2780. .clkr = {
  2781. .enable_reg = 0x8b008,
  2782. .enable_mask = BIT(0),
  2783. .hw.init = &(struct clk_init_data){
  2784. .name = "gcc_qspi_ser_clk",
  2785. .parent_hws = (const struct clk_hw*[]){
  2786. &qspi_ser_clk_src.clkr.hw,
  2787. },
  2788. .num_parents = 1,
  2789. .flags = CLK_SET_RATE_PARENT,
  2790. .ops = &clk_branch2_ops,
  2791. },
  2792. },
  2793. };
  2794. static struct clk_branch gcc_usb3_clkref_clk = {
  2795. .halt_reg = 0x8800C,
  2796. .clkr = {
  2797. .enable_reg = 0x8800C,
  2798. .enable_mask = BIT(0),
  2799. .hw.init = &(struct clk_init_data){
  2800. .name = "gcc_usb3_clkref_clk",
  2801. .parent_data = &(const struct clk_parent_data){
  2802. .fw_name = "cxo2",
  2803. .name = "xo",
  2804. },
  2805. .num_parents = 1,
  2806. .ops = &clk_branch2_ops,
  2807. },
  2808. },
  2809. };
  2810. static struct clk_branch gcc_hdmi_clkref_clk = {
  2811. .halt_reg = 0x88000,
  2812. .clkr = {
  2813. .enable_reg = 0x88000,
  2814. .enable_mask = BIT(0),
  2815. .hw.init = &(struct clk_init_data){
  2816. .name = "gcc_hdmi_clkref_clk",
  2817. .parent_data = &(const struct clk_parent_data){
  2818. .fw_name = "cxo2",
  2819. .name = "xo",
  2820. },
  2821. .num_parents = 1,
  2822. .ops = &clk_branch2_ops,
  2823. },
  2824. },
  2825. };
  2826. static struct clk_branch gcc_edp_clkref_clk = {
  2827. .halt_reg = 0x88004,
  2828. .clkr = {
  2829. .enable_reg = 0x88004,
  2830. .enable_mask = BIT(0),
  2831. .hw.init = &(struct clk_init_data){
  2832. .name = "gcc_edp_clkref_clk",
  2833. .parent_data = &(const struct clk_parent_data){
  2834. .fw_name = "cxo2",
  2835. .name = "xo",
  2836. },
  2837. .num_parents = 1,
  2838. .ops = &clk_branch2_ops,
  2839. },
  2840. },
  2841. };
  2842. static struct clk_branch gcc_ufs_clkref_clk = {
  2843. .halt_reg = 0x88008,
  2844. .clkr = {
  2845. .enable_reg = 0x88008,
  2846. .enable_mask = BIT(0),
  2847. .hw.init = &(struct clk_init_data){
  2848. .name = "gcc_ufs_clkref_clk",
  2849. .parent_data = &(const struct clk_parent_data){
  2850. .fw_name = "cxo2",
  2851. .name = "xo",
  2852. },
  2853. .num_parents = 1,
  2854. .ops = &clk_branch2_ops,
  2855. },
  2856. },
  2857. };
  2858. static struct clk_branch gcc_pcie_clkref_clk = {
  2859. .halt_reg = 0x88010,
  2860. .clkr = {
  2861. .enable_reg = 0x88010,
  2862. .enable_mask = BIT(0),
  2863. .hw.init = &(struct clk_init_data){
  2864. .name = "gcc_pcie_clkref_clk",
  2865. .parent_data = &(const struct clk_parent_data){
  2866. .fw_name = "cxo2",
  2867. .name = "xo",
  2868. },
  2869. .num_parents = 1,
  2870. .ops = &clk_branch2_ops,
  2871. },
  2872. },
  2873. };
  2874. static struct clk_branch gcc_rx2_usb2_clkref_clk = {
  2875. .halt_reg = 0x88014,
  2876. .clkr = {
  2877. .enable_reg = 0x88014,
  2878. .enable_mask = BIT(0),
  2879. .hw.init = &(struct clk_init_data){
  2880. .name = "gcc_rx2_usb2_clkref_clk",
  2881. .parent_data = &(const struct clk_parent_data){
  2882. .fw_name = "cxo2",
  2883. .name = "xo",
  2884. },
  2885. .num_parents = 1,
  2886. .ops = &clk_branch2_ops,
  2887. },
  2888. },
  2889. };
  2890. static struct clk_branch gcc_rx1_usb2_clkref_clk = {
  2891. .halt_reg = 0x88018,
  2892. .clkr = {
  2893. .enable_reg = 0x88018,
  2894. .enable_mask = BIT(0),
  2895. .hw.init = &(struct clk_init_data){
  2896. .name = "gcc_rx1_usb2_clkref_clk",
  2897. .parent_data = &(const struct clk_parent_data){
  2898. .fw_name = "cxo2",
  2899. .name = "xo",
  2900. },
  2901. .num_parents = 1,
  2902. .ops = &clk_branch2_ops,
  2903. },
  2904. },
  2905. };
  2906. static struct clk_branch gcc_mss_cfg_ahb_clk = {
  2907. .halt_reg = 0x8a000,
  2908. .clkr = {
  2909. .enable_reg = 0x8a000,
  2910. .enable_mask = BIT(0),
  2911. .hw.init = &(struct clk_init_data){
  2912. .name = "gcc_mss_cfg_ahb_clk",
  2913. .ops = &clk_branch2_ops,
  2914. },
  2915. },
  2916. };
  2917. static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
  2918. .halt_reg = 0x8a004,
  2919. .clkr = {
  2920. .enable_reg = 0x8a004,
  2921. .enable_mask = BIT(0),
  2922. .hw.init = &(struct clk_init_data){
  2923. .name = "gcc_mss_mnoc_bimc_axi_clk",
  2924. .ops = &clk_branch2_ops,
  2925. },
  2926. },
  2927. };
  2928. static struct clk_branch gcc_mss_snoc_axi_clk = {
  2929. .halt_reg = 0x8a024,
  2930. .clkr = {
  2931. .enable_reg = 0x8a024,
  2932. .enable_mask = BIT(0),
  2933. .hw.init = &(struct clk_init_data){
  2934. .name = "gcc_mss_snoc_axi_clk",
  2935. .ops = &clk_branch2_ops,
  2936. },
  2937. },
  2938. };
  2939. static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
  2940. .halt_reg = 0x8a028,
  2941. .clkr = {
  2942. .enable_reg = 0x8a028,
  2943. .enable_mask = BIT(0),
  2944. .hw.init = &(struct clk_init_data){
  2945. .name = "gcc_mss_q6_bimc_axi_clk",
  2946. .ops = &clk_branch2_ops,
  2947. },
  2948. },
  2949. };
  2950. static struct clk_hw *gcc_msm8996_hws[] = {
  2951. &xo.hw,
  2952. &gpll0_early_div.hw,
  2953. &ufs_tx_cfg_clk_src.hw,
  2954. &ufs_rx_cfg_clk_src.hw,
  2955. &ufs_ice_core_postdiv_clk_src.hw,
  2956. };
  2957. static struct gdsc aggre0_noc_gdsc = {
  2958. .gdscr = 0x81004,
  2959. .gds_hw_ctrl = 0x81028,
  2960. .pd = {
  2961. .name = "aggre0_noc",
  2962. },
  2963. .pwrsts = PWRSTS_OFF_ON,
  2964. .flags = VOTABLE | ALWAYS_ON,
  2965. };
  2966. static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
  2967. .gdscr = 0x7d024,
  2968. .pd = {
  2969. .name = "hlos1_vote_aggre0_noc",
  2970. },
  2971. .pwrsts = PWRSTS_OFF_ON,
  2972. .flags = VOTABLE,
  2973. };
  2974. static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
  2975. .gdscr = 0x7d034,
  2976. .pd = {
  2977. .name = "hlos1_vote_lpass_adsp",
  2978. },
  2979. .pwrsts = PWRSTS_OFF_ON,
  2980. .flags = VOTABLE,
  2981. };
  2982. static struct gdsc hlos1_vote_lpass_core_gdsc = {
  2983. .gdscr = 0x7d038,
  2984. .pd = {
  2985. .name = "hlos1_vote_lpass_core",
  2986. },
  2987. .pwrsts = PWRSTS_OFF_ON,
  2988. .flags = VOTABLE,
  2989. };
  2990. static struct gdsc usb30_gdsc = {
  2991. .gdscr = 0xf004,
  2992. .pd = {
  2993. .name = "usb30",
  2994. },
  2995. .pwrsts = PWRSTS_OFF_ON,
  2996. };
  2997. static struct gdsc pcie0_gdsc = {
  2998. .gdscr = 0x6b004,
  2999. .pd = {
  3000. .name = "pcie0",
  3001. },
  3002. .pwrsts = PWRSTS_OFF_ON,
  3003. };
  3004. static struct gdsc pcie1_gdsc = {
  3005. .gdscr = 0x6d004,
  3006. .pd = {
  3007. .name = "pcie1",
  3008. },
  3009. .pwrsts = PWRSTS_OFF_ON,
  3010. };
  3011. static struct gdsc pcie2_gdsc = {
  3012. .gdscr = 0x6e004,
  3013. .pd = {
  3014. .name = "pcie2",
  3015. },
  3016. .pwrsts = PWRSTS_OFF_ON,
  3017. };
  3018. static struct gdsc ufs_gdsc = {
  3019. .gdscr = 0x75004,
  3020. .pd = {
  3021. .name = "ufs",
  3022. },
  3023. .pwrsts = PWRSTS_OFF_ON,
  3024. };
  3025. static struct clk_regmap *gcc_msm8996_clocks[] = {
  3026. [GPLL0_EARLY] = &gpll0_early.clkr,
  3027. [GPLL0] = &gpll0.clkr,
  3028. [GPLL4_EARLY] = &gpll4_early.clkr,
  3029. [GPLL4] = &gpll4.clkr,
  3030. [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
  3031. [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
  3032. [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
  3033. [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
  3034. [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
  3035. [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
  3036. [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
  3037. [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
  3038. [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
  3039. [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
  3040. [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
  3041. [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
  3042. [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
  3043. [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
  3044. [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
  3045. [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
  3046. [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
  3047. [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
  3048. [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
  3049. [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
  3050. [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
  3051. [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
  3052. [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
  3053. [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
  3054. [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
  3055. [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
  3056. [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
  3057. [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
  3058. [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
  3059. [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
  3060. [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
  3061. [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
  3062. [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
  3063. [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
  3064. [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
  3065. [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
  3066. [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
  3067. [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
  3068. [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
  3069. [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
  3070. [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
  3071. [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
  3072. [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
  3073. [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
  3074. [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
  3075. [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
  3076. [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
  3077. [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
  3078. [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
  3079. [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
  3080. [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
  3081. [GP1_CLK_SRC] = &gp1_clk_src.clkr,
  3082. [GP2_CLK_SRC] = &gp2_clk_src.clkr,
  3083. [GP3_CLK_SRC] = &gp3_clk_src.clkr,
  3084. [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
  3085. [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
  3086. [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
  3087. [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
  3088. [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
  3089. [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
  3090. [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
  3091. [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
  3092. [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
  3093. [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
  3094. [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
  3095. [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
  3096. [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
  3097. [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
  3098. [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
  3099. [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
  3100. [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
  3101. [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
  3102. [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
  3103. [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
  3104. [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
  3105. [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
  3106. [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
  3107. [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
  3108. [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
  3109. [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
  3110. [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
  3111. [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
  3112. [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
  3113. [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
  3114. [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
  3115. [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
  3116. [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
  3117. [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
  3118. [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
  3119. [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
  3120. [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
  3121. [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
  3122. [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
  3123. [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
  3124. [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
  3125. [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
  3126. [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
  3127. [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
  3128. [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
  3129. [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
  3130. [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
  3131. [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
  3132. [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
  3133. [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
  3134. [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
  3135. [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
  3136. [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
  3137. [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
  3138. [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
  3139. [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
  3140. [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
  3141. [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
  3142. [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
  3143. [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
  3144. [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
  3145. [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
  3146. [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
  3147. [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
  3148. [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
  3149. [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
  3150. [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
  3151. [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
  3152. [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
  3153. [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
  3154. [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
  3155. [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
  3156. [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
  3157. [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
  3158. [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
  3159. [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
  3160. [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
  3161. [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
  3162. [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
  3163. [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
  3164. [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
  3165. [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
  3166. [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
  3167. [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
  3168. [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
  3169. [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
  3170. [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
  3171. [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
  3172. [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
  3173. [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
  3174. [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
  3175. [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
  3176. [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
  3177. [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
  3178. [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
  3179. [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
  3180. [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
  3181. [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
  3182. [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
  3183. [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
  3184. [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
  3185. [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
  3186. [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
  3187. [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
  3188. [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
  3189. [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
  3190. [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
  3191. [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
  3192. [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
  3193. [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
  3194. [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
  3195. [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
  3196. [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
  3197. [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
  3198. [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
  3199. [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
  3200. [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
  3201. [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
  3202. [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
  3203. [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
  3204. [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
  3205. [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
  3206. [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
  3207. [GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,
  3208. [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
  3209. [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
  3210. [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
  3211. [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
  3212. [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
  3213. [GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
  3214. [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
  3215. [GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,
  3216. };
  3217. static struct gdsc *gcc_msm8996_gdscs[] = {
  3218. [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
  3219. [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
  3220. [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
  3221. [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
  3222. [USB30_GDSC] = &usb30_gdsc,
  3223. [PCIE0_GDSC] = &pcie0_gdsc,
  3224. [PCIE1_GDSC] = &pcie1_gdsc,
  3225. [PCIE2_GDSC] = &pcie2_gdsc,
  3226. [UFS_GDSC] = &ufs_gdsc,
  3227. };
  3228. static const struct qcom_reset_map gcc_msm8996_resets[] = {
  3229. [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
  3230. [GCC_CONFIG_NOC_BCR] = { 0x5000 },
  3231. [GCC_PERIPH_NOC_BCR] = { 0x6000 },
  3232. [GCC_IMEM_BCR] = { 0x8000 },
  3233. [GCC_MMSS_BCR] = { 0x9000 },
  3234. [GCC_PIMEM_BCR] = { 0x0a000 },
  3235. [GCC_QDSS_BCR] = { 0x0c000 },
  3236. [GCC_USB_30_BCR] = { 0x0f000 },
  3237. [GCC_USB_20_BCR] = { 0x12000 },
  3238. [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
  3239. [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
  3240. [GCC_USB3_PHY_BCR] = { 0x50020 },
  3241. [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
  3242. [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
  3243. [GCC_SDCC1_BCR] = { 0x13000 },
  3244. [GCC_SDCC2_BCR] = { 0x14000 },
  3245. [GCC_SDCC3_BCR] = { 0x15000 },
  3246. [GCC_SDCC4_BCR] = { 0x16000 },
  3247. [GCC_BLSP1_BCR] = { 0x17000 },
  3248. [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
  3249. [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
  3250. [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
  3251. [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
  3252. [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
  3253. [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
  3254. [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
  3255. [GCC_BLSP1_UART4_BCR] = { 0x20000 },
  3256. [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
  3257. [GCC_BLSP1_UART5_BCR] = { 0x22000 },
  3258. [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
  3259. [GCC_BLSP1_UART6_BCR] = { 0x24000 },
  3260. [GCC_BLSP2_BCR] = { 0x25000 },
  3261. [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
  3262. [GCC_BLSP2_UART1_BCR] = { 0x27000 },
  3263. [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
  3264. [GCC_BLSP2_UART2_BCR] = { 0x29000 },
  3265. [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
  3266. [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
  3267. [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
  3268. [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
  3269. [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
  3270. [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
  3271. [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
  3272. [GCC_BLSP2_UART6_BCR] = { 0x31000 },
  3273. [GCC_PDM_BCR] = { 0x33000 },
  3274. [GCC_PRNG_BCR] = { 0x34000 },
  3275. [GCC_TSIF_BCR] = { 0x36000 },
  3276. [GCC_TCSR_BCR] = { 0x37000 },
  3277. [GCC_BOOT_ROM_BCR] = { 0x38000 },
  3278. [GCC_MSG_RAM_BCR] = { 0x39000 },
  3279. [GCC_TLMM_BCR] = { 0x3a000 },
  3280. [GCC_MPM_BCR] = { 0x3b000 },
  3281. [GCC_SEC_CTRL_BCR] = { 0x3d000 },
  3282. [GCC_SPMI_BCR] = { 0x3f000 },
  3283. [GCC_SPDM_BCR] = { 0x40000 },
  3284. [GCC_CE1_BCR] = { 0x41000 },
  3285. [GCC_BIMC_BCR] = { 0x44000 },
  3286. [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
  3287. [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
  3288. [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
  3289. [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
  3290. [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
  3291. [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
  3292. [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
  3293. [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
  3294. [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
  3295. [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
  3296. [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
  3297. [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
  3298. [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
  3299. [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
  3300. [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
  3301. [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
  3302. [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
  3303. [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
  3304. [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
  3305. [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
  3306. [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
  3307. [GCC_APB2JTAG_BCR] = { 0x4c000 },
  3308. [GCC_RBCPR_CX_BCR] = { 0x4e000 },
  3309. [GCC_RBCPR_MX_BCR] = { 0x4f000 },
  3310. [GCC_PCIE_0_BCR] = { 0x6b000 },
  3311. [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
  3312. [GCC_PCIE_1_BCR] = { 0x6d000 },
  3313. [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
  3314. [GCC_PCIE_2_BCR] = { 0x6e000 },
  3315. [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
  3316. [GCC_PCIE_PHY_BCR] = { 0x6f000 },
  3317. [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
  3318. [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
  3319. [GCC_DCD_BCR] = { 0x70000 },
  3320. [GCC_OBT_ODT_BCR] = { 0x73000 },
  3321. [GCC_UFS_BCR] = { 0x75000 },
  3322. [GCC_SSC_BCR] = { 0x63000 },
  3323. [GCC_VS_BCR] = { 0x7a000 },
  3324. [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
  3325. [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
  3326. [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
  3327. [GCC_DCC_BCR] = { 0x84000 },
  3328. [GCC_IPA_BCR] = { 0x89000 },
  3329. [GCC_QSPI_BCR] = { 0x8b000 },
  3330. [GCC_SKL_BCR] = { 0x8c000 },
  3331. [GCC_MSMPU_BCR] = { 0x8d000 },
  3332. [GCC_MSS_Q6_BCR] = { 0x8e000 },
  3333. [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
  3334. [GCC_MSS_RESTART] = { 0x8f008 },
  3335. };
  3336. static const struct regmap_config gcc_msm8996_regmap_config = {
  3337. .reg_bits = 32,
  3338. .reg_stride = 4,
  3339. .val_bits = 32,
  3340. .max_register = 0x8f010,
  3341. .fast_io = true,
  3342. };
  3343. static const struct qcom_cc_desc gcc_msm8996_desc = {
  3344. .config = &gcc_msm8996_regmap_config,
  3345. .clks = gcc_msm8996_clocks,
  3346. .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
  3347. .resets = gcc_msm8996_resets,
  3348. .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
  3349. .gdscs = gcc_msm8996_gdscs,
  3350. .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
  3351. .clk_hws = gcc_msm8996_hws,
  3352. .num_clk_hws = ARRAY_SIZE(gcc_msm8996_hws),
  3353. };
  3354. static const struct of_device_id gcc_msm8996_match_table[] = {
  3355. { .compatible = "qcom,gcc-msm8996" },
  3356. { }
  3357. };
  3358. MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
  3359. static int gcc_msm8996_probe(struct platform_device *pdev)
  3360. {
  3361. struct regmap *regmap;
  3362. regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
  3363. if (IS_ERR(regmap))
  3364. return PTR_ERR(regmap);
  3365. /*
  3366. * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
  3367. * turned off by hardware during certain apps low power modes.
  3368. */
  3369. regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
  3370. return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
  3371. }
  3372. static struct platform_driver gcc_msm8996_driver = {
  3373. .probe = gcc_msm8996_probe,
  3374. .driver = {
  3375. .name = "gcc-msm8996",
  3376. .of_match_table = gcc_msm8996_match_table,
  3377. },
  3378. };
  3379. static int __init gcc_msm8996_init(void)
  3380. {
  3381. return platform_driver_register(&gcc_msm8996_driver);
  3382. }
  3383. core_initcall(gcc_msm8996_init);
  3384. static void __exit gcc_msm8996_exit(void)
  3385. {
  3386. platform_driver_unregister(&gcc_msm8996_driver);
  3387. }
  3388. module_exit(gcc_msm8996_exit);
  3389. MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
  3390. MODULE_LICENSE("GPL v2");
  3391. MODULE_ALIAS("platform:gcc-msm8996");