1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997 |
- // SPDX-License-Identifier: GPL-2.0-only
- /*
- * Copyright 2020 Linaro Limited
- */
- #include <linux/kernel.h>
- #include <linux/bitops.h>
- #include <linux/err.h>
- #include <linux/platform_device.h>
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
- #include <linux/clk-provider.h>
- #include <linux/regmap.h>
- #include <linux/reset-controller.h>
- #include <dt-bindings/clock/qcom,gcc-msm8939.h>
- #include <dt-bindings/reset/qcom,gcc-msm8939.h>
- #include "common.h"
- #include "clk-regmap.h"
- #include "clk-pll.h"
- #include "clk-rcg.h"
- #include "clk-branch.h"
- #include "reset.h"
- #include "gdsc.h"
- enum {
- P_XO,
- P_GPLL0,
- P_GPLL0_AUX,
- P_BIMC,
- P_GPLL1,
- P_GPLL1_AUX,
- P_GPLL2,
- P_GPLL2_AUX,
- P_GPLL3,
- P_GPLL3_AUX,
- P_GPLL4,
- P_GPLL5,
- P_GPLL5_AUX,
- P_GPLL5_EARLY,
- P_GPLL6,
- P_GPLL6_AUX,
- P_SLEEP_CLK,
- P_DSI0_PHYPLL_BYTE,
- P_DSI0_PHYPLL_DSI,
- P_EXT_PRI_I2S,
- P_EXT_SEC_I2S,
- P_EXT_MCLK,
- };
- static struct clk_pll gpll0 = {
- .l_reg = 0x21004,
- .m_reg = 0x21008,
- .n_reg = 0x2100c,
- .config_reg = 0x21010,
- .mode_reg = 0x21000,
- .status_reg = 0x2101c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll0",
- .parent_data = &(const struct clk_parent_data) {
- .fw_name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
- };
- static struct clk_regmap gpll0_vote = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_vote",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &gpll0.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
- };
- static struct clk_pll gpll1 = {
- .l_reg = 0x20004,
- .m_reg = 0x20008,
- .n_reg = 0x2000c,
- .config_reg = 0x20010,
- .mode_reg = 0x20000,
- .status_reg = 0x2001c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll1",
- .parent_data = &(const struct clk_parent_data) {
- .fw_name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
- };
- static struct clk_regmap gpll1_vote = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gpll1_vote",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &gpll1.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
- };
- static struct clk_pll gpll2 = {
- .l_reg = 0x4a004,
- .m_reg = 0x4a008,
- .n_reg = 0x4a00c,
- .config_reg = 0x4a010,
- .mode_reg = 0x4a000,
- .status_reg = 0x4a01c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll2",
- .parent_data = &(const struct clk_parent_data) {
- .fw_name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
- };
- static struct clk_regmap gpll2_vote = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gpll2_vote",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &gpll2.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
- };
- static struct clk_pll bimc_pll = {
- .l_reg = 0x23004,
- .m_reg = 0x23008,
- .n_reg = 0x2300c,
- .config_reg = 0x23010,
- .mode_reg = 0x23000,
- .status_reg = 0x2301c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "bimc_pll",
- .parent_data = &(const struct clk_parent_data) {
- .fw_name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
- };
- static struct clk_regmap bimc_pll_vote = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(3),
- .hw.init = &(struct clk_init_data){
- .name = "bimc_pll_vote",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &bimc_pll.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
- };
- static struct clk_pll gpll3 = {
- .l_reg = 0x22004,
- .m_reg = 0x22008,
- .n_reg = 0x2200c,
- .config_reg = 0x22010,
- .mode_reg = 0x22000,
- .status_reg = 0x2201c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll3",
- .parent_data = &(const struct clk_parent_data) {
- .fw_name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
- };
- static struct clk_regmap gpll3_vote = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "gpll3_vote",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &gpll3.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
- };
- /* GPLL3 at 1100 MHz, main output enabled. */
- static const struct pll_config gpll3_config = {
- .l = 57,
- .m = 7,
- .n = 24,
- .vco_val = 0x0,
- .vco_mask = BIT(20),
- .pre_div_val = 0x0,
- .pre_div_mask = BIT(12),
- .post_div_val = 0x0,
- .post_div_mask = BIT(9) | BIT(8),
- .mn_ena_mask = BIT(24),
- .main_output_mask = BIT(0),
- .aux_output_mask = BIT(1),
- };
- static struct clk_pll gpll4 = {
- .l_reg = 0x24004,
- .m_reg = 0x24008,
- .n_reg = 0x2400c,
- .config_reg = 0x24010,
- .mode_reg = 0x24000,
- .status_reg = 0x2401c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll4",
- .parent_data = &(const struct clk_parent_data) {
- .fw_name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
- };
- static struct clk_regmap gpll4_vote = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(5),
- .hw.init = &(struct clk_init_data){
- .name = "gpll4_vote",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &gpll4.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
- };
- /* GPLL4 at 1200 MHz, main output enabled. */
- static struct pll_config gpll4_config = {
- .l = 62,
- .m = 1,
- .n = 2,
- .vco_val = 0x0,
- .vco_mask = BIT(20),
- .pre_div_val = 0x0,
- .pre_div_mask = BIT(12),
- .post_div_val = 0x0,
- .post_div_mask = BIT(9) | BIT(8),
- .mn_ena_mask = BIT(24),
- .main_output_mask = BIT(0),
- };
- static struct clk_pll gpll5 = {
- .l_reg = 0x25004,
- .m_reg = 0x25008,
- .n_reg = 0x2500c,
- .config_reg = 0x25010,
- .mode_reg = 0x25000,
- .status_reg = 0x2501c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll5",
- .parent_data = &(const struct clk_parent_data) {
- .fw_name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
- };
- static struct clk_regmap gpll5_vote = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(6),
- .hw.init = &(struct clk_init_data){
- .name = "gpll5_vote",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &gpll5.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
- };
- static struct clk_pll gpll6 = {
- .l_reg = 0x37004,
- .m_reg = 0x37008,
- .n_reg = 0x3700c,
- .config_reg = 0x37010,
- .mode_reg = 0x37000,
- .status_reg = 0x3701c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll6",
- .parent_data = &(const struct clk_parent_data) {
- .fw_name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
- };
- static struct clk_regmap gpll6_vote = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(7),
- .hw.init = &(struct clk_init_data){
- .name = "gpll6_vote",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &gpll6.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
- };
- static const struct parent_map gcc_xo_gpll0_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- };
- static const struct clk_parent_data gcc_xo_gpll0_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- };
- static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_BIMC, 2 },
- };
- static const struct clk_parent_data gcc_xo_gpll0_bimc_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .hw = &bimc_pll_vote.hw },
- };
- static const struct parent_map gcc_xo_gpll0_gpll6a_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL6_AUX, 2 },
- };
- static const struct clk_parent_data gcc_xo_gpll0_gpll6a_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .hw = &gpll6_vote.hw },
- };
- static const struct parent_map gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL2_AUX, 4 },
- { P_GPLL3, 2 },
- { P_GPLL6_AUX, 3 },
- };
- static const struct clk_parent_data gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .hw = &gpll2_vote.hw },
- { .hw = &gpll3_vote.hw },
- { .hw = &gpll6_vote.hw },
- };
- static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL2, 2 },
- };
- static const struct clk_parent_data gcc_xo_gpll0_gpll2_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .hw = &gpll2_vote.hw },
- };
- static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL2, 3 },
- { P_GPLL4, 2 },
- };
- static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .hw = &gpll2_vote.hw },
- { .hw = &gpll4_vote.hw },
- };
- static const struct parent_map gcc_xo_gpll0a_map[] = {
- { P_XO, 0 },
- { P_GPLL0_AUX, 2 },
- };
- static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- };
- static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL1_AUX, 2 },
- { P_SLEEP_CLK, 6 },
- };
- static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .hw = &gpll1_vote.hw },
- { .fw_name = "sleep_clk", .name = "sleep_clk" },
- };
- static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL1_AUX, 2 },
- { P_GPLL6, 2 },
- { P_SLEEP_CLK, 6 },
- };
- static const struct clk_parent_data gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .hw = &gpll1_vote.hw },
- { .hw = &gpll6_vote.hw },
- { .fw_name = "sleep_clk", .name = "sleep_clk" },
- };
- static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL1_AUX, 2 },
- };
- static const struct clk_parent_data gcc_xo_gpll0_gpll1a_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .hw = &gpll1_vote.hw },
- };
- static const struct parent_map gcc_xo_dsibyte_map[] = {
- { P_XO, 0, },
- { P_DSI0_PHYPLL_BYTE, 2 },
- };
- static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] = {
- { .fw_name = "xo" },
- { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
- };
- static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
- { P_XO, 0 },
- { P_GPLL0_AUX, 2 },
- { P_DSI0_PHYPLL_BYTE, 1 },
- };
- static const struct clk_parent_data gcc_xo_gpll0a_dsibyte_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
- };
- static const struct parent_map gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map[] = {
- { P_XO, 0 },
- { P_GPLL1, 1 },
- { P_DSI0_PHYPLL_DSI, 2 },
- { P_GPLL6, 3 },
- { P_GPLL3_AUX, 4 },
- { P_GPLL0_AUX, 5 },
- };
- static const struct clk_parent_data gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll1_vote.hw },
- { .fw_name = "dsi0pll", .name = "dsi0pll" },
- { .hw = &gpll6_vote.hw },
- { .hw = &gpll3_vote.hw },
- { .hw = &gpll0_vote.hw },
- };
- static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
- { P_XO, 0 },
- { P_GPLL0_AUX, 2 },
- { P_DSI0_PHYPLL_DSI, 1 },
- };
- static const struct clk_parent_data gcc_xo_gpll0a_dsiphy_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .fw_name = "dsi0pll", .name = "dsi0pll" },
- };
- static const struct parent_map gcc_xo_gpll0_gpll5a_gpll6_bimc_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL5_AUX, 3 },
- { P_GPLL6, 2 },
- { P_BIMC, 4 },
- };
- static const struct clk_parent_data gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .hw = &gpll5_vote.hw },
- { .hw = &gpll6_vote.hw },
- { .hw = &bimc_pll_vote.hw },
- };
- static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL1, 2 },
- { P_SLEEP_CLK, 6 }
- };
- static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .hw = &gpll1_vote.hw },
- { .fw_name = "sleep_clk", .name = "sleep_clk" },
- };
- static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
- { P_XO, 0 },
- { P_GPLL1, 1 },
- { P_EXT_PRI_I2S, 2 },
- { P_EXT_MCLK, 3 },
- { P_SLEEP_CLK, 6 }
- };
- static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0_vote.hw },
- { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
- { .fw_name = "ext_mclk", .name = "ext_mclk" },
- { .fw_name = "sleep_clk", .name = "sleep_clk" },
- };
- static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
- { P_XO, 0 },
- { P_GPLL1, 1 },
- { P_EXT_SEC_I2S, 2 },
- { P_EXT_MCLK, 3 },
- { P_SLEEP_CLK, 6 }
- };
- static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll1_vote.hw },
- { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
- { .fw_name = "ext_mclk", .name = "ext_mclk" },
- { .fw_name = "sleep_clk", .name = "sleep_clk" },
- };
- static const struct parent_map gcc_xo_sleep_map[] = {
- { P_XO, 0 },
- { P_SLEEP_CLK, 6 }
- };
- static const struct clk_parent_data gcc_xo_sleep_parent_data[] = {
- { .fw_name = "xo" },
- { .fw_name = "sleep_clk", .name = "sleep_clk" },
- };
- static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
- { P_XO, 0 },
- { P_GPLL1, 1 },
- { P_EXT_MCLK, 2 },
- { P_SLEEP_CLK, 6 }
- };
- static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll1_vote.hw },
- { .fw_name = "ext_mclk", .name = "ext_mclk" },
- { .fw_name = "sleep_clk", .name = "sleep_clk" },
- };
- static const struct clk_parent_data gcc_xo_gpll6_gpll0_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll6_vote.hw },
- { .hw = &gpll0_vote.hw },
- };
- static const struct clk_parent_data gcc_xo_gpll6_gpll0a_parent_data[] = {
- { .fw_name = "xo" },
- { .hw = &gpll6_vote.hw },
- { .hw = &gpll0_vote.hw },
- };
- static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
- .cmd_rcgr = 0x27000,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcnoc_bfdcd_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 system_noc_bfdcd_clk_src = {
- .cmd_rcgr = 0x26004,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll6a_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_bfdcd_clk_src",
- .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 bimc_ddr_clk_src = {
- .cmd_rcgr = 0x32024,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_bimc_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "bimc_ddr_clk_src",
- .parent_data = gcc_xo_gpll0_bimc_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_parent_data),
- .ops = &clk_rcg2_ops,
- .flags = CLK_GET_RATE_NOCACHE,
- },
- };
- static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = {
- .cmd_rcgr = 0x2600c,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll6a_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_mm_noc_bfdcd_clk_src",
- .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
- F(40000000, P_GPLL0, 10, 1, 2),
- F(80000000, P_GPLL0, 10, 0, 0),
- { }
- };
- static struct clk_rcg2 camss_ahb_clk_src = {
- .cmd_rcgr = 0x5a000,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_camss_ahb_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "camss_ahb_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_apss_ahb_clk[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(50000000, P_GPLL0, 16, 0, 0),
- F(100000000, P_GPLL0, 8, 0, 0),
- F(133330000, P_GPLL0, 6, 0, 0),
- { }
- };
- static struct clk_rcg2 apss_ahb_clk_src = {
- .cmd_rcgr = 0x46000,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_apss_ahb_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "apss_ahb_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
- F(100000000, P_GPLL0, 8, 0, 0),
- F(200000000, P_GPLL0, 4, 0, 0),
- { }
- };
- static struct clk_rcg2 csi0_clk_src = {
- .cmd_rcgr = 0x4e020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "csi0_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 csi1_clk_src = {
- .cmd_rcgr = 0x4f020,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "csi1_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(50000000, P_GPLL0, 16, 0, 0),
- F(80000000, P_GPLL0, 10, 0, 0),
- F(100000000, P_GPLL0, 8, 0, 0),
- F(160000000, P_GPLL0, 5, 0, 0),
- F(200000000, P_GPLL0, 4, 0, 0),
- F(220000000, P_GPLL3, 5, 0, 0),
- F(266670000, P_GPLL0, 3, 0, 0),
- F(310000000, P_GPLL2_AUX, 3, 0, 0),
- F(400000000, P_GPLL0, 2, 0, 0),
- F(465000000, P_GPLL2_AUX, 2, 0, 0),
- F(550000000, P_GPLL3, 2, 0, 0),
- { }
- };
- static struct clk_rcg2 gfx3d_clk_src = {
- .cmd_rcgr = 0x59000,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map,
- .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gfx3d_clk_src",
- .parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
- F(50000000, P_GPLL0, 16, 0, 0),
- F(80000000, P_GPLL0, 10, 0, 0),
- F(100000000, P_GPLL0, 8, 0, 0),
- F(160000000, P_GPLL0, 5, 0, 0),
- F(177780000, P_GPLL0, 4.5, 0, 0),
- F(200000000, P_GPLL0, 4, 0, 0),
- F(266670000, P_GPLL0, 3, 0, 0),
- F(320000000, P_GPLL0, 2.5, 0, 0),
- F(400000000, P_GPLL0, 2, 0, 0),
- F(465000000, P_GPLL2, 2, 0, 0),
- F(480000000, P_GPLL4, 2.5, 0, 0),
- F(600000000, P_GPLL4, 2, 0, 0),
- { }
- };
- static struct clk_rcg2 vfe0_clk_src = {
- .cmd_rcgr = 0x58000,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
- .freq_tbl = ftbl_gcc_camss_vfe0_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "vfe0_clk_src",
- .parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(50000000, P_GPLL0, 16, 0, 0),
- { }
- };
- static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
- .cmd_rcgr = 0x0200c,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
- F(960000, P_XO, 10, 1, 2),
- F(4800000, P_XO, 4, 0, 0),
- F(9600000, P_XO, 2, 0, 0),
- F(16000000, P_GPLL0, 10, 1, 5),
- F(19200000, P_XO, 1, 0, 0),
- F(25000000, P_GPLL0, 16, 1, 2),
- F(50000000, P_GPLL0, 16, 0, 0),
- { }
- };
- static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
- .cmd_rcgr = 0x02024,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
- .cmd_rcgr = 0x03000,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
- .cmd_rcgr = 0x03014,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
- .cmd_rcgr = 0x04000,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
- .cmd_rcgr = 0x04024,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
- .cmd_rcgr = 0x05000,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
- .cmd_rcgr = 0x05024,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
- .cmd_rcgr = 0x06000,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
- .cmd_rcgr = 0x06024,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
- .cmd_rcgr = 0x07000,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_i2c_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
- .cmd_rcgr = 0x07024,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_spi_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
- F(3686400, P_GPLL0, 1, 72, 15625),
- F(7372800, P_GPLL0, 1, 144, 15625),
- F(14745600, P_GPLL0, 1, 288, 15625),
- F(16000000, P_GPLL0, 10, 1, 5),
- F(19200000, P_XO, 1, 0, 0),
- F(24000000, P_GPLL0, 1, 3, 100),
- F(25000000, P_GPLL0, 16, 1, 2),
- F(32000000, P_GPLL0, 1, 1, 25),
- F(40000000, P_GPLL0, 1, 1, 20),
- F(46400000, P_GPLL0, 1, 29, 500),
- F(48000000, P_GPLL0, 1, 3, 50),
- F(51200000, P_GPLL0, 1, 8, 125),
- F(56000000, P_GPLL0, 1, 7, 100),
- F(58982400, P_GPLL0, 1, 1152, 15625),
- F(60000000, P_GPLL0, 1, 3, 40),
- { }
- };
- static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
- .cmd_rcgr = 0x02044,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart1_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
- .cmd_rcgr = 0x03034,
- .mnd_width = 16,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart2_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(37500000, P_GPLL0, 1, 3, 64),
- { }
- };
- static struct clk_rcg2 cci_clk_src = {
- .cmd_rcgr = 0x51000,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0a_map,
- .freq_tbl = ftbl_gcc_camss_cci_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "cci_clk_src",
- .parent_data = gcc_xo_gpll0a_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
- F(100000000, P_GPLL0, 8, 0, 0),
- F(200000000, P_GPLL0, 4, 0, 0),
- { }
- };
- static struct clk_rcg2 camss_gp0_clk_src = {
- .cmd_rcgr = 0x54000,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
- .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "camss_gp0_clk_src",
- .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 camss_gp1_clk_src = {
- .cmd_rcgr = 0x55000,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
- .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "camss_gp1_clk_src",
- .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
- F(133330000, P_GPLL0, 6, 0, 0),
- F(266670000, P_GPLL0, 3, 0, 0),
- F(320000000, P_GPLL0, 2.5, 0, 0),
- { }
- };
- static struct clk_rcg2 jpeg0_clk_src = {
- .cmd_rcgr = 0x57000,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "jpeg0_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
- F(24000000, P_GPLL0, 1, 1, 45),
- F(66670000, P_GPLL0, 12, 0, 0),
- { }
- };
- static struct clk_rcg2 mclk0_clk_src = {
- .cmd_rcgr = 0x52000,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
- .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mclk0_clk_src",
- .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 mclk1_clk_src = {
- .cmd_rcgr = 0x53000,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
- .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mclk1_clk_src",
- .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
- F(100000000, P_GPLL0, 8, 0, 0),
- F(200000000, P_GPLL0, 4, 0, 0),
- { }
- };
- static struct clk_rcg2 csi0phytimer_clk_src = {
- .cmd_rcgr = 0x4e000,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll1a_map,
- .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "csi0phytimer_clk_src",
- .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 csi1phytimer_clk_src = {
- .cmd_rcgr = 0x4f000,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll1a_map,
- .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "csi1phytimer_clk_src",
- .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
- F(160000000, P_GPLL0, 5, 0, 0),
- F(200000000, P_GPLL0, 4, 0, 0),
- F(228570000, P_GPLL0, 3.5, 0, 0),
- F(266670000, P_GPLL0, 3, 0, 0),
- F(320000000, P_GPLL0, 2.5, 0, 0),
- F(465000000, P_GPLL2, 2, 0, 0),
- { }
- };
- static struct clk_rcg2 cpp_clk_src = {
- .cmd_rcgr = 0x58018,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll2_map,
- .freq_tbl = ftbl_gcc_camss_cpp_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "cpp_clk_src",
- .parent_data = gcc_xo_gpll0_gpll2_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
- F(50000000, P_GPLL0, 16, 0, 0),
- F(80000000, P_GPLL0, 10, 0, 0),
- F(100000000, P_GPLL0, 8, 0, 0),
- F(160000000, P_GPLL0, 5, 0, 0),
- { }
- };
- /* This is not in the documentation but is in the downstream driver */
- static struct clk_rcg2 crypto_clk_src = {
- .cmd_rcgr = 0x16004,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_crypto_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "crypto_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
- F(19200000, P_XO, 1, 0, 0),
- { }
- };
- static struct clk_rcg2 gp1_clk_src = {
- .cmd_rcgr = 0x08004,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
- .freq_tbl = ftbl_gcc_gp1_3_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp1_clk_src",
- .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 gp2_clk_src = {
- .cmd_rcgr = 0x09004,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
- .freq_tbl = ftbl_gcc_gp1_3_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp2_clk_src",
- .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 gp3_clk_src = {
- .cmd_rcgr = 0x0a004,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
- .freq_tbl = ftbl_gcc_gp1_3_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp3_clk_src",
- .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 byte0_clk_src = {
- .cmd_rcgr = 0x4d044,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0a_dsibyte_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "byte0_clk_src",
- .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
- .ops = &clk_byte2_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- };
- static struct clk_rcg2 byte1_clk_src = {
- .cmd_rcgr = 0x4d0b0,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0a_dsibyte_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "byte1_clk_src",
- .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
- .ops = &clk_byte2_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- };
- static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] = {
- F(19200000, P_XO, 1, 0, 0),
- { }
- };
- static struct clk_rcg2 esc0_clk_src = {
- .cmd_rcgr = 0x4d060,
- .hid_width = 5,
- .parent_map = gcc_xo_dsibyte_map,
- .freq_tbl = ftbl_gcc_mdss_esc_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "esc0_clk_src",
- .parent_data = gcc_xo_dsibyte_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 esc1_clk_src = {
- .cmd_rcgr = 0x4d0a8,
- .hid_width = 5,
- .parent_map = gcc_xo_dsibyte_map,
- .freq_tbl = ftbl_gcc_mdss_esc_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "esc1_clk_src",
- .parent_data = gcc_xo_dsibyte_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
- F(50000000, P_GPLL0_AUX, 16, 0, 0),
- F(80000000, P_GPLL0_AUX, 10, 0, 0),
- F(100000000, P_GPLL0_AUX, 8, 0, 0),
- F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
- F(153600000, P_GPLL0, 4, 0, 0),
- F(160000000, P_GPLL0_AUX, 5, 0, 0),
- F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
- F(200000000, P_GPLL0_AUX, 4, 0, 0),
- F(266670000, P_GPLL0_AUX, 3, 0, 0),
- F(307200000, P_GPLL1, 2, 0, 0),
- F(366670000, P_GPLL3_AUX, 3, 0, 0),
- { }
- };
- static struct clk_rcg2 mdp_clk_src = {
- .cmd_rcgr = 0x4d014,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map,
- .freq_tbl = ftbl_gcc_mdss_mdp_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mdp_clk_src",
- .parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_rcg2 pclk0_clk_src = {
- .cmd_rcgr = 0x4d000,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0a_dsiphy_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pclk0_clk_src",
- .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
- .ops = &clk_pixel_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- };
- static struct clk_rcg2 pclk1_clk_src = {
- .cmd_rcgr = 0x4d0b8,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0a_dsiphy_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pclk1_clk_src",
- .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
- .ops = &clk_pixel_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- };
- static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
- F(19200000, P_XO, 1, 0, 0),
- { }
- };
- static struct clk_rcg2 vsync_clk_src = {
- .cmd_rcgr = 0x4d02c,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0a_map,
- .freq_tbl = ftbl_gcc_mdss_vsync_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "vsync_clk_src",
- .parent_data = gcc_xo_gpll0a_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
- F(64000000, P_GPLL0, 12.5, 0, 0),
- { }
- };
- /* This is not in the documentation but is in the downstream driver */
- static struct clk_rcg2 pdm2_clk_src = {
- .cmd_rcgr = 0x44010,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_pdm2_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pdm2_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
- F(144000, P_XO, 16, 3, 25),
- F(400000, P_XO, 12, 1, 4),
- F(20000000, P_GPLL0, 10, 1, 4),
- F(25000000, P_GPLL0, 16, 1, 2),
- F(50000000, P_GPLL0, 16, 0, 0),
- F(100000000, P_GPLL0, 8, 0, 0),
- F(177770000, P_GPLL0, 4.5, 0, 0),
- F(200000000, P_GPLL0, 4, 0, 0),
- { }
- };
- static struct clk_rcg2 sdcc1_apps_clk_src = {
- .cmd_rcgr = 0x42004,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_sdcc_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_floor_ops,
- },
- };
- static struct clk_rcg2 sdcc2_apps_clk_src = {
- .cmd_rcgr = 0x43004,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_sdcc_apps_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc2_apps_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_floor_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
- F(154285000, P_GPLL6, 7, 0, 0),
- F(320000000, P_GPLL0, 2.5, 0, 0),
- F(400000000, P_GPLL0, 2, 0, 0),
- { }
- };
- static struct clk_rcg2 apss_tcu_clk_src = {
- .cmd_rcgr = 0x1207c,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
- .freq_tbl = ftbl_gcc_apss_tcu_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "apss_tcu_clk_src",
- .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(100000000, P_GPLL0, 8, 0, 0),
- F(200000000, P_GPLL0, 4, 0, 0),
- F(266500000, P_BIMC, 4, 0, 0),
- F(400000000, P_GPLL0, 2, 0, 0),
- F(533000000, P_BIMC, 2, 0, 0),
- { }
- };
- static struct clk_rcg2 bimc_gpu_clk_src = {
- .cmd_rcgr = 0x31028,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
- .freq_tbl = ftbl_gcc_bimc_gpu_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "bimc_gpu_clk_src",
- .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
- .flags = CLK_GET_RATE_NOCACHE,
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
- F(57140000, P_GPLL0, 14, 0, 0),
- F(80000000, P_GPLL0, 10, 0, 0),
- F(100000000, P_GPLL0, 8, 0, 0),
- { }
- };
- static struct clk_rcg2 usb_hs_system_clk_src = {
- .cmd_rcgr = 0x41010,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_usb_hs_system_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb_hs_system_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
- F(64000000, P_GPLL0, 12.5, 0, 0),
- { }
- };
- static struct clk_rcg2 usb_fs_system_clk_src = {
- .cmd_rcgr = 0x3f010,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_usb_fs_system_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb_fs_system_clk_src",
- .parent_data = gcc_xo_gpll6_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
- F(60000000, P_GPLL6, 1, 1, 18),
- { }
- };
- static struct clk_rcg2 usb_fs_ic_clk_src = {
- .cmd_rcgr = 0x3f034,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb_fs_ic_clk_src",
- .parent_data = gcc_xo_gpll6_gpll0a_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0a_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
- F(3200000, P_XO, 6, 0, 0),
- F(6400000, P_XO, 3, 0, 0),
- F(9600000, P_XO, 2, 0, 0),
- F(19200000, P_XO, 1, 0, 0),
- F(40000000, P_GPLL0, 10, 1, 2),
- F(66670000, P_GPLL0, 12, 0, 0),
- F(80000000, P_GPLL0, 10, 0, 0),
- F(100000000, P_GPLL0, 8, 0, 0),
- { }
- };
- static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
- .cmd_rcgr = 0x1c010,
- .hid_width = 5,
- .mnd_width = 8,
- .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
- .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ultaudio_ahbfabric_clk_src",
- .parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
- .halt_reg = 0x1c028,
- .clkr = {
- .enable_reg = 0x1c028,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ultaudio_ahbfabric_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
- .halt_reg = 0x1c024,
- .clkr = {
- .enable_reg = 0x1c024,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ultaudio_ahbfabric_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
- F(128000, P_XO, 10, 1, 15),
- F(256000, P_XO, 5, 1, 15),
- F(384000, P_XO, 5, 1, 10),
- F(512000, P_XO, 5, 2, 15),
- F(576000, P_XO, 5, 3, 20),
- F(705600, P_GPLL1, 16, 1, 80),
- F(768000, P_XO, 5, 1, 5),
- F(800000, P_XO, 5, 5, 24),
- F(1024000, P_XO, 5, 4, 15),
- F(1152000, P_XO, 1, 3, 50),
- F(1411200, P_GPLL1, 16, 1, 40),
- F(1536000, P_XO, 1, 2, 25),
- F(1600000, P_XO, 12, 0, 0),
- F(1728000, P_XO, 5, 9, 20),
- F(2048000, P_XO, 5, 8, 15),
- F(2304000, P_XO, 5, 3, 5),
- F(2400000, P_XO, 8, 0, 0),
- F(2822400, P_GPLL1, 16, 1, 20),
- F(3072000, P_XO, 5, 4, 5),
- F(4096000, P_GPLL1, 9, 2, 49),
- F(4800000, P_XO, 4, 0, 0),
- F(5644800, P_GPLL1, 16, 1, 10),
- F(6144000, P_GPLL1, 7, 1, 21),
- F(8192000, P_GPLL1, 9, 4, 49),
- F(9600000, P_XO, 2, 0, 0),
- F(11289600, P_GPLL1, 16, 1, 5),
- F(12288000, P_GPLL1, 7, 2, 21),
- { }
- };
- static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
- .cmd_rcgr = 0x1c054,
- .hid_width = 5,
- .mnd_width = 8,
- .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
- .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ultaudio_lpaif_pri_i2s_clk_src",
- .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
- .halt_reg = 0x1c068,
- .clkr = {
- .enable_reg = 0x1c068,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
- .cmd_rcgr = 0x1c06c,
- .hid_width = 5,
- .mnd_width = 8,
- .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
- .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ultaudio_lpaif_sec_i2s_clk_src",
- .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
- .halt_reg = 0x1c080,
- .clkr = {
- .enable_reg = 0x1c080,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
- .cmd_rcgr = 0x1c084,
- .hid_width = 5,
- .mnd_width = 8,
- .parent_map = gcc_xo_gpll1_emclk_sleep_map,
- .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ultaudio_lpaif_aux_i2s_clk_src",
- .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
- .halt_reg = 0x1c098,
- .clkr = {
- .enable_reg = 0x1c098,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
- F(19200000, P_XO, 1, 0, 0),
- { }
- };
- static struct clk_rcg2 ultaudio_xo_clk_src = {
- .cmd_rcgr = 0x1c034,
- .hid_width = 5,
- .parent_map = gcc_xo_sleep_map,
- .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ultaudio_xo_clk_src",
- .parent_data = gcc_xo_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
- .halt_reg = 0x1c04c,
- .clkr = {
- .enable_reg = 0x1c04c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ultaudio_avsync_xo_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ultaudio_xo_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ultaudio_stc_xo_clk = {
- .halt_reg = 0x1c050,
- .clkr = {
- .enable_reg = 0x1c050,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ultaudio_stc_xo_clk",
- .parent_hws = (const struct clk_hw*[]){
- &ultaudio_xo_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static const struct freq_tbl ftbl_codec_clk[] = {
- F(9600000, P_XO, 2, 0, 0),
- F(12288000, P_XO, 1, 16, 25),
- F(19200000, P_XO, 1, 0, 0),
- F(11289600, P_EXT_MCLK, 1, 0, 0),
- { }
- };
- static struct clk_rcg2 codec_digcodec_clk_src = {
- .cmd_rcgr = 0x1c09c,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll1_emclk_sleep_map,
- .freq_tbl = ftbl_codec_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "codec_digcodec_clk_src",
- .parent_data = gcc_xo_gpll1_emclk_sleep_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_branch gcc_codec_digcodec_clk = {
- .halt_reg = 0x1c0b0,
- .clkr = {
- .enable_reg = 0x1c0b0,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ultaudio_codec_digcodec_clk",
- .parent_hws = (const struct clk_hw*[]){
- &codec_digcodec_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
- .halt_reg = 0x1c000,
- .clkr = {
- .enable_reg = 0x1c000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ultaudio_pcnoc_mport_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
- .halt_reg = 0x1c004,
- .clkr = {
- .enable_reg = 0x1c004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ultaudio_pcnoc_sway_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
- F(133330000, P_GPLL0, 6, 0, 0),
- F(200000000, P_GPLL0, 4, 0, 0),
- F(266670000, P_GPLL0, 3, 0, 0),
- { }
- };
- static struct clk_rcg2 vcodec0_clk_src = {
- .cmd_rcgr = 0x4C000,
- .mnd_width = 8,
- .hid_width = 5,
- .parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "vcodec0_clk_src",
- .parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
- .ops = &clk_rcg2_ops,
- },
- };
- static struct clk_branch gcc_blsp1_ahb_clk = {
- .halt_reg = 0x01008,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x45004,
- .enable_mask = BIT(10),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_sleep_clk = {
- .halt_reg = 0x01004,
- .clkr = {
- .enable_reg = 0x01004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_sleep_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
- .halt_reg = 0x02008,
- .clkr = {
- .enable_reg = 0x02008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
- .halt_reg = 0x02004,
- .clkr = {
- .enable_reg = 0x02004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup1_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
- .halt_reg = 0x03010,
- .clkr = {
- .enable_reg = 0x03010,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
- .halt_reg = 0x0300c,
- .clkr = {
- .enable_reg = 0x0300c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup2_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
- .halt_reg = 0x04020,
- .clkr = {
- .enable_reg = 0x04020,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
- .halt_reg = 0x0401c,
- .clkr = {
- .enable_reg = 0x0401c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup3_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
- .halt_reg = 0x05020,
- .clkr = {
- .enable_reg = 0x05020,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
- .halt_reg = 0x0501c,
- .clkr = {
- .enable_reg = 0x0501c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup4_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
- .halt_reg = 0x06020,
- .clkr = {
- .enable_reg = 0x06020,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
- .halt_reg = 0x0601c,
- .clkr = {
- .enable_reg = 0x0601c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup5_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
- .halt_reg = 0x07020,
- .clkr = {
- .enable_reg = 0x07020,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_i2c_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
- .halt_reg = 0x0701c,
- .clkr = {
- .enable_reg = 0x0701c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_spi_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_qup6_spi_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_uart1_apps_clk = {
- .halt_reg = 0x0203c,
- .clkr = {
- .enable_reg = 0x0203c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart1_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_uart1_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_blsp1_uart2_apps_clk = {
- .halt_reg = 0x0302c,
- .clkr = {
- .enable_reg = 0x0302c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart2_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &blsp1_uart2_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_boot_rom_ahb_clk = {
- .halt_reg = 0x1300c,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x45004,
- .enable_mask = BIT(7),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_boot_rom_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_cci_ahb_clk = {
- .halt_reg = 0x5101c,
- .clkr = {
- .enable_reg = 0x5101c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_cci_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &camss_ahb_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_cci_clk = {
- .halt_reg = 0x51018,
- .clkr = {
- .enable_reg = 0x51018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_cci_clk",
- .parent_hws = (const struct clk_hw*[]){
- &cci_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi0_ahb_clk = {
- .halt_reg = 0x4e040,
- .clkr = {
- .enable_reg = 0x4e040,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi0_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &camss_ahb_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi0_clk = {
- .halt_reg = 0x4e03c,
- .clkr = {
- .enable_reg = 0x4e03c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi0_clk",
- .parent_hws = (const struct clk_hw*[]){
- &csi0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi0phy_clk = {
- .halt_reg = 0x4e048,
- .clkr = {
- .enable_reg = 0x4e048,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi0phy_clk",
- .parent_hws = (const struct clk_hw*[]){
- &csi0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi0pix_clk = {
- .halt_reg = 0x4e058,
- .clkr = {
- .enable_reg = 0x4e058,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi0pix_clk",
- .parent_hws = (const struct clk_hw*[]){
- &csi0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi0rdi_clk = {
- .halt_reg = 0x4e050,
- .clkr = {
- .enable_reg = 0x4e050,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi0rdi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &csi0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi1_ahb_clk = {
- .halt_reg = 0x4f040,
- .clkr = {
- .enable_reg = 0x4f040,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi1_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &camss_ahb_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi1_clk = {
- .halt_reg = 0x4f03c,
- .clkr = {
- .enable_reg = 0x4f03c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi1_clk",
- .parent_hws = (const struct clk_hw*[]){
- &csi1_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi1phy_clk = {
- .halt_reg = 0x4f048,
- .clkr = {
- .enable_reg = 0x4f048,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi1phy_clk",
- .parent_hws = (const struct clk_hw*[]){
- &csi1_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi1pix_clk = {
- .halt_reg = 0x4f058,
- .clkr = {
- .enable_reg = 0x4f058,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi1pix_clk",
- .parent_hws = (const struct clk_hw*[]){
- &csi1_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi1rdi_clk = {
- .halt_reg = 0x4f050,
- .clkr = {
- .enable_reg = 0x4f050,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi1rdi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &csi1_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi_vfe0_clk = {
- .halt_reg = 0x58050,
- .clkr = {
- .enable_reg = 0x58050,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi_vfe0_clk",
- .parent_hws = (const struct clk_hw*[]){
- &vfe0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_gp0_clk = {
- .halt_reg = 0x54018,
- .clkr = {
- .enable_reg = 0x54018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_gp0_clk",
- .parent_hws = (const struct clk_hw*[]){
- &camss_gp0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_gp1_clk = {
- .halt_reg = 0x55018,
- .clkr = {
- .enable_reg = 0x55018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_gp1_clk",
- .parent_hws = (const struct clk_hw*[]){
- &camss_gp1_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_ispif_ahb_clk = {
- .halt_reg = 0x50004,
- .clkr = {
- .enable_reg = 0x50004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_ispif_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &camss_ahb_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_jpeg0_clk = {
- .halt_reg = 0x57020,
- .clkr = {
- .enable_reg = 0x57020,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_jpeg0_clk",
- .parent_hws = (const struct clk_hw*[]){
- &jpeg0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_jpeg_ahb_clk = {
- .halt_reg = 0x57024,
- .clkr = {
- .enable_reg = 0x57024,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_jpeg_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &camss_ahb_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_jpeg_axi_clk = {
- .halt_reg = 0x57028,
- .clkr = {
- .enable_reg = 0x57028,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_jpeg_axi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &system_mm_noc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_mclk0_clk = {
- .halt_reg = 0x52018,
- .clkr = {
- .enable_reg = 0x52018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_mclk0_clk",
- .parent_hws = (const struct clk_hw*[]){
- &mclk0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_mclk1_clk = {
- .halt_reg = 0x53018,
- .clkr = {
- .enable_reg = 0x53018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_mclk1_clk",
- .parent_hws = (const struct clk_hw*[]){
- &mclk1_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_micro_ahb_clk = {
- .halt_reg = 0x5600c,
- .clkr = {
- .enable_reg = 0x5600c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_micro_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &camss_ahb_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi0phytimer_clk = {
- .halt_reg = 0x4e01c,
- .clkr = {
- .enable_reg = 0x4e01c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi0phytimer_clk",
- .parent_hws = (const struct clk_hw*[]){
- &csi0phytimer_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_csi1phytimer_clk = {
- .halt_reg = 0x4f01c,
- .clkr = {
- .enable_reg = 0x4f01c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_csi1phytimer_clk",
- .parent_hws = (const struct clk_hw*[]){
- &csi1phytimer_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_ahb_clk = {
- .halt_reg = 0x5a014,
- .clkr = {
- .enable_reg = 0x5a014,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &camss_ahb_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_top_ahb_clk = {
- .halt_reg = 0x56004,
- .clkr = {
- .enable_reg = 0x56004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_top_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_cpp_ahb_clk = {
- .halt_reg = 0x58040,
- .clkr = {
- .enable_reg = 0x58040,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_cpp_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &camss_ahb_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_cpp_clk = {
- .halt_reg = 0x5803c,
- .clkr = {
- .enable_reg = 0x5803c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_cpp_clk",
- .parent_hws = (const struct clk_hw*[]){
- &cpp_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_vfe0_clk = {
- .halt_reg = 0x58038,
- .clkr = {
- .enable_reg = 0x58038,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_vfe0_clk",
- .parent_hws = (const struct clk_hw*[]){
- &vfe0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_vfe_ahb_clk = {
- .halt_reg = 0x58044,
- .clkr = {
- .enable_reg = 0x58044,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_vfe_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &camss_ahb_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_camss_vfe_axi_clk = {
- .halt_reg = 0x58048,
- .clkr = {
- .enable_reg = 0x58048,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_camss_vfe_axi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &system_mm_noc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_crypto_ahb_clk = {
- .halt_reg = 0x16024,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x45004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_crypto_axi_clk = {
- .halt_reg = 0x16020,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x45004,
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_axi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_crypto_clk = {
- .halt_reg = 0x1601c,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x45004,
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_clk",
- .parent_hws = (const struct clk_hw*[]){
- &crypto_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_oxili_gmem_clk = {
- .halt_reg = 0x59024,
- .clkr = {
- .enable_reg = 0x59024,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_oxili_gmem_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gfx3d_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_gp1_clk = {
- .halt_reg = 0x08000,
- .clkr = {
- .enable_reg = 0x08000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp1_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gp1_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_gp2_clk = {
- .halt_reg = 0x09000,
- .clkr = {
- .enable_reg = 0x09000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp2_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gp2_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_gp3_clk = {
- .halt_reg = 0x0a000,
- .clkr = {
- .enable_reg = 0x0a000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp3_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gp3_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mdss_ahb_clk = {
- .halt_reg = 0x4d07c,
- .clkr = {
- .enable_reg = 0x4d07c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdss_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mdss_axi_clk = {
- .halt_reg = 0x4d080,
- .clkr = {
- .enable_reg = 0x4d080,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdss_axi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &system_mm_noc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mdss_byte0_clk = {
- .halt_reg = 0x4d094,
- .clkr = {
- .enable_reg = 0x4d094,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdss_byte0_clk",
- .parent_hws = (const struct clk_hw*[]){
- &byte0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mdss_byte1_clk = {
- .halt_reg = 0x4d0a0,
- .clkr = {
- .enable_reg = 0x4d0a0,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdss_byte1_clk",
- .parent_hws = (const struct clk_hw*[]){
- &byte1_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mdss_esc0_clk = {
- .halt_reg = 0x4d098,
- .clkr = {
- .enable_reg = 0x4d098,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdss_esc0_clk",
- .parent_hws = (const struct clk_hw*[]){
- &esc0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mdss_esc1_clk = {
- .halt_reg = 0x4d09c,
- .clkr = {
- .enable_reg = 0x4d09c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdss_esc1_clk",
- .parent_hws = (const struct clk_hw*[]){
- &esc1_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mdss_mdp_clk = {
- .halt_reg = 0x4D088,
- .clkr = {
- .enable_reg = 0x4D088,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdss_mdp_clk",
- .parent_hws = (const struct clk_hw*[]){
- &mdp_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mdss_pclk0_clk = {
- .halt_reg = 0x4d084,
- .clkr = {
- .enable_reg = 0x4d084,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdss_pclk0_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pclk0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mdss_pclk1_clk = {
- .halt_reg = 0x4d0a4,
- .clkr = {
- .enable_reg = 0x4d0a4,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdss_pclk1_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pclk1_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mdss_vsync_clk = {
- .halt_reg = 0x4d090,
- .clkr = {
- .enable_reg = 0x4d090,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdss_vsync_clk",
- .parent_hws = (const struct clk_hw*[]){
- &vsync_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mss_cfg_ahb_clk = {
- .halt_reg = 0x49000,
- .clkr = {
- .enable_reg = 0x49000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_cfg_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
- .halt_reg = 0x49004,
- .clkr = {
- .enable_reg = 0x49004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_q6_bimc_axi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &bimc_ddr_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_oxili_ahb_clk = {
- .halt_reg = 0x59028,
- .clkr = {
- .enable_reg = 0x59028,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_oxili_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_oxili_gfx3d_clk = {
- .halt_reg = 0x59020,
- .clkr = {
- .enable_reg = 0x59020,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_oxili_gfx3d_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gfx3d_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pdm2_clk = {
- .halt_reg = 0x4400c,
- .clkr = {
- .enable_reg = 0x4400c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm2_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pdm2_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_pdm_ahb_clk = {
- .halt_reg = 0x44004,
- .clkr = {
- .enable_reg = 0x44004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pdm_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_prng_ahb_clk = {
- .halt_reg = 0x13004,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x45004,
- .enable_mask = BIT(8),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_prng_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc1_ahb_clk = {
- .halt_reg = 0x4201c,
- .clkr = {
- .enable_reg = 0x4201c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc1_apps_clk = {
- .halt_reg = 0x42018,
- .clkr = {
- .enable_reg = 0x42018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &sdcc1_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc2_ahb_clk = {
- .halt_reg = 0x4301c,
- .clkr = {
- .enable_reg = 0x4301c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_sdcc2_apps_clk = {
- .halt_reg = 0x43018,
- .clkr = {
- .enable_reg = 0x43018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_apps_clk",
- .parent_hws = (const struct clk_hw*[]){
- &sdcc2_apps_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_apss_tcu_clk = {
- .halt_reg = 0x12018,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x4500c,
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_apss_tcu_clk",
- .parent_hws = (const struct clk_hw*[]){
- &bimc_ddr_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_gfx_tcu_clk = {
- .halt_reg = 0x12020,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x4500c,
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gfx_tcu_clk",
- .parent_hws = (const struct clk_hw*[]){
- &bimc_ddr_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_gfx_tbu_clk = {
- .halt_reg = 0x12010,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x4500c,
- .enable_mask = BIT(3),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gfx_tbu_clk",
- .parent_hws = (const struct clk_hw*[]){
- &bimc_ddr_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mdp_tbu_clk = {
- .halt_reg = 0x1201c,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x4500c,
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdp_tbu_clk",
- .parent_hws = (const struct clk_hw*[]){
- &system_mm_noc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_venus_tbu_clk = {
- .halt_reg = 0x12014,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x4500c,
- .enable_mask = BIT(5),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_venus_tbu_clk",
- .parent_hws = (const struct clk_hw*[]){
- &system_mm_noc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_vfe_tbu_clk = {
- .halt_reg = 0x1203c,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x4500c,
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_vfe_tbu_clk",
- .parent_hws = (const struct clk_hw*[]){
- &system_mm_noc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_jpeg_tbu_clk = {
- .halt_reg = 0x12034,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x4500c,
- .enable_mask = BIT(10),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_jpeg_tbu_clk",
- .parent_hws = (const struct clk_hw*[]){
- &system_mm_noc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_smmu_cfg_clk = {
- .halt_reg = 0x12038,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x4500c,
- .enable_mask = BIT(12),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_smmu_cfg_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_gtcu_ahb_clk = {
- .halt_reg = 0x12044,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x4500c,
- .enable_mask = BIT(13),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gtcu_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_cpp_tbu_clk = {
- .halt_reg = 0x12040,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x4500c,
- .enable_mask = BIT(14),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_cpp_tbu_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_mdp_rt_tbu_clk = {
- .halt_reg = 0x1201c,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x4500c,
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdp_rt_tbu_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_bimc_gfx_clk = {
- .halt_reg = 0x31024,
- .clkr = {
- .enable_reg = 0x31024,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_bimc_gfx_clk",
- .parent_hws = (const struct clk_hw*[]){
- &bimc_gpu_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_bimc_gpu_clk = {
- .halt_reg = 0x31040,
- .clkr = {
- .enable_reg = 0x31040,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_bimc_gpu_clk",
- .parent_hws = (const struct clk_hw*[]){
- &bimc_gpu_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb2a_phy_sleep_clk = {
- .halt_reg = 0x4102c,
- .clkr = {
- .enable_reg = 0x4102c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb2a_phy_sleep_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb_fs_ahb_clk = {
- .halt_reg = 0x3f008,
- .clkr = {
- .enable_reg = 0x3f008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_fs_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb_fs_ic_clk = {
- .halt_reg = 0x3f030,
- .clkr = {
- .enable_reg = 0x3f030,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_fs_ic_clk",
- .parent_hws = (const struct clk_hw*[]){
- &usb_fs_ic_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb_fs_system_clk = {
- .halt_reg = 0x3f004,
- .clkr = {
- .enable_reg = 0x3f004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_fs_system_clk",
- .parent_hws = (const struct clk_hw*[]){
- &usb_fs_system_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb_hs_ahb_clk = {
- .halt_reg = 0x41008,
- .clkr = {
- .enable_reg = 0x41008,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_hs_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_usb_hs_system_clk = {
- .halt_reg = 0x41004,
- .clkr = {
- .enable_reg = 0x41004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb_hs_system_clk",
- .parent_hws = (const struct clk_hw*[]){
- &usb_hs_system_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_venus0_ahb_clk = {
- .halt_reg = 0x4c020,
- .clkr = {
- .enable_reg = 0x4c020,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_venus0_ahb_clk",
- .parent_hws = (const struct clk_hw*[]){
- &pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_venus0_axi_clk = {
- .halt_reg = 0x4c024,
- .clkr = {
- .enable_reg = 0x4c024,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_venus0_axi_clk",
- .parent_hws = (const struct clk_hw*[]){
- &system_mm_noc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_venus0_vcodec0_clk = {
- .halt_reg = 0x4c01c,
- .clkr = {
- .enable_reg = 0x4c01c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_venus0_vcodec0_clk",
- .parent_hws = (const struct clk_hw*[]){
- &vcodec0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
- .halt_reg = 0x4c02c,
- .clkr = {
- .enable_reg = 0x4c02c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_venus0_core0_vcodec0_clk",
- .parent_hws = (const struct clk_hw*[]){
- &vcodec0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
- .halt_reg = 0x4c034,
- .clkr = {
- .enable_reg = 0x4c034,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_venus0_core1_vcodec0_clk",
- .parent_hws = (const struct clk_hw*[]){
- &vcodec0_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct clk_branch gcc_oxili_timer_clk = {
- .halt_reg = 0x59040,
- .clkr = {
- .enable_reg = 0x59040,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_oxili_timer_clk",
- .ops = &clk_branch2_ops,
- },
- },
- };
- static struct gdsc venus_gdsc = {
- .gdscr = 0x4c018,
- .pd = {
- .name = "venus",
- },
- .pwrsts = PWRSTS_OFF_ON,
- };
- static struct gdsc mdss_gdsc = {
- .gdscr = 0x4d078,
- .pd = {
- .name = "mdss",
- },
- .pwrsts = PWRSTS_OFF_ON,
- };
- static struct gdsc jpeg_gdsc = {
- .gdscr = 0x5701c,
- .pd = {
- .name = "jpeg",
- },
- .pwrsts = PWRSTS_OFF_ON,
- };
- static struct gdsc vfe_gdsc = {
- .gdscr = 0x58034,
- .pd = {
- .name = "vfe",
- },
- .pwrsts = PWRSTS_OFF_ON,
- };
- static struct gdsc oxili_gdsc = {
- .gdscr = 0x5901c,
- .pd = {
- .name = "oxili",
- },
- .pwrsts = PWRSTS_OFF_ON,
- };
- static struct gdsc venus_core0_gdsc = {
- .gdscr = 0x4c028,
- .pd = {
- .name = "venus_core0",
- },
- .pwrsts = PWRSTS_OFF_ON,
- };
- static struct gdsc venus_core1_gdsc = {
- .gdscr = 0x4c030,
- .pd = {
- .name = "venus_core1",
- },
- .pwrsts = PWRSTS_OFF_ON,
- };
- static struct clk_regmap *gcc_msm8939_clocks[] = {
- [GPLL0] = &gpll0.clkr,
- [GPLL0_VOTE] = &gpll0_vote,
- [BIMC_PLL] = &bimc_pll.clkr,
- [BIMC_PLL_VOTE] = &bimc_pll_vote,
- [GPLL1] = &gpll1.clkr,
- [GPLL1_VOTE] = &gpll1_vote,
- [GPLL2] = &gpll2.clkr,
- [GPLL2_VOTE] = &gpll2_vote,
- [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
- [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
- [SYSTEM_MM_NOC_BFDCD_CLK_SRC] = &system_mm_noc_bfdcd_clk_src.clkr,
- [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
- [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
- [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
- [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
- [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
- [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
- [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
- [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
- [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
- [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
- [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
- [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
- [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
- [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
- [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
- [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
- [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
- [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
- [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
- [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
- [CCI_CLK_SRC] = &cci_clk_src.clkr,
- [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
- [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
- [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
- [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
- [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
- [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
- [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
- [CPP_CLK_SRC] = &cpp_clk_src.clkr,
- [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
- [GP1_CLK_SRC] = &gp1_clk_src.clkr,
- [GP2_CLK_SRC] = &gp2_clk_src.clkr,
- [GP3_CLK_SRC] = &gp3_clk_src.clkr,
- [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
- [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
- [MDP_CLK_SRC] = &mdp_clk_src.clkr,
- [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
- [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
- [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
- [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
- [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
- [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
- [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
- [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
- [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
- [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
- [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
- [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
- [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
- [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
- [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
- [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
- [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
- [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
- [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
- [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
- [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
- [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
- [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
- [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
- [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
- [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
- [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
- [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
- [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
- [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
- [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
- [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
- [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
- [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
- [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
- [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
- [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
- [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
- [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
- [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
- [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
- [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
- [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
- [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
- [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
- [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
- [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
- [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
- [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
- [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
- [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
- [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
- [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
- [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
- [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
- [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
- [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
- [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
- [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
- [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
- [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
- [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
- [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
- [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
- [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
- [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
- [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
- [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
- [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
- [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
- [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
- [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
- [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
- [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
- [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
- [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
- [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
- [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
- [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
- [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
- [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
- [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
- [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
- [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
- [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
- [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
- [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
- [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
- [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
- [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
- [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
- [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
- [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
- [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
- [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
- [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
- [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
- [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
- [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
- [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
- [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
- [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
- [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
- [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
- [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
- [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
- [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
- [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
- [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
- [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
- [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
- [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
- [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
- [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
- [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
- [GPLL3] = &gpll3.clkr,
- [GPLL3_VOTE] = &gpll3_vote,
- [GPLL4] = &gpll4.clkr,
- [GPLL4_VOTE] = &gpll4_vote,
- [GPLL5] = &gpll5.clkr,
- [GPLL5_VOTE] = &gpll5_vote,
- [GPLL6] = &gpll6.clkr,
- [GPLL6_VOTE] = &gpll6_vote,
- [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
- [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
- [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
- [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
- [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
- [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
- [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
- [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
- [GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,
- [USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,
- [USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,
- [GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,
- [GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,
- [GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,
- [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
- [GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,
- [GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
- };
- static struct gdsc *gcc_msm8939_gdscs[] = {
- [VENUS_GDSC] = &venus_gdsc,
- [MDSS_GDSC] = &mdss_gdsc,
- [JPEG_GDSC] = &jpeg_gdsc,
- [VFE_GDSC] = &vfe_gdsc,
- [OXILI_GDSC] = &oxili_gdsc,
- [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
- [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
- };
- static const struct qcom_reset_map gcc_msm8939_resets[] = {
- [GCC_BLSP1_BCR] = { 0x01000 },
- [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
- [GCC_BLSP1_UART1_BCR] = { 0x02038 },
- [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
- [GCC_BLSP1_UART2_BCR] = { 0x03028 },
- [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
- [GCC_BLSP1_UART3_BCR] = { 0x04038 },
- [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
- [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
- [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
- [GCC_IMEM_BCR] = { 0x0e000 },
- [GCC_SMMU_BCR] = { 0x12000 },
- [GCC_APSS_TCU_BCR] = { 0x12050 },
- [GCC_SMMU_XPU_BCR] = { 0x12054 },
- [GCC_PCNOC_TBU_BCR] = { 0x12058 },
- [GCC_PRNG_BCR] = { 0x13000 },
- [GCC_BOOT_ROM_BCR] = { 0x13008 },
- [GCC_CRYPTO_BCR] = { 0x16000 },
- [GCC_SEC_CTRL_BCR] = { 0x1a000 },
- [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
- [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
- [GCC_DEHR_BCR] = { 0x1f000 },
- [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
- [GCC_PCNOC_BCR] = { 0x27018 },
- [GCC_TCSR_BCR] = { 0x28000 },
- [GCC_QDSS_BCR] = { 0x29000 },
- [GCC_DCD_BCR] = { 0x2a000 },
- [GCC_MSG_RAM_BCR] = { 0x2b000 },
- [GCC_MPM_BCR] = { 0x2c000 },
- [GCC_SPMI_BCR] = { 0x2e000 },
- [GCC_SPDM_BCR] = { 0x2f000 },
- [GCC_MM_SPDM_BCR] = { 0x2f024 },
- [GCC_BIMC_BCR] = { 0x31000 },
- [GCC_RBCPR_BCR] = { 0x33000 },
- [GCC_TLMM_BCR] = { 0x34000 },
- [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
- [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
- [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
- [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
- [GCC_USB_FS_BCR] = { 0x3f000 },
- [GCC_USB_HS_BCR] = { 0x41000 },
- [GCC_USB2A_PHY_BCR] = { 0x41028 },
- [GCC_SDCC1_BCR] = { 0x42000 },
- [GCC_SDCC2_BCR] = { 0x43000 },
- [GCC_PDM_BCR] = { 0x44000 },
- [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
- [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
- [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
- [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
- [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
- [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
- [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
- [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
- [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
- [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
- [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
- [GCC_MMSS_BCR] = { 0x4b000 },
- [GCC_VENUS0_BCR] = { 0x4c014 },
- [GCC_MDSS_BCR] = { 0x4d074 },
- [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
- [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
- [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
- [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
- [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
- [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
- [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
- [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
- [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
- [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
- [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
- [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
- [GCC_CAMSS_CCI_BCR] = { 0x51014 },
- [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
- [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
- [GCC_CAMSS_GP0_BCR] = { 0x54014 },
- [GCC_CAMSS_GP1_BCR] = { 0x55014 },
- [GCC_CAMSS_TOP_BCR] = { 0x56000 },
- [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
- [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
- [GCC_CAMSS_VFE_BCR] = { 0x58030 },
- [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
- [GCC_OXILI_BCR] = { 0x59018 },
- [GCC_GMEM_BCR] = { 0x5902c },
- [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
- [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
- [GCC_MDP_TBU_BCR] = { 0x62000 },
- [GCC_GFX_TBU_BCR] = { 0x63000 },
- [GCC_GFX_TCU_BCR] = { 0x64000 },
- [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
- [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
- [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
- [GCC_GTCU_AHB_BCR] = { 0x68000 },
- [GCC_SMMU_CFG_BCR] = { 0x69000 },
- [GCC_VFE_TBU_BCR] = { 0x6a000 },
- [GCC_VENUS_TBU_BCR] = { 0x6b000 },
- [GCC_JPEG_TBU_BCR] = { 0x6c000 },
- [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
- [GCC_CPP_TBU_BCR] = { 0x6e000 },
- [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
- [GCC_SMMU_CATS_BCR] = { 0x7c000 },
- };
- static const struct regmap_config gcc_msm8939_regmap_config = {
- .reg_bits = 32,
- .reg_stride = 4,
- .val_bits = 32,
- .max_register = 0x80000,
- .fast_io = true,
- };
- static const struct qcom_cc_desc gcc_msm8939_desc = {
- .config = &gcc_msm8939_regmap_config,
- .clks = gcc_msm8939_clocks,
- .num_clks = ARRAY_SIZE(gcc_msm8939_clocks),
- .resets = gcc_msm8939_resets,
- .num_resets = ARRAY_SIZE(gcc_msm8939_resets),
- .gdscs = gcc_msm8939_gdscs,
- .num_gdscs = ARRAY_SIZE(gcc_msm8939_gdscs),
- };
- static const struct of_device_id gcc_msm8939_match_table[] = {
- { .compatible = "qcom,gcc-msm8939" },
- { }
- };
- MODULE_DEVICE_TABLE(of, gcc_msm8939_match_table);
- static int gcc_msm8939_probe(struct platform_device *pdev)
- {
- struct regmap *regmap;
- regmap = qcom_cc_map(pdev, &gcc_msm8939_desc);
- if (IS_ERR(regmap))
- return PTR_ERR(regmap);
- clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
- clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
- return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap);
- }
- static struct platform_driver gcc_msm8939_driver = {
- .probe = gcc_msm8939_probe,
- .driver = {
- .name = "gcc-msm8939",
- .of_match_table = gcc_msm8939_match_table,
- },
- };
- static int __init gcc_msm8939_init(void)
- {
- return platform_driver_register(&gcc_msm8939_driver);
- }
- core_initcall(gcc_msm8939_init);
- static void __exit gcc_msm8939_exit(void)
- {
- platform_driver_unregister(&gcc_msm8939_driver);
- }
- module_exit(gcc_msm8939_exit);
- MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver");
- MODULE_LICENSE("GPL v2");
|