gcc-msm8939.c 101 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2020 Linaro Limited
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/bitops.h>
  7. #include <linux/err.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/regmap.h>
  14. #include <linux/reset-controller.h>
  15. #include <dt-bindings/clock/qcom,gcc-msm8939.h>
  16. #include <dt-bindings/reset/qcom,gcc-msm8939.h>
  17. #include "common.h"
  18. #include "clk-regmap.h"
  19. #include "clk-pll.h"
  20. #include "clk-rcg.h"
  21. #include "clk-branch.h"
  22. #include "reset.h"
  23. #include "gdsc.h"
  24. enum {
  25. P_XO,
  26. P_GPLL0,
  27. P_GPLL0_AUX,
  28. P_BIMC,
  29. P_GPLL1,
  30. P_GPLL1_AUX,
  31. P_GPLL2,
  32. P_GPLL2_AUX,
  33. P_GPLL3,
  34. P_GPLL3_AUX,
  35. P_GPLL4,
  36. P_GPLL5,
  37. P_GPLL5_AUX,
  38. P_GPLL5_EARLY,
  39. P_GPLL6,
  40. P_GPLL6_AUX,
  41. P_SLEEP_CLK,
  42. P_DSI0_PHYPLL_BYTE,
  43. P_DSI0_PHYPLL_DSI,
  44. P_EXT_PRI_I2S,
  45. P_EXT_SEC_I2S,
  46. P_EXT_MCLK,
  47. };
  48. static struct clk_pll gpll0 = {
  49. .l_reg = 0x21004,
  50. .m_reg = 0x21008,
  51. .n_reg = 0x2100c,
  52. .config_reg = 0x21010,
  53. .mode_reg = 0x21000,
  54. .status_reg = 0x2101c,
  55. .status_bit = 17,
  56. .clkr.hw.init = &(struct clk_init_data){
  57. .name = "gpll0",
  58. .parent_data = &(const struct clk_parent_data) {
  59. .fw_name = "xo",
  60. },
  61. .num_parents = 1,
  62. .ops = &clk_pll_ops,
  63. },
  64. };
  65. static struct clk_regmap gpll0_vote = {
  66. .enable_reg = 0x45000,
  67. .enable_mask = BIT(0),
  68. .hw.init = &(struct clk_init_data){
  69. .name = "gpll0_vote",
  70. .parent_data = &(const struct clk_parent_data) {
  71. .hw = &gpll0.clkr.hw,
  72. },
  73. .num_parents = 1,
  74. .ops = &clk_pll_vote_ops,
  75. },
  76. };
  77. static struct clk_pll gpll1 = {
  78. .l_reg = 0x20004,
  79. .m_reg = 0x20008,
  80. .n_reg = 0x2000c,
  81. .config_reg = 0x20010,
  82. .mode_reg = 0x20000,
  83. .status_reg = 0x2001c,
  84. .status_bit = 17,
  85. .clkr.hw.init = &(struct clk_init_data){
  86. .name = "gpll1",
  87. .parent_data = &(const struct clk_parent_data) {
  88. .fw_name = "xo",
  89. },
  90. .num_parents = 1,
  91. .ops = &clk_pll_ops,
  92. },
  93. };
  94. static struct clk_regmap gpll1_vote = {
  95. .enable_reg = 0x45000,
  96. .enable_mask = BIT(1),
  97. .hw.init = &(struct clk_init_data){
  98. .name = "gpll1_vote",
  99. .parent_data = &(const struct clk_parent_data) {
  100. .hw = &gpll1.clkr.hw,
  101. },
  102. .num_parents = 1,
  103. .ops = &clk_pll_vote_ops,
  104. },
  105. };
  106. static struct clk_pll gpll2 = {
  107. .l_reg = 0x4a004,
  108. .m_reg = 0x4a008,
  109. .n_reg = 0x4a00c,
  110. .config_reg = 0x4a010,
  111. .mode_reg = 0x4a000,
  112. .status_reg = 0x4a01c,
  113. .status_bit = 17,
  114. .clkr.hw.init = &(struct clk_init_data){
  115. .name = "gpll2",
  116. .parent_data = &(const struct clk_parent_data) {
  117. .fw_name = "xo",
  118. },
  119. .num_parents = 1,
  120. .ops = &clk_pll_ops,
  121. },
  122. };
  123. static struct clk_regmap gpll2_vote = {
  124. .enable_reg = 0x45000,
  125. .enable_mask = BIT(2),
  126. .hw.init = &(struct clk_init_data){
  127. .name = "gpll2_vote",
  128. .parent_data = &(const struct clk_parent_data) {
  129. .hw = &gpll2.clkr.hw,
  130. },
  131. .num_parents = 1,
  132. .ops = &clk_pll_vote_ops,
  133. },
  134. };
  135. static struct clk_pll bimc_pll = {
  136. .l_reg = 0x23004,
  137. .m_reg = 0x23008,
  138. .n_reg = 0x2300c,
  139. .config_reg = 0x23010,
  140. .mode_reg = 0x23000,
  141. .status_reg = 0x2301c,
  142. .status_bit = 17,
  143. .clkr.hw.init = &(struct clk_init_data){
  144. .name = "bimc_pll",
  145. .parent_data = &(const struct clk_parent_data) {
  146. .fw_name = "xo",
  147. },
  148. .num_parents = 1,
  149. .ops = &clk_pll_ops,
  150. },
  151. };
  152. static struct clk_regmap bimc_pll_vote = {
  153. .enable_reg = 0x45000,
  154. .enable_mask = BIT(3),
  155. .hw.init = &(struct clk_init_data){
  156. .name = "bimc_pll_vote",
  157. .parent_data = &(const struct clk_parent_data) {
  158. .hw = &bimc_pll.clkr.hw,
  159. },
  160. .num_parents = 1,
  161. .ops = &clk_pll_vote_ops,
  162. },
  163. };
  164. static struct clk_pll gpll3 = {
  165. .l_reg = 0x22004,
  166. .m_reg = 0x22008,
  167. .n_reg = 0x2200c,
  168. .config_reg = 0x22010,
  169. .mode_reg = 0x22000,
  170. .status_reg = 0x2201c,
  171. .status_bit = 17,
  172. .clkr.hw.init = &(struct clk_init_data){
  173. .name = "gpll3",
  174. .parent_data = &(const struct clk_parent_data) {
  175. .fw_name = "xo",
  176. },
  177. .num_parents = 1,
  178. .ops = &clk_pll_ops,
  179. },
  180. };
  181. static struct clk_regmap gpll3_vote = {
  182. .enable_reg = 0x45000,
  183. .enable_mask = BIT(4),
  184. .hw.init = &(struct clk_init_data){
  185. .name = "gpll3_vote",
  186. .parent_data = &(const struct clk_parent_data) {
  187. .hw = &gpll3.clkr.hw,
  188. },
  189. .num_parents = 1,
  190. .ops = &clk_pll_vote_ops,
  191. },
  192. };
  193. /* GPLL3 at 1100 MHz, main output enabled. */
  194. static const struct pll_config gpll3_config = {
  195. .l = 57,
  196. .m = 7,
  197. .n = 24,
  198. .vco_val = 0x0,
  199. .vco_mask = BIT(20),
  200. .pre_div_val = 0x0,
  201. .pre_div_mask = BIT(12),
  202. .post_div_val = 0x0,
  203. .post_div_mask = BIT(9) | BIT(8),
  204. .mn_ena_mask = BIT(24),
  205. .main_output_mask = BIT(0),
  206. .aux_output_mask = BIT(1),
  207. };
  208. static struct clk_pll gpll4 = {
  209. .l_reg = 0x24004,
  210. .m_reg = 0x24008,
  211. .n_reg = 0x2400c,
  212. .config_reg = 0x24010,
  213. .mode_reg = 0x24000,
  214. .status_reg = 0x2401c,
  215. .status_bit = 17,
  216. .clkr.hw.init = &(struct clk_init_data){
  217. .name = "gpll4",
  218. .parent_data = &(const struct clk_parent_data) {
  219. .fw_name = "xo",
  220. },
  221. .num_parents = 1,
  222. .ops = &clk_pll_ops,
  223. },
  224. };
  225. static struct clk_regmap gpll4_vote = {
  226. .enable_reg = 0x45000,
  227. .enable_mask = BIT(5),
  228. .hw.init = &(struct clk_init_data){
  229. .name = "gpll4_vote",
  230. .parent_data = &(const struct clk_parent_data) {
  231. .hw = &gpll4.clkr.hw,
  232. },
  233. .num_parents = 1,
  234. .ops = &clk_pll_vote_ops,
  235. },
  236. };
  237. /* GPLL4 at 1200 MHz, main output enabled. */
  238. static struct pll_config gpll4_config = {
  239. .l = 62,
  240. .m = 1,
  241. .n = 2,
  242. .vco_val = 0x0,
  243. .vco_mask = BIT(20),
  244. .pre_div_val = 0x0,
  245. .pre_div_mask = BIT(12),
  246. .post_div_val = 0x0,
  247. .post_div_mask = BIT(9) | BIT(8),
  248. .mn_ena_mask = BIT(24),
  249. .main_output_mask = BIT(0),
  250. };
  251. static struct clk_pll gpll5 = {
  252. .l_reg = 0x25004,
  253. .m_reg = 0x25008,
  254. .n_reg = 0x2500c,
  255. .config_reg = 0x25010,
  256. .mode_reg = 0x25000,
  257. .status_reg = 0x2501c,
  258. .status_bit = 17,
  259. .clkr.hw.init = &(struct clk_init_data){
  260. .name = "gpll5",
  261. .parent_data = &(const struct clk_parent_data) {
  262. .fw_name = "xo",
  263. },
  264. .num_parents = 1,
  265. .ops = &clk_pll_ops,
  266. },
  267. };
  268. static struct clk_regmap gpll5_vote = {
  269. .enable_reg = 0x45000,
  270. .enable_mask = BIT(6),
  271. .hw.init = &(struct clk_init_data){
  272. .name = "gpll5_vote",
  273. .parent_data = &(const struct clk_parent_data) {
  274. .hw = &gpll5.clkr.hw,
  275. },
  276. .num_parents = 1,
  277. .ops = &clk_pll_vote_ops,
  278. },
  279. };
  280. static struct clk_pll gpll6 = {
  281. .l_reg = 0x37004,
  282. .m_reg = 0x37008,
  283. .n_reg = 0x3700c,
  284. .config_reg = 0x37010,
  285. .mode_reg = 0x37000,
  286. .status_reg = 0x3701c,
  287. .status_bit = 17,
  288. .clkr.hw.init = &(struct clk_init_data){
  289. .name = "gpll6",
  290. .parent_data = &(const struct clk_parent_data) {
  291. .fw_name = "xo",
  292. },
  293. .num_parents = 1,
  294. .ops = &clk_pll_ops,
  295. },
  296. };
  297. static struct clk_regmap gpll6_vote = {
  298. .enable_reg = 0x45000,
  299. .enable_mask = BIT(7),
  300. .hw.init = &(struct clk_init_data){
  301. .name = "gpll6_vote",
  302. .parent_data = &(const struct clk_parent_data) {
  303. .hw = &gpll6.clkr.hw,
  304. },
  305. .num_parents = 1,
  306. .ops = &clk_pll_vote_ops,
  307. },
  308. };
  309. static const struct parent_map gcc_xo_gpll0_map[] = {
  310. { P_XO, 0 },
  311. { P_GPLL0, 1 },
  312. };
  313. static const struct clk_parent_data gcc_xo_gpll0_parent_data[] = {
  314. { .fw_name = "xo" },
  315. { .hw = &gpll0_vote.hw },
  316. };
  317. static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
  318. { P_XO, 0 },
  319. { P_GPLL0, 1 },
  320. { P_BIMC, 2 },
  321. };
  322. static const struct clk_parent_data gcc_xo_gpll0_bimc_parent_data[] = {
  323. { .fw_name = "xo" },
  324. { .hw = &gpll0_vote.hw },
  325. { .hw = &bimc_pll_vote.hw },
  326. };
  327. static const struct parent_map gcc_xo_gpll0_gpll6a_map[] = {
  328. { P_XO, 0 },
  329. { P_GPLL0, 1 },
  330. { P_GPLL6_AUX, 2 },
  331. };
  332. static const struct clk_parent_data gcc_xo_gpll0_gpll6a_parent_data[] = {
  333. { .fw_name = "xo" },
  334. { .hw = &gpll0_vote.hw },
  335. { .hw = &gpll6_vote.hw },
  336. };
  337. static const struct parent_map gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map[] = {
  338. { P_XO, 0 },
  339. { P_GPLL0, 1 },
  340. { P_GPLL2_AUX, 4 },
  341. { P_GPLL3, 2 },
  342. { P_GPLL6_AUX, 3 },
  343. };
  344. static const struct clk_parent_data gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data[] = {
  345. { .fw_name = "xo" },
  346. { .hw = &gpll0_vote.hw },
  347. { .hw = &gpll2_vote.hw },
  348. { .hw = &gpll3_vote.hw },
  349. { .hw = &gpll6_vote.hw },
  350. };
  351. static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
  352. { P_XO, 0 },
  353. { P_GPLL0, 1 },
  354. { P_GPLL2, 2 },
  355. };
  356. static const struct clk_parent_data gcc_xo_gpll0_gpll2_parent_data[] = {
  357. { .fw_name = "xo" },
  358. { .hw = &gpll0_vote.hw },
  359. { .hw = &gpll2_vote.hw },
  360. };
  361. static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
  362. { P_XO, 0 },
  363. { P_GPLL0, 1 },
  364. { P_GPLL2, 3 },
  365. { P_GPLL4, 2 },
  366. };
  367. static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_parent_data[] = {
  368. { .fw_name = "xo" },
  369. { .hw = &gpll0_vote.hw },
  370. { .hw = &gpll2_vote.hw },
  371. { .hw = &gpll4_vote.hw },
  372. };
  373. static const struct parent_map gcc_xo_gpll0a_map[] = {
  374. { P_XO, 0 },
  375. { P_GPLL0_AUX, 2 },
  376. };
  377. static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] = {
  378. { .fw_name = "xo" },
  379. { .hw = &gpll0_vote.hw },
  380. };
  381. static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
  382. { P_XO, 0 },
  383. { P_GPLL0, 1 },
  384. { P_GPLL1_AUX, 2 },
  385. { P_SLEEP_CLK, 6 },
  386. };
  387. static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep_parent_data[] = {
  388. { .fw_name = "xo" },
  389. { .hw = &gpll0_vote.hw },
  390. { .hw = &gpll1_vote.hw },
  391. { .fw_name = "sleep_clk", .name = "sleep_clk" },
  392. };
  393. static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
  394. { P_XO, 0 },
  395. { P_GPLL0, 1 },
  396. { P_GPLL1_AUX, 2 },
  397. { P_GPLL6, 2 },
  398. { P_SLEEP_CLK, 6 },
  399. };
  400. static const struct clk_parent_data gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data[] = {
  401. { .fw_name = "xo" },
  402. { .hw = &gpll0_vote.hw },
  403. { .hw = &gpll1_vote.hw },
  404. { .hw = &gpll6_vote.hw },
  405. { .fw_name = "sleep_clk", .name = "sleep_clk" },
  406. };
  407. static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
  408. { P_XO, 0 },
  409. { P_GPLL0, 1 },
  410. { P_GPLL1_AUX, 2 },
  411. };
  412. static const struct clk_parent_data gcc_xo_gpll0_gpll1a_parent_data[] = {
  413. { .fw_name = "xo" },
  414. { .hw = &gpll0_vote.hw },
  415. { .hw = &gpll1_vote.hw },
  416. };
  417. static const struct parent_map gcc_xo_dsibyte_map[] = {
  418. { P_XO, 0, },
  419. { P_DSI0_PHYPLL_BYTE, 2 },
  420. };
  421. static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] = {
  422. { .fw_name = "xo" },
  423. { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
  424. };
  425. static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
  426. { P_XO, 0 },
  427. { P_GPLL0_AUX, 2 },
  428. { P_DSI0_PHYPLL_BYTE, 1 },
  429. };
  430. static const struct clk_parent_data gcc_xo_gpll0a_dsibyte_parent_data[] = {
  431. { .fw_name = "xo" },
  432. { .hw = &gpll0_vote.hw },
  433. { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
  434. };
  435. static const struct parent_map gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map[] = {
  436. { P_XO, 0 },
  437. { P_GPLL1, 1 },
  438. { P_DSI0_PHYPLL_DSI, 2 },
  439. { P_GPLL6, 3 },
  440. { P_GPLL3_AUX, 4 },
  441. { P_GPLL0_AUX, 5 },
  442. };
  443. static const struct clk_parent_data gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data[] = {
  444. { .fw_name = "xo" },
  445. { .hw = &gpll1_vote.hw },
  446. { .fw_name = "dsi0pll", .name = "dsi0pll" },
  447. { .hw = &gpll6_vote.hw },
  448. { .hw = &gpll3_vote.hw },
  449. { .hw = &gpll0_vote.hw },
  450. };
  451. static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
  452. { P_XO, 0 },
  453. { P_GPLL0_AUX, 2 },
  454. { P_DSI0_PHYPLL_DSI, 1 },
  455. };
  456. static const struct clk_parent_data gcc_xo_gpll0a_dsiphy_parent_data[] = {
  457. { .fw_name = "xo" },
  458. { .hw = &gpll0_vote.hw },
  459. { .fw_name = "dsi0pll", .name = "dsi0pll" },
  460. };
  461. static const struct parent_map gcc_xo_gpll0_gpll5a_gpll6_bimc_map[] = {
  462. { P_XO, 0 },
  463. { P_GPLL0, 1 },
  464. { P_GPLL5_AUX, 3 },
  465. { P_GPLL6, 2 },
  466. { P_BIMC, 4 },
  467. };
  468. static const struct clk_parent_data gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data[] = {
  469. { .fw_name = "xo" },
  470. { .hw = &gpll0_vote.hw },
  471. { .hw = &gpll5_vote.hw },
  472. { .hw = &gpll6_vote.hw },
  473. { .hw = &bimc_pll_vote.hw },
  474. };
  475. static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
  476. { P_XO, 0 },
  477. { P_GPLL0, 1 },
  478. { P_GPLL1, 2 },
  479. { P_SLEEP_CLK, 6 }
  480. };
  481. static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep_parent_data[] = {
  482. { .fw_name = "xo" },
  483. { .hw = &gpll0_vote.hw },
  484. { .hw = &gpll1_vote.hw },
  485. { .fw_name = "sleep_clk", .name = "sleep_clk" },
  486. };
  487. static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
  488. { P_XO, 0 },
  489. { P_GPLL1, 1 },
  490. { P_EXT_PRI_I2S, 2 },
  491. { P_EXT_MCLK, 3 },
  492. { P_SLEEP_CLK, 6 }
  493. };
  494. static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep_parent_data[] = {
  495. { .fw_name = "xo" },
  496. { .hw = &gpll0_vote.hw },
  497. { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
  498. { .fw_name = "ext_mclk", .name = "ext_mclk" },
  499. { .fw_name = "sleep_clk", .name = "sleep_clk" },
  500. };
  501. static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
  502. { P_XO, 0 },
  503. { P_GPLL1, 1 },
  504. { P_EXT_SEC_I2S, 2 },
  505. { P_EXT_MCLK, 3 },
  506. { P_SLEEP_CLK, 6 }
  507. };
  508. static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep_parent_data[] = {
  509. { .fw_name = "xo" },
  510. { .hw = &gpll1_vote.hw },
  511. { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
  512. { .fw_name = "ext_mclk", .name = "ext_mclk" },
  513. { .fw_name = "sleep_clk", .name = "sleep_clk" },
  514. };
  515. static const struct parent_map gcc_xo_sleep_map[] = {
  516. { P_XO, 0 },
  517. { P_SLEEP_CLK, 6 }
  518. };
  519. static const struct clk_parent_data gcc_xo_sleep_parent_data[] = {
  520. { .fw_name = "xo" },
  521. { .fw_name = "sleep_clk", .name = "sleep_clk" },
  522. };
  523. static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
  524. { P_XO, 0 },
  525. { P_GPLL1, 1 },
  526. { P_EXT_MCLK, 2 },
  527. { P_SLEEP_CLK, 6 }
  528. };
  529. static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep_parent_data[] = {
  530. { .fw_name = "xo" },
  531. { .hw = &gpll1_vote.hw },
  532. { .fw_name = "ext_mclk", .name = "ext_mclk" },
  533. { .fw_name = "sleep_clk", .name = "sleep_clk" },
  534. };
  535. static const struct clk_parent_data gcc_xo_gpll6_gpll0_parent_data[] = {
  536. { .fw_name = "xo" },
  537. { .hw = &gpll6_vote.hw },
  538. { .hw = &gpll0_vote.hw },
  539. };
  540. static const struct clk_parent_data gcc_xo_gpll6_gpll0a_parent_data[] = {
  541. { .fw_name = "xo" },
  542. { .hw = &gpll6_vote.hw },
  543. { .hw = &gpll0_vote.hw },
  544. };
  545. static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
  546. .cmd_rcgr = 0x27000,
  547. .hid_width = 5,
  548. .parent_map = gcc_xo_gpll0_map,
  549. .clkr.hw.init = &(struct clk_init_data){
  550. .name = "pcnoc_bfdcd_clk_src",
  551. .parent_data = gcc_xo_gpll0_parent_data,
  552. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  553. .ops = &clk_rcg2_ops,
  554. },
  555. };
  556. static struct clk_rcg2 system_noc_bfdcd_clk_src = {
  557. .cmd_rcgr = 0x26004,
  558. .hid_width = 5,
  559. .parent_map = gcc_xo_gpll0_gpll6a_map,
  560. .clkr.hw.init = &(struct clk_init_data){
  561. .name = "system_noc_bfdcd_clk_src",
  562. .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
  563. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
  564. .ops = &clk_rcg2_ops,
  565. },
  566. };
  567. static struct clk_rcg2 bimc_ddr_clk_src = {
  568. .cmd_rcgr = 0x32024,
  569. .hid_width = 5,
  570. .parent_map = gcc_xo_gpll0_bimc_map,
  571. .clkr.hw.init = &(struct clk_init_data){
  572. .name = "bimc_ddr_clk_src",
  573. .parent_data = gcc_xo_gpll0_bimc_parent_data,
  574. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_parent_data),
  575. .ops = &clk_rcg2_ops,
  576. .flags = CLK_GET_RATE_NOCACHE,
  577. },
  578. };
  579. static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = {
  580. .cmd_rcgr = 0x2600c,
  581. .hid_width = 5,
  582. .parent_map = gcc_xo_gpll0_gpll6a_map,
  583. .clkr.hw.init = &(struct clk_init_data){
  584. .name = "system_mm_noc_bfdcd_clk_src",
  585. .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
  586. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
  587. .ops = &clk_rcg2_ops,
  588. },
  589. };
  590. static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
  591. F(40000000, P_GPLL0, 10, 1, 2),
  592. F(80000000, P_GPLL0, 10, 0, 0),
  593. { }
  594. };
  595. static struct clk_rcg2 camss_ahb_clk_src = {
  596. .cmd_rcgr = 0x5a000,
  597. .mnd_width = 8,
  598. .hid_width = 5,
  599. .parent_map = gcc_xo_gpll0_map,
  600. .freq_tbl = ftbl_gcc_camss_ahb_clk,
  601. .clkr.hw.init = &(struct clk_init_data){
  602. .name = "camss_ahb_clk_src",
  603. .parent_data = gcc_xo_gpll0_parent_data,
  604. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  605. .ops = &clk_rcg2_ops,
  606. },
  607. };
  608. static const struct freq_tbl ftbl_apss_ahb_clk[] = {
  609. F(19200000, P_XO, 1, 0, 0),
  610. F(50000000, P_GPLL0, 16, 0, 0),
  611. F(100000000, P_GPLL0, 8, 0, 0),
  612. F(133330000, P_GPLL0, 6, 0, 0),
  613. { }
  614. };
  615. static struct clk_rcg2 apss_ahb_clk_src = {
  616. .cmd_rcgr = 0x46000,
  617. .hid_width = 5,
  618. .parent_map = gcc_xo_gpll0_map,
  619. .freq_tbl = ftbl_apss_ahb_clk,
  620. .clkr.hw.init = &(struct clk_init_data){
  621. .name = "apss_ahb_clk_src",
  622. .parent_data = gcc_xo_gpll0_parent_data,
  623. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  624. .ops = &clk_rcg2_ops,
  625. },
  626. };
  627. static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
  628. F(100000000, P_GPLL0, 8, 0, 0),
  629. F(200000000, P_GPLL0, 4, 0, 0),
  630. { }
  631. };
  632. static struct clk_rcg2 csi0_clk_src = {
  633. .cmd_rcgr = 0x4e020,
  634. .hid_width = 5,
  635. .parent_map = gcc_xo_gpll0_map,
  636. .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
  637. .clkr.hw.init = &(struct clk_init_data){
  638. .name = "csi0_clk_src",
  639. .parent_data = gcc_xo_gpll0_parent_data,
  640. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  641. .ops = &clk_rcg2_ops,
  642. },
  643. };
  644. static struct clk_rcg2 csi1_clk_src = {
  645. .cmd_rcgr = 0x4f020,
  646. .hid_width = 5,
  647. .parent_map = gcc_xo_gpll0_map,
  648. .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
  649. .clkr.hw.init = &(struct clk_init_data){
  650. .name = "csi1_clk_src",
  651. .parent_data = gcc_xo_gpll0_parent_data,
  652. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  653. .ops = &clk_rcg2_ops,
  654. },
  655. };
  656. static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
  657. F(19200000, P_XO, 1, 0, 0),
  658. F(50000000, P_GPLL0, 16, 0, 0),
  659. F(80000000, P_GPLL0, 10, 0, 0),
  660. F(100000000, P_GPLL0, 8, 0, 0),
  661. F(160000000, P_GPLL0, 5, 0, 0),
  662. F(200000000, P_GPLL0, 4, 0, 0),
  663. F(220000000, P_GPLL3, 5, 0, 0),
  664. F(266670000, P_GPLL0, 3, 0, 0),
  665. F(310000000, P_GPLL2_AUX, 3, 0, 0),
  666. F(400000000, P_GPLL0, 2, 0, 0),
  667. F(465000000, P_GPLL2_AUX, 2, 0, 0),
  668. F(550000000, P_GPLL3, 2, 0, 0),
  669. { }
  670. };
  671. static struct clk_rcg2 gfx3d_clk_src = {
  672. .cmd_rcgr = 0x59000,
  673. .hid_width = 5,
  674. .parent_map = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map,
  675. .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
  676. .clkr.hw.init = &(struct clk_init_data){
  677. .name = "gfx3d_clk_src",
  678. .parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data,
  679. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data),
  680. .ops = &clk_rcg2_ops,
  681. },
  682. };
  683. static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
  684. F(50000000, P_GPLL0, 16, 0, 0),
  685. F(80000000, P_GPLL0, 10, 0, 0),
  686. F(100000000, P_GPLL0, 8, 0, 0),
  687. F(160000000, P_GPLL0, 5, 0, 0),
  688. F(177780000, P_GPLL0, 4.5, 0, 0),
  689. F(200000000, P_GPLL0, 4, 0, 0),
  690. F(266670000, P_GPLL0, 3, 0, 0),
  691. F(320000000, P_GPLL0, 2.5, 0, 0),
  692. F(400000000, P_GPLL0, 2, 0, 0),
  693. F(465000000, P_GPLL2, 2, 0, 0),
  694. F(480000000, P_GPLL4, 2.5, 0, 0),
  695. F(600000000, P_GPLL4, 2, 0, 0),
  696. { }
  697. };
  698. static struct clk_rcg2 vfe0_clk_src = {
  699. .cmd_rcgr = 0x58000,
  700. .hid_width = 5,
  701. .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
  702. .freq_tbl = ftbl_gcc_camss_vfe0_clk,
  703. .clkr.hw.init = &(struct clk_init_data){
  704. .name = "vfe0_clk_src",
  705. .parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data,
  706. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_parent_data),
  707. .ops = &clk_rcg2_ops,
  708. },
  709. };
  710. static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
  711. F(19200000, P_XO, 1, 0, 0),
  712. F(50000000, P_GPLL0, 16, 0, 0),
  713. { }
  714. };
  715. static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
  716. .cmd_rcgr = 0x0200c,
  717. .hid_width = 5,
  718. .parent_map = gcc_xo_gpll0_map,
  719. .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
  720. .clkr.hw.init = &(struct clk_init_data){
  721. .name = "blsp1_qup1_i2c_apps_clk_src",
  722. .parent_data = gcc_xo_gpll0_parent_data,
  723. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  724. .ops = &clk_rcg2_ops,
  725. },
  726. };
  727. static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
  728. F(960000, P_XO, 10, 1, 2),
  729. F(4800000, P_XO, 4, 0, 0),
  730. F(9600000, P_XO, 2, 0, 0),
  731. F(16000000, P_GPLL0, 10, 1, 5),
  732. F(19200000, P_XO, 1, 0, 0),
  733. F(25000000, P_GPLL0, 16, 1, 2),
  734. F(50000000, P_GPLL0, 16, 0, 0),
  735. { }
  736. };
  737. static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
  738. .cmd_rcgr = 0x02024,
  739. .mnd_width = 8,
  740. .hid_width = 5,
  741. .parent_map = gcc_xo_gpll0_map,
  742. .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
  743. .clkr.hw.init = &(struct clk_init_data){
  744. .name = "blsp1_qup1_spi_apps_clk_src",
  745. .parent_data = gcc_xo_gpll0_parent_data,
  746. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  747. .ops = &clk_rcg2_ops,
  748. },
  749. };
  750. static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
  751. .cmd_rcgr = 0x03000,
  752. .hid_width = 5,
  753. .parent_map = gcc_xo_gpll0_map,
  754. .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
  755. .clkr.hw.init = &(struct clk_init_data){
  756. .name = "blsp1_qup2_i2c_apps_clk_src",
  757. .parent_data = gcc_xo_gpll0_parent_data,
  758. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  759. .ops = &clk_rcg2_ops,
  760. },
  761. };
  762. static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
  763. .cmd_rcgr = 0x03014,
  764. .mnd_width = 8,
  765. .hid_width = 5,
  766. .parent_map = gcc_xo_gpll0_map,
  767. .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
  768. .clkr.hw.init = &(struct clk_init_data){
  769. .name = "blsp1_qup2_spi_apps_clk_src",
  770. .parent_data = gcc_xo_gpll0_parent_data,
  771. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  772. .ops = &clk_rcg2_ops,
  773. },
  774. };
  775. static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
  776. .cmd_rcgr = 0x04000,
  777. .hid_width = 5,
  778. .parent_map = gcc_xo_gpll0_map,
  779. .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
  780. .clkr.hw.init = &(struct clk_init_data){
  781. .name = "blsp1_qup3_i2c_apps_clk_src",
  782. .parent_data = gcc_xo_gpll0_parent_data,
  783. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  784. .ops = &clk_rcg2_ops,
  785. },
  786. };
  787. static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
  788. .cmd_rcgr = 0x04024,
  789. .mnd_width = 8,
  790. .hid_width = 5,
  791. .parent_map = gcc_xo_gpll0_map,
  792. .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
  793. .clkr.hw.init = &(struct clk_init_data){
  794. .name = "blsp1_qup3_spi_apps_clk_src",
  795. .parent_data = gcc_xo_gpll0_parent_data,
  796. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  797. .ops = &clk_rcg2_ops,
  798. },
  799. };
  800. static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
  801. .cmd_rcgr = 0x05000,
  802. .hid_width = 5,
  803. .parent_map = gcc_xo_gpll0_map,
  804. .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
  805. .clkr.hw.init = &(struct clk_init_data){
  806. .name = "blsp1_qup4_i2c_apps_clk_src",
  807. .parent_data = gcc_xo_gpll0_parent_data,
  808. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  809. .ops = &clk_rcg2_ops,
  810. },
  811. };
  812. static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
  813. .cmd_rcgr = 0x05024,
  814. .mnd_width = 8,
  815. .hid_width = 5,
  816. .parent_map = gcc_xo_gpll0_map,
  817. .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
  818. .clkr.hw.init = &(struct clk_init_data){
  819. .name = "blsp1_qup4_spi_apps_clk_src",
  820. .parent_data = gcc_xo_gpll0_parent_data,
  821. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  822. .ops = &clk_rcg2_ops,
  823. },
  824. };
  825. static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
  826. .cmd_rcgr = 0x06000,
  827. .hid_width = 5,
  828. .parent_map = gcc_xo_gpll0_map,
  829. .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
  830. .clkr.hw.init = &(struct clk_init_data){
  831. .name = "blsp1_qup5_i2c_apps_clk_src",
  832. .parent_data = gcc_xo_gpll0_parent_data,
  833. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  834. .ops = &clk_rcg2_ops,
  835. },
  836. };
  837. static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
  838. .cmd_rcgr = 0x06024,
  839. .mnd_width = 8,
  840. .hid_width = 5,
  841. .parent_map = gcc_xo_gpll0_map,
  842. .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
  843. .clkr.hw.init = &(struct clk_init_data){
  844. .name = "blsp1_qup5_spi_apps_clk_src",
  845. .parent_data = gcc_xo_gpll0_parent_data,
  846. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  847. .ops = &clk_rcg2_ops,
  848. },
  849. };
  850. static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
  851. .cmd_rcgr = 0x07000,
  852. .hid_width = 5,
  853. .parent_map = gcc_xo_gpll0_map,
  854. .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
  855. .clkr.hw.init = &(struct clk_init_data){
  856. .name = "blsp1_qup6_i2c_apps_clk_src",
  857. .parent_data = gcc_xo_gpll0_parent_data,
  858. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  859. .ops = &clk_rcg2_ops,
  860. },
  861. };
  862. static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
  863. .cmd_rcgr = 0x07024,
  864. .mnd_width = 8,
  865. .hid_width = 5,
  866. .parent_map = gcc_xo_gpll0_map,
  867. .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
  868. .clkr.hw.init = &(struct clk_init_data){
  869. .name = "blsp1_qup6_spi_apps_clk_src",
  870. .parent_data = gcc_xo_gpll0_parent_data,
  871. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  872. .ops = &clk_rcg2_ops,
  873. },
  874. };
  875. static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
  876. F(3686400, P_GPLL0, 1, 72, 15625),
  877. F(7372800, P_GPLL0, 1, 144, 15625),
  878. F(14745600, P_GPLL0, 1, 288, 15625),
  879. F(16000000, P_GPLL0, 10, 1, 5),
  880. F(19200000, P_XO, 1, 0, 0),
  881. F(24000000, P_GPLL0, 1, 3, 100),
  882. F(25000000, P_GPLL0, 16, 1, 2),
  883. F(32000000, P_GPLL0, 1, 1, 25),
  884. F(40000000, P_GPLL0, 1, 1, 20),
  885. F(46400000, P_GPLL0, 1, 29, 500),
  886. F(48000000, P_GPLL0, 1, 3, 50),
  887. F(51200000, P_GPLL0, 1, 8, 125),
  888. F(56000000, P_GPLL0, 1, 7, 100),
  889. F(58982400, P_GPLL0, 1, 1152, 15625),
  890. F(60000000, P_GPLL0, 1, 3, 40),
  891. { }
  892. };
  893. static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
  894. .cmd_rcgr = 0x02044,
  895. .mnd_width = 16,
  896. .hid_width = 5,
  897. .parent_map = gcc_xo_gpll0_map,
  898. .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
  899. .clkr.hw.init = &(struct clk_init_data){
  900. .name = "blsp1_uart1_apps_clk_src",
  901. .parent_data = gcc_xo_gpll0_parent_data,
  902. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  903. .ops = &clk_rcg2_ops,
  904. },
  905. };
  906. static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
  907. .cmd_rcgr = 0x03034,
  908. .mnd_width = 16,
  909. .hid_width = 5,
  910. .parent_map = gcc_xo_gpll0_map,
  911. .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
  912. .clkr.hw.init = &(struct clk_init_data){
  913. .name = "blsp1_uart2_apps_clk_src",
  914. .parent_data = gcc_xo_gpll0_parent_data,
  915. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  916. .ops = &clk_rcg2_ops,
  917. },
  918. };
  919. static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
  920. F(19200000, P_XO, 1, 0, 0),
  921. F(37500000, P_GPLL0, 1, 3, 64),
  922. { }
  923. };
  924. static struct clk_rcg2 cci_clk_src = {
  925. .cmd_rcgr = 0x51000,
  926. .mnd_width = 8,
  927. .hid_width = 5,
  928. .parent_map = gcc_xo_gpll0a_map,
  929. .freq_tbl = ftbl_gcc_camss_cci_clk,
  930. .clkr.hw.init = &(struct clk_init_data){
  931. .name = "cci_clk_src",
  932. .parent_data = gcc_xo_gpll0a_parent_data,
  933. .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
  934. .ops = &clk_rcg2_ops,
  935. },
  936. };
  937. static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
  938. F(100000000, P_GPLL0, 8, 0, 0),
  939. F(200000000, P_GPLL0, 4, 0, 0),
  940. { }
  941. };
  942. static struct clk_rcg2 camss_gp0_clk_src = {
  943. .cmd_rcgr = 0x54000,
  944. .mnd_width = 8,
  945. .hid_width = 5,
  946. .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
  947. .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
  948. .clkr.hw.init = &(struct clk_init_data){
  949. .name = "camss_gp0_clk_src",
  950. .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
  951. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
  952. .ops = &clk_rcg2_ops,
  953. },
  954. };
  955. static struct clk_rcg2 camss_gp1_clk_src = {
  956. .cmd_rcgr = 0x55000,
  957. .mnd_width = 8,
  958. .hid_width = 5,
  959. .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
  960. .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
  961. .clkr.hw.init = &(struct clk_init_data){
  962. .name = "camss_gp1_clk_src",
  963. .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
  964. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
  965. .ops = &clk_rcg2_ops,
  966. },
  967. };
  968. static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
  969. F(133330000, P_GPLL0, 6, 0, 0),
  970. F(266670000, P_GPLL0, 3, 0, 0),
  971. F(320000000, P_GPLL0, 2.5, 0, 0),
  972. { }
  973. };
  974. static struct clk_rcg2 jpeg0_clk_src = {
  975. .cmd_rcgr = 0x57000,
  976. .hid_width = 5,
  977. .parent_map = gcc_xo_gpll0_map,
  978. .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
  979. .clkr.hw.init = &(struct clk_init_data){
  980. .name = "jpeg0_clk_src",
  981. .parent_data = gcc_xo_gpll0_parent_data,
  982. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  983. .ops = &clk_rcg2_ops,
  984. },
  985. };
  986. static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
  987. F(24000000, P_GPLL0, 1, 1, 45),
  988. F(66670000, P_GPLL0, 12, 0, 0),
  989. { }
  990. };
  991. static struct clk_rcg2 mclk0_clk_src = {
  992. .cmd_rcgr = 0x52000,
  993. .mnd_width = 8,
  994. .hid_width = 5,
  995. .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
  996. .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
  997. .clkr.hw.init = &(struct clk_init_data){
  998. .name = "mclk0_clk_src",
  999. .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
  1000. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
  1001. .ops = &clk_rcg2_ops,
  1002. },
  1003. };
  1004. static struct clk_rcg2 mclk1_clk_src = {
  1005. .cmd_rcgr = 0x53000,
  1006. .mnd_width = 8,
  1007. .hid_width = 5,
  1008. .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
  1009. .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
  1010. .clkr.hw.init = &(struct clk_init_data){
  1011. .name = "mclk1_clk_src",
  1012. .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
  1013. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
  1014. .ops = &clk_rcg2_ops,
  1015. },
  1016. };
  1017. static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
  1018. F(100000000, P_GPLL0, 8, 0, 0),
  1019. F(200000000, P_GPLL0, 4, 0, 0),
  1020. { }
  1021. };
  1022. static struct clk_rcg2 csi0phytimer_clk_src = {
  1023. .cmd_rcgr = 0x4e000,
  1024. .hid_width = 5,
  1025. .parent_map = gcc_xo_gpll0_gpll1a_map,
  1026. .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
  1027. .clkr.hw.init = &(struct clk_init_data){
  1028. .name = "csi0phytimer_clk_src",
  1029. .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
  1030. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
  1031. .ops = &clk_rcg2_ops,
  1032. },
  1033. };
  1034. static struct clk_rcg2 csi1phytimer_clk_src = {
  1035. .cmd_rcgr = 0x4f000,
  1036. .hid_width = 5,
  1037. .parent_map = gcc_xo_gpll0_gpll1a_map,
  1038. .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
  1039. .clkr.hw.init = &(struct clk_init_data){
  1040. .name = "csi1phytimer_clk_src",
  1041. .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
  1042. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
  1043. .ops = &clk_rcg2_ops,
  1044. },
  1045. };
  1046. static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
  1047. F(160000000, P_GPLL0, 5, 0, 0),
  1048. F(200000000, P_GPLL0, 4, 0, 0),
  1049. F(228570000, P_GPLL0, 3.5, 0, 0),
  1050. F(266670000, P_GPLL0, 3, 0, 0),
  1051. F(320000000, P_GPLL0, 2.5, 0, 0),
  1052. F(465000000, P_GPLL2, 2, 0, 0),
  1053. { }
  1054. };
  1055. static struct clk_rcg2 cpp_clk_src = {
  1056. .cmd_rcgr = 0x58018,
  1057. .hid_width = 5,
  1058. .parent_map = gcc_xo_gpll0_gpll2_map,
  1059. .freq_tbl = ftbl_gcc_camss_cpp_clk,
  1060. .clkr.hw.init = &(struct clk_init_data){
  1061. .name = "cpp_clk_src",
  1062. .parent_data = gcc_xo_gpll0_gpll2_parent_data,
  1063. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_parent_data),
  1064. .ops = &clk_rcg2_ops,
  1065. },
  1066. };
  1067. static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
  1068. F(50000000, P_GPLL0, 16, 0, 0),
  1069. F(80000000, P_GPLL0, 10, 0, 0),
  1070. F(100000000, P_GPLL0, 8, 0, 0),
  1071. F(160000000, P_GPLL0, 5, 0, 0),
  1072. { }
  1073. };
  1074. /* This is not in the documentation but is in the downstream driver */
  1075. static struct clk_rcg2 crypto_clk_src = {
  1076. .cmd_rcgr = 0x16004,
  1077. .hid_width = 5,
  1078. .parent_map = gcc_xo_gpll0_map,
  1079. .freq_tbl = ftbl_gcc_crypto_clk,
  1080. .clkr.hw.init = &(struct clk_init_data){
  1081. .name = "crypto_clk_src",
  1082. .parent_data = gcc_xo_gpll0_parent_data,
  1083. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  1084. .ops = &clk_rcg2_ops,
  1085. },
  1086. };
  1087. static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
  1088. F(19200000, P_XO, 1, 0, 0),
  1089. { }
  1090. };
  1091. static struct clk_rcg2 gp1_clk_src = {
  1092. .cmd_rcgr = 0x08004,
  1093. .mnd_width = 8,
  1094. .hid_width = 5,
  1095. .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
  1096. .freq_tbl = ftbl_gcc_gp1_3_clk,
  1097. .clkr.hw.init = &(struct clk_init_data){
  1098. .name = "gp1_clk_src",
  1099. .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
  1100. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
  1101. .ops = &clk_rcg2_ops,
  1102. },
  1103. };
  1104. static struct clk_rcg2 gp2_clk_src = {
  1105. .cmd_rcgr = 0x09004,
  1106. .mnd_width = 8,
  1107. .hid_width = 5,
  1108. .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
  1109. .freq_tbl = ftbl_gcc_gp1_3_clk,
  1110. .clkr.hw.init = &(struct clk_init_data){
  1111. .name = "gp2_clk_src",
  1112. .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
  1113. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
  1114. .ops = &clk_rcg2_ops,
  1115. },
  1116. };
  1117. static struct clk_rcg2 gp3_clk_src = {
  1118. .cmd_rcgr = 0x0a004,
  1119. .mnd_width = 8,
  1120. .hid_width = 5,
  1121. .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
  1122. .freq_tbl = ftbl_gcc_gp1_3_clk,
  1123. .clkr.hw.init = &(struct clk_init_data){
  1124. .name = "gp3_clk_src",
  1125. .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
  1126. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
  1127. .ops = &clk_rcg2_ops,
  1128. },
  1129. };
  1130. static struct clk_rcg2 byte0_clk_src = {
  1131. .cmd_rcgr = 0x4d044,
  1132. .hid_width = 5,
  1133. .parent_map = gcc_xo_gpll0a_dsibyte_map,
  1134. .clkr.hw.init = &(struct clk_init_data){
  1135. .name = "byte0_clk_src",
  1136. .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
  1137. .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
  1138. .ops = &clk_byte2_ops,
  1139. .flags = CLK_SET_RATE_PARENT,
  1140. },
  1141. };
  1142. static struct clk_rcg2 byte1_clk_src = {
  1143. .cmd_rcgr = 0x4d0b0,
  1144. .hid_width = 5,
  1145. .parent_map = gcc_xo_gpll0a_dsibyte_map,
  1146. .clkr.hw.init = &(struct clk_init_data){
  1147. .name = "byte1_clk_src",
  1148. .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
  1149. .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
  1150. .ops = &clk_byte2_ops,
  1151. .flags = CLK_SET_RATE_PARENT,
  1152. },
  1153. };
  1154. static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] = {
  1155. F(19200000, P_XO, 1, 0, 0),
  1156. { }
  1157. };
  1158. static struct clk_rcg2 esc0_clk_src = {
  1159. .cmd_rcgr = 0x4d060,
  1160. .hid_width = 5,
  1161. .parent_map = gcc_xo_dsibyte_map,
  1162. .freq_tbl = ftbl_gcc_mdss_esc_clk,
  1163. .clkr.hw.init = &(struct clk_init_data){
  1164. .name = "esc0_clk_src",
  1165. .parent_data = gcc_xo_dsibyte_parent_data,
  1166. .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
  1167. .ops = &clk_rcg2_ops,
  1168. },
  1169. };
  1170. static struct clk_rcg2 esc1_clk_src = {
  1171. .cmd_rcgr = 0x4d0a8,
  1172. .hid_width = 5,
  1173. .parent_map = gcc_xo_dsibyte_map,
  1174. .freq_tbl = ftbl_gcc_mdss_esc_clk,
  1175. .clkr.hw.init = &(struct clk_init_data){
  1176. .name = "esc1_clk_src",
  1177. .parent_data = gcc_xo_dsibyte_parent_data,
  1178. .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
  1179. .ops = &clk_rcg2_ops,
  1180. },
  1181. };
  1182. static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
  1183. F(50000000, P_GPLL0_AUX, 16, 0, 0),
  1184. F(80000000, P_GPLL0_AUX, 10, 0, 0),
  1185. F(100000000, P_GPLL0_AUX, 8, 0, 0),
  1186. F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
  1187. F(153600000, P_GPLL0, 4, 0, 0),
  1188. F(160000000, P_GPLL0_AUX, 5, 0, 0),
  1189. F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
  1190. F(200000000, P_GPLL0_AUX, 4, 0, 0),
  1191. F(266670000, P_GPLL0_AUX, 3, 0, 0),
  1192. F(307200000, P_GPLL1, 2, 0, 0),
  1193. F(366670000, P_GPLL3_AUX, 3, 0, 0),
  1194. { }
  1195. };
  1196. static struct clk_rcg2 mdp_clk_src = {
  1197. .cmd_rcgr = 0x4d014,
  1198. .hid_width = 5,
  1199. .parent_map = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map,
  1200. .freq_tbl = ftbl_gcc_mdss_mdp_clk,
  1201. .clkr.hw.init = &(struct clk_init_data){
  1202. .name = "mdp_clk_src",
  1203. .parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data,
  1204. .num_parents = ARRAY_SIZE(gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data),
  1205. .ops = &clk_rcg2_ops,
  1206. },
  1207. };
  1208. static struct clk_rcg2 pclk0_clk_src = {
  1209. .cmd_rcgr = 0x4d000,
  1210. .mnd_width = 8,
  1211. .hid_width = 5,
  1212. .parent_map = gcc_xo_gpll0a_dsiphy_map,
  1213. .clkr.hw.init = &(struct clk_init_data){
  1214. .name = "pclk0_clk_src",
  1215. .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
  1216. .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
  1217. .ops = &clk_pixel_ops,
  1218. .flags = CLK_SET_RATE_PARENT,
  1219. },
  1220. };
  1221. static struct clk_rcg2 pclk1_clk_src = {
  1222. .cmd_rcgr = 0x4d0b8,
  1223. .mnd_width = 8,
  1224. .hid_width = 5,
  1225. .parent_map = gcc_xo_gpll0a_dsiphy_map,
  1226. .clkr.hw.init = &(struct clk_init_data){
  1227. .name = "pclk1_clk_src",
  1228. .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
  1229. .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
  1230. .ops = &clk_pixel_ops,
  1231. .flags = CLK_SET_RATE_PARENT,
  1232. },
  1233. };
  1234. static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
  1235. F(19200000, P_XO, 1, 0, 0),
  1236. { }
  1237. };
  1238. static struct clk_rcg2 vsync_clk_src = {
  1239. .cmd_rcgr = 0x4d02c,
  1240. .hid_width = 5,
  1241. .parent_map = gcc_xo_gpll0a_map,
  1242. .freq_tbl = ftbl_gcc_mdss_vsync_clk,
  1243. .clkr.hw.init = &(struct clk_init_data){
  1244. .name = "vsync_clk_src",
  1245. .parent_data = gcc_xo_gpll0a_parent_data,
  1246. .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
  1247. .ops = &clk_rcg2_ops,
  1248. },
  1249. };
  1250. static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
  1251. F(64000000, P_GPLL0, 12.5, 0, 0),
  1252. { }
  1253. };
  1254. /* This is not in the documentation but is in the downstream driver */
  1255. static struct clk_rcg2 pdm2_clk_src = {
  1256. .cmd_rcgr = 0x44010,
  1257. .hid_width = 5,
  1258. .parent_map = gcc_xo_gpll0_map,
  1259. .freq_tbl = ftbl_gcc_pdm2_clk,
  1260. .clkr.hw.init = &(struct clk_init_data){
  1261. .name = "pdm2_clk_src",
  1262. .parent_data = gcc_xo_gpll0_parent_data,
  1263. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  1264. .ops = &clk_rcg2_ops,
  1265. },
  1266. };
  1267. static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
  1268. F(144000, P_XO, 16, 3, 25),
  1269. F(400000, P_XO, 12, 1, 4),
  1270. F(20000000, P_GPLL0, 10, 1, 4),
  1271. F(25000000, P_GPLL0, 16, 1, 2),
  1272. F(50000000, P_GPLL0, 16, 0, 0),
  1273. F(100000000, P_GPLL0, 8, 0, 0),
  1274. F(177770000, P_GPLL0, 4.5, 0, 0),
  1275. F(200000000, P_GPLL0, 4, 0, 0),
  1276. { }
  1277. };
  1278. static struct clk_rcg2 sdcc1_apps_clk_src = {
  1279. .cmd_rcgr = 0x42004,
  1280. .mnd_width = 8,
  1281. .hid_width = 5,
  1282. .parent_map = gcc_xo_gpll0_map,
  1283. .freq_tbl = ftbl_gcc_sdcc_apps_clk,
  1284. .clkr.hw.init = &(struct clk_init_data){
  1285. .name = "sdcc1_apps_clk_src",
  1286. .parent_data = gcc_xo_gpll0_parent_data,
  1287. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  1288. .ops = &clk_rcg2_floor_ops,
  1289. },
  1290. };
  1291. static struct clk_rcg2 sdcc2_apps_clk_src = {
  1292. .cmd_rcgr = 0x43004,
  1293. .mnd_width = 8,
  1294. .hid_width = 5,
  1295. .parent_map = gcc_xo_gpll0_map,
  1296. .freq_tbl = ftbl_gcc_sdcc_apps_clk,
  1297. .clkr.hw.init = &(struct clk_init_data){
  1298. .name = "sdcc2_apps_clk_src",
  1299. .parent_data = gcc_xo_gpll0_parent_data,
  1300. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  1301. .ops = &clk_rcg2_floor_ops,
  1302. },
  1303. };
  1304. static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
  1305. F(154285000, P_GPLL6, 7, 0, 0),
  1306. F(320000000, P_GPLL0, 2.5, 0, 0),
  1307. F(400000000, P_GPLL0, 2, 0, 0),
  1308. { }
  1309. };
  1310. static struct clk_rcg2 apss_tcu_clk_src = {
  1311. .cmd_rcgr = 0x1207c,
  1312. .hid_width = 5,
  1313. .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
  1314. .freq_tbl = ftbl_gcc_apss_tcu_clk,
  1315. .clkr.hw.init = &(struct clk_init_data){
  1316. .name = "apss_tcu_clk_src",
  1317. .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
  1318. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
  1319. .ops = &clk_rcg2_ops,
  1320. },
  1321. };
  1322. static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
  1323. F(19200000, P_XO, 1, 0, 0),
  1324. F(100000000, P_GPLL0, 8, 0, 0),
  1325. F(200000000, P_GPLL0, 4, 0, 0),
  1326. F(266500000, P_BIMC, 4, 0, 0),
  1327. F(400000000, P_GPLL0, 2, 0, 0),
  1328. F(533000000, P_BIMC, 2, 0, 0),
  1329. { }
  1330. };
  1331. static struct clk_rcg2 bimc_gpu_clk_src = {
  1332. .cmd_rcgr = 0x31028,
  1333. .hid_width = 5,
  1334. .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
  1335. .freq_tbl = ftbl_gcc_bimc_gpu_clk,
  1336. .clkr.hw.init = &(struct clk_init_data){
  1337. .name = "bimc_gpu_clk_src",
  1338. .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
  1339. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
  1340. .flags = CLK_GET_RATE_NOCACHE,
  1341. .ops = &clk_rcg2_ops,
  1342. },
  1343. };
  1344. static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
  1345. F(57140000, P_GPLL0, 14, 0, 0),
  1346. F(80000000, P_GPLL0, 10, 0, 0),
  1347. F(100000000, P_GPLL0, 8, 0, 0),
  1348. { }
  1349. };
  1350. static struct clk_rcg2 usb_hs_system_clk_src = {
  1351. .cmd_rcgr = 0x41010,
  1352. .hid_width = 5,
  1353. .parent_map = gcc_xo_gpll0_map,
  1354. .freq_tbl = ftbl_gcc_usb_hs_system_clk,
  1355. .clkr.hw.init = &(struct clk_init_data){
  1356. .name = "usb_hs_system_clk_src",
  1357. .parent_data = gcc_xo_gpll0_parent_data,
  1358. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  1359. .ops = &clk_rcg2_ops,
  1360. },
  1361. };
  1362. static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
  1363. F(64000000, P_GPLL0, 12.5, 0, 0),
  1364. { }
  1365. };
  1366. static struct clk_rcg2 usb_fs_system_clk_src = {
  1367. .cmd_rcgr = 0x3f010,
  1368. .hid_width = 5,
  1369. .parent_map = gcc_xo_gpll0_map,
  1370. .freq_tbl = ftbl_gcc_usb_fs_system_clk,
  1371. .clkr.hw.init = &(struct clk_init_data){
  1372. .name = "usb_fs_system_clk_src",
  1373. .parent_data = gcc_xo_gpll6_gpll0_parent_data,
  1374. .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_parent_data),
  1375. .ops = &clk_rcg2_ops,
  1376. },
  1377. };
  1378. static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
  1379. F(60000000, P_GPLL6, 1, 1, 18),
  1380. { }
  1381. };
  1382. static struct clk_rcg2 usb_fs_ic_clk_src = {
  1383. .cmd_rcgr = 0x3f034,
  1384. .hid_width = 5,
  1385. .parent_map = gcc_xo_gpll0_map,
  1386. .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
  1387. .clkr.hw.init = &(struct clk_init_data){
  1388. .name = "usb_fs_ic_clk_src",
  1389. .parent_data = gcc_xo_gpll6_gpll0a_parent_data,
  1390. .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0a_parent_data),
  1391. .ops = &clk_rcg2_ops,
  1392. },
  1393. };
  1394. static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
  1395. F(3200000, P_XO, 6, 0, 0),
  1396. F(6400000, P_XO, 3, 0, 0),
  1397. F(9600000, P_XO, 2, 0, 0),
  1398. F(19200000, P_XO, 1, 0, 0),
  1399. F(40000000, P_GPLL0, 10, 1, 2),
  1400. F(66670000, P_GPLL0, 12, 0, 0),
  1401. F(80000000, P_GPLL0, 10, 0, 0),
  1402. F(100000000, P_GPLL0, 8, 0, 0),
  1403. { }
  1404. };
  1405. static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
  1406. .cmd_rcgr = 0x1c010,
  1407. .hid_width = 5,
  1408. .mnd_width = 8,
  1409. .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
  1410. .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
  1411. .clkr.hw.init = &(struct clk_init_data){
  1412. .name = "ultaudio_ahbfabric_clk_src",
  1413. .parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data,
  1414. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep_parent_data),
  1415. .ops = &clk_rcg2_ops,
  1416. },
  1417. };
  1418. static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
  1419. .halt_reg = 0x1c028,
  1420. .clkr = {
  1421. .enable_reg = 0x1c028,
  1422. .enable_mask = BIT(0),
  1423. .hw.init = &(struct clk_init_data){
  1424. .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
  1425. .parent_hws = (const struct clk_hw*[]){
  1426. &ultaudio_ahbfabric_clk_src.clkr.hw,
  1427. },
  1428. .num_parents = 1,
  1429. .flags = CLK_SET_RATE_PARENT,
  1430. .ops = &clk_branch2_ops,
  1431. },
  1432. },
  1433. };
  1434. static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
  1435. .halt_reg = 0x1c024,
  1436. .clkr = {
  1437. .enable_reg = 0x1c024,
  1438. .enable_mask = BIT(0),
  1439. .hw.init = &(struct clk_init_data){
  1440. .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
  1441. .parent_hws = (const struct clk_hw*[]){
  1442. &ultaudio_ahbfabric_clk_src.clkr.hw,
  1443. },
  1444. .num_parents = 1,
  1445. .flags = CLK_SET_RATE_PARENT,
  1446. .ops = &clk_branch2_ops,
  1447. },
  1448. },
  1449. };
  1450. static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
  1451. F(128000, P_XO, 10, 1, 15),
  1452. F(256000, P_XO, 5, 1, 15),
  1453. F(384000, P_XO, 5, 1, 10),
  1454. F(512000, P_XO, 5, 2, 15),
  1455. F(576000, P_XO, 5, 3, 20),
  1456. F(705600, P_GPLL1, 16, 1, 80),
  1457. F(768000, P_XO, 5, 1, 5),
  1458. F(800000, P_XO, 5, 5, 24),
  1459. F(1024000, P_XO, 5, 4, 15),
  1460. F(1152000, P_XO, 1, 3, 50),
  1461. F(1411200, P_GPLL1, 16, 1, 40),
  1462. F(1536000, P_XO, 1, 2, 25),
  1463. F(1600000, P_XO, 12, 0, 0),
  1464. F(1728000, P_XO, 5, 9, 20),
  1465. F(2048000, P_XO, 5, 8, 15),
  1466. F(2304000, P_XO, 5, 3, 5),
  1467. F(2400000, P_XO, 8, 0, 0),
  1468. F(2822400, P_GPLL1, 16, 1, 20),
  1469. F(3072000, P_XO, 5, 4, 5),
  1470. F(4096000, P_GPLL1, 9, 2, 49),
  1471. F(4800000, P_XO, 4, 0, 0),
  1472. F(5644800, P_GPLL1, 16, 1, 10),
  1473. F(6144000, P_GPLL1, 7, 1, 21),
  1474. F(8192000, P_GPLL1, 9, 4, 49),
  1475. F(9600000, P_XO, 2, 0, 0),
  1476. F(11289600, P_GPLL1, 16, 1, 5),
  1477. F(12288000, P_GPLL1, 7, 2, 21),
  1478. { }
  1479. };
  1480. static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
  1481. .cmd_rcgr = 0x1c054,
  1482. .hid_width = 5,
  1483. .mnd_width = 8,
  1484. .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
  1485. .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
  1486. .clkr.hw.init = &(struct clk_init_data){
  1487. .name = "ultaudio_lpaif_pri_i2s_clk_src",
  1488. .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data,
  1489. .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep_parent_data),
  1490. .ops = &clk_rcg2_ops,
  1491. },
  1492. };
  1493. static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
  1494. .halt_reg = 0x1c068,
  1495. .clkr = {
  1496. .enable_reg = 0x1c068,
  1497. .enable_mask = BIT(0),
  1498. .hw.init = &(struct clk_init_data){
  1499. .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
  1500. .parent_hws = (const struct clk_hw*[]){
  1501. &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
  1502. },
  1503. .num_parents = 1,
  1504. .flags = CLK_SET_RATE_PARENT,
  1505. .ops = &clk_branch2_ops,
  1506. },
  1507. },
  1508. };
  1509. static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
  1510. .cmd_rcgr = 0x1c06c,
  1511. .hid_width = 5,
  1512. .mnd_width = 8,
  1513. .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
  1514. .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
  1515. .clkr.hw.init = &(struct clk_init_data){
  1516. .name = "ultaudio_lpaif_sec_i2s_clk_src",
  1517. .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
  1518. .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
  1519. .ops = &clk_rcg2_ops,
  1520. },
  1521. };
  1522. static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
  1523. .halt_reg = 0x1c080,
  1524. .clkr = {
  1525. .enable_reg = 0x1c080,
  1526. .enable_mask = BIT(0),
  1527. .hw.init = &(struct clk_init_data){
  1528. .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
  1529. .parent_hws = (const struct clk_hw*[]){
  1530. &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
  1531. },
  1532. .num_parents = 1,
  1533. .flags = CLK_SET_RATE_PARENT,
  1534. .ops = &clk_branch2_ops,
  1535. },
  1536. },
  1537. };
  1538. static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
  1539. .cmd_rcgr = 0x1c084,
  1540. .hid_width = 5,
  1541. .mnd_width = 8,
  1542. .parent_map = gcc_xo_gpll1_emclk_sleep_map,
  1543. .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
  1544. .clkr.hw.init = &(struct clk_init_data){
  1545. .name = "ultaudio_lpaif_aux_i2s_clk_src",
  1546. .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
  1547. .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
  1548. .ops = &clk_rcg2_ops,
  1549. },
  1550. };
  1551. static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
  1552. .halt_reg = 0x1c098,
  1553. .clkr = {
  1554. .enable_reg = 0x1c098,
  1555. .enable_mask = BIT(0),
  1556. .hw.init = &(struct clk_init_data){
  1557. .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
  1558. .parent_hws = (const struct clk_hw*[]){
  1559. &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
  1560. },
  1561. .num_parents = 1,
  1562. .flags = CLK_SET_RATE_PARENT,
  1563. .ops = &clk_branch2_ops,
  1564. },
  1565. },
  1566. };
  1567. static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
  1568. F(19200000, P_XO, 1, 0, 0),
  1569. { }
  1570. };
  1571. static struct clk_rcg2 ultaudio_xo_clk_src = {
  1572. .cmd_rcgr = 0x1c034,
  1573. .hid_width = 5,
  1574. .parent_map = gcc_xo_sleep_map,
  1575. .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
  1576. .clkr.hw.init = &(struct clk_init_data){
  1577. .name = "ultaudio_xo_clk_src",
  1578. .parent_data = gcc_xo_sleep_parent_data,
  1579. .num_parents = ARRAY_SIZE(gcc_xo_sleep_parent_data),
  1580. .ops = &clk_rcg2_ops,
  1581. },
  1582. };
  1583. static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
  1584. .halt_reg = 0x1c04c,
  1585. .clkr = {
  1586. .enable_reg = 0x1c04c,
  1587. .enable_mask = BIT(0),
  1588. .hw.init = &(struct clk_init_data){
  1589. .name = "gcc_ultaudio_avsync_xo_clk",
  1590. .parent_hws = (const struct clk_hw*[]){
  1591. &ultaudio_xo_clk_src.clkr.hw,
  1592. },
  1593. .num_parents = 1,
  1594. .flags = CLK_SET_RATE_PARENT,
  1595. .ops = &clk_branch2_ops,
  1596. },
  1597. },
  1598. };
  1599. static struct clk_branch gcc_ultaudio_stc_xo_clk = {
  1600. .halt_reg = 0x1c050,
  1601. .clkr = {
  1602. .enable_reg = 0x1c050,
  1603. .enable_mask = BIT(0),
  1604. .hw.init = &(struct clk_init_data){
  1605. .name = "gcc_ultaudio_stc_xo_clk",
  1606. .parent_hws = (const struct clk_hw*[]){
  1607. &ultaudio_xo_clk_src.clkr.hw,
  1608. },
  1609. .num_parents = 1,
  1610. .flags = CLK_SET_RATE_PARENT,
  1611. .ops = &clk_branch2_ops,
  1612. },
  1613. },
  1614. };
  1615. static const struct freq_tbl ftbl_codec_clk[] = {
  1616. F(9600000, P_XO, 2, 0, 0),
  1617. F(12288000, P_XO, 1, 16, 25),
  1618. F(19200000, P_XO, 1, 0, 0),
  1619. F(11289600, P_EXT_MCLK, 1, 0, 0),
  1620. { }
  1621. };
  1622. static struct clk_rcg2 codec_digcodec_clk_src = {
  1623. .cmd_rcgr = 0x1c09c,
  1624. .mnd_width = 8,
  1625. .hid_width = 5,
  1626. .parent_map = gcc_xo_gpll1_emclk_sleep_map,
  1627. .freq_tbl = ftbl_codec_clk,
  1628. .clkr.hw.init = &(struct clk_init_data){
  1629. .name = "codec_digcodec_clk_src",
  1630. .parent_data = gcc_xo_gpll1_emclk_sleep_parent_data,
  1631. .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep_parent_data),
  1632. .ops = &clk_rcg2_ops,
  1633. },
  1634. };
  1635. static struct clk_branch gcc_codec_digcodec_clk = {
  1636. .halt_reg = 0x1c0b0,
  1637. .clkr = {
  1638. .enable_reg = 0x1c0b0,
  1639. .enable_mask = BIT(0),
  1640. .hw.init = &(struct clk_init_data){
  1641. .name = "gcc_ultaudio_codec_digcodec_clk",
  1642. .parent_hws = (const struct clk_hw*[]){
  1643. &codec_digcodec_clk_src.clkr.hw,
  1644. },
  1645. .num_parents = 1,
  1646. .flags = CLK_SET_RATE_PARENT,
  1647. .ops = &clk_branch2_ops,
  1648. },
  1649. },
  1650. };
  1651. static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
  1652. .halt_reg = 0x1c000,
  1653. .clkr = {
  1654. .enable_reg = 0x1c000,
  1655. .enable_mask = BIT(0),
  1656. .hw.init = &(struct clk_init_data){
  1657. .name = "gcc_ultaudio_pcnoc_mport_clk",
  1658. .parent_hws = (const struct clk_hw*[]){
  1659. &pcnoc_bfdcd_clk_src.clkr.hw,
  1660. },
  1661. .num_parents = 1,
  1662. .ops = &clk_branch2_ops,
  1663. },
  1664. },
  1665. };
  1666. static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
  1667. .halt_reg = 0x1c004,
  1668. .clkr = {
  1669. .enable_reg = 0x1c004,
  1670. .enable_mask = BIT(0),
  1671. .hw.init = &(struct clk_init_data){
  1672. .name = "gcc_ultaudio_pcnoc_sway_clk",
  1673. .parent_hws = (const struct clk_hw*[]){
  1674. &pcnoc_bfdcd_clk_src.clkr.hw,
  1675. },
  1676. .num_parents = 1,
  1677. .ops = &clk_branch2_ops,
  1678. },
  1679. },
  1680. };
  1681. static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
  1682. F(133330000, P_GPLL0, 6, 0, 0),
  1683. F(200000000, P_GPLL0, 4, 0, 0),
  1684. F(266670000, P_GPLL0, 3, 0, 0),
  1685. { }
  1686. };
  1687. static struct clk_rcg2 vcodec0_clk_src = {
  1688. .cmd_rcgr = 0x4C000,
  1689. .mnd_width = 8,
  1690. .hid_width = 5,
  1691. .parent_map = gcc_xo_gpll0_map,
  1692. .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
  1693. .clkr.hw.init = &(struct clk_init_data){
  1694. .name = "vcodec0_clk_src",
  1695. .parent_data = gcc_xo_gpll0_parent_data,
  1696. .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
  1697. .ops = &clk_rcg2_ops,
  1698. },
  1699. };
  1700. static struct clk_branch gcc_blsp1_ahb_clk = {
  1701. .halt_reg = 0x01008,
  1702. .halt_check = BRANCH_HALT_VOTED,
  1703. .clkr = {
  1704. .enable_reg = 0x45004,
  1705. .enable_mask = BIT(10),
  1706. .hw.init = &(struct clk_init_data){
  1707. .name = "gcc_blsp1_ahb_clk",
  1708. .parent_hws = (const struct clk_hw*[]){
  1709. &pcnoc_bfdcd_clk_src.clkr.hw,
  1710. },
  1711. .num_parents = 1,
  1712. .ops = &clk_branch2_ops,
  1713. },
  1714. },
  1715. };
  1716. static struct clk_branch gcc_blsp1_sleep_clk = {
  1717. .halt_reg = 0x01004,
  1718. .clkr = {
  1719. .enable_reg = 0x01004,
  1720. .enable_mask = BIT(0),
  1721. .hw.init = &(struct clk_init_data){
  1722. .name = "gcc_blsp1_sleep_clk",
  1723. .ops = &clk_branch2_ops,
  1724. },
  1725. },
  1726. };
  1727. static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
  1728. .halt_reg = 0x02008,
  1729. .clkr = {
  1730. .enable_reg = 0x02008,
  1731. .enable_mask = BIT(0),
  1732. .hw.init = &(struct clk_init_data){
  1733. .name = "gcc_blsp1_qup1_i2c_apps_clk",
  1734. .parent_hws = (const struct clk_hw*[]){
  1735. &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
  1736. },
  1737. .num_parents = 1,
  1738. .flags = CLK_SET_RATE_PARENT,
  1739. .ops = &clk_branch2_ops,
  1740. },
  1741. },
  1742. };
  1743. static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
  1744. .halt_reg = 0x02004,
  1745. .clkr = {
  1746. .enable_reg = 0x02004,
  1747. .enable_mask = BIT(0),
  1748. .hw.init = &(struct clk_init_data){
  1749. .name = "gcc_blsp1_qup1_spi_apps_clk",
  1750. .parent_hws = (const struct clk_hw*[]){
  1751. &blsp1_qup1_spi_apps_clk_src.clkr.hw,
  1752. },
  1753. .num_parents = 1,
  1754. .flags = CLK_SET_RATE_PARENT,
  1755. .ops = &clk_branch2_ops,
  1756. },
  1757. },
  1758. };
  1759. static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
  1760. .halt_reg = 0x03010,
  1761. .clkr = {
  1762. .enable_reg = 0x03010,
  1763. .enable_mask = BIT(0),
  1764. .hw.init = &(struct clk_init_data){
  1765. .name = "gcc_blsp1_qup2_i2c_apps_clk",
  1766. .parent_hws = (const struct clk_hw*[]){
  1767. &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
  1768. },
  1769. .num_parents = 1,
  1770. .flags = CLK_SET_RATE_PARENT,
  1771. .ops = &clk_branch2_ops,
  1772. },
  1773. },
  1774. };
  1775. static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
  1776. .halt_reg = 0x0300c,
  1777. .clkr = {
  1778. .enable_reg = 0x0300c,
  1779. .enable_mask = BIT(0),
  1780. .hw.init = &(struct clk_init_data){
  1781. .name = "gcc_blsp1_qup2_spi_apps_clk",
  1782. .parent_hws = (const struct clk_hw*[]){
  1783. &blsp1_qup2_spi_apps_clk_src.clkr.hw,
  1784. },
  1785. .num_parents = 1,
  1786. .flags = CLK_SET_RATE_PARENT,
  1787. .ops = &clk_branch2_ops,
  1788. },
  1789. },
  1790. };
  1791. static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
  1792. .halt_reg = 0x04020,
  1793. .clkr = {
  1794. .enable_reg = 0x04020,
  1795. .enable_mask = BIT(0),
  1796. .hw.init = &(struct clk_init_data){
  1797. .name = "gcc_blsp1_qup3_i2c_apps_clk",
  1798. .parent_hws = (const struct clk_hw*[]){
  1799. &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
  1800. },
  1801. .num_parents = 1,
  1802. .flags = CLK_SET_RATE_PARENT,
  1803. .ops = &clk_branch2_ops,
  1804. },
  1805. },
  1806. };
  1807. static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
  1808. .halt_reg = 0x0401c,
  1809. .clkr = {
  1810. .enable_reg = 0x0401c,
  1811. .enable_mask = BIT(0),
  1812. .hw.init = &(struct clk_init_data){
  1813. .name = "gcc_blsp1_qup3_spi_apps_clk",
  1814. .parent_hws = (const struct clk_hw*[]){
  1815. &blsp1_qup3_spi_apps_clk_src.clkr.hw,
  1816. },
  1817. .num_parents = 1,
  1818. .flags = CLK_SET_RATE_PARENT,
  1819. .ops = &clk_branch2_ops,
  1820. },
  1821. },
  1822. };
  1823. static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
  1824. .halt_reg = 0x05020,
  1825. .clkr = {
  1826. .enable_reg = 0x05020,
  1827. .enable_mask = BIT(0),
  1828. .hw.init = &(struct clk_init_data){
  1829. .name = "gcc_blsp1_qup4_i2c_apps_clk",
  1830. .parent_hws = (const struct clk_hw*[]){
  1831. &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
  1832. },
  1833. .num_parents = 1,
  1834. .flags = CLK_SET_RATE_PARENT,
  1835. .ops = &clk_branch2_ops,
  1836. },
  1837. },
  1838. };
  1839. static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
  1840. .halt_reg = 0x0501c,
  1841. .clkr = {
  1842. .enable_reg = 0x0501c,
  1843. .enable_mask = BIT(0),
  1844. .hw.init = &(struct clk_init_data){
  1845. .name = "gcc_blsp1_qup4_spi_apps_clk",
  1846. .parent_hws = (const struct clk_hw*[]){
  1847. &blsp1_qup4_spi_apps_clk_src.clkr.hw,
  1848. },
  1849. .num_parents = 1,
  1850. .flags = CLK_SET_RATE_PARENT,
  1851. .ops = &clk_branch2_ops,
  1852. },
  1853. },
  1854. };
  1855. static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
  1856. .halt_reg = 0x06020,
  1857. .clkr = {
  1858. .enable_reg = 0x06020,
  1859. .enable_mask = BIT(0),
  1860. .hw.init = &(struct clk_init_data){
  1861. .name = "gcc_blsp1_qup5_i2c_apps_clk",
  1862. .parent_hws = (const struct clk_hw*[]){
  1863. &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
  1864. },
  1865. .num_parents = 1,
  1866. .flags = CLK_SET_RATE_PARENT,
  1867. .ops = &clk_branch2_ops,
  1868. },
  1869. },
  1870. };
  1871. static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
  1872. .halt_reg = 0x0601c,
  1873. .clkr = {
  1874. .enable_reg = 0x0601c,
  1875. .enable_mask = BIT(0),
  1876. .hw.init = &(struct clk_init_data){
  1877. .name = "gcc_blsp1_qup5_spi_apps_clk",
  1878. .parent_hws = (const struct clk_hw*[]){
  1879. &blsp1_qup5_spi_apps_clk_src.clkr.hw,
  1880. },
  1881. .num_parents = 1,
  1882. .flags = CLK_SET_RATE_PARENT,
  1883. .ops = &clk_branch2_ops,
  1884. },
  1885. },
  1886. };
  1887. static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
  1888. .halt_reg = 0x07020,
  1889. .clkr = {
  1890. .enable_reg = 0x07020,
  1891. .enable_mask = BIT(0),
  1892. .hw.init = &(struct clk_init_data){
  1893. .name = "gcc_blsp1_qup6_i2c_apps_clk",
  1894. .parent_hws = (const struct clk_hw*[]){
  1895. &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
  1896. },
  1897. .num_parents = 1,
  1898. .flags = CLK_SET_RATE_PARENT,
  1899. .ops = &clk_branch2_ops,
  1900. },
  1901. },
  1902. };
  1903. static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
  1904. .halt_reg = 0x0701c,
  1905. .clkr = {
  1906. .enable_reg = 0x0701c,
  1907. .enable_mask = BIT(0),
  1908. .hw.init = &(struct clk_init_data){
  1909. .name = "gcc_blsp1_qup6_spi_apps_clk",
  1910. .parent_hws = (const struct clk_hw*[]){
  1911. &blsp1_qup6_spi_apps_clk_src.clkr.hw,
  1912. },
  1913. .num_parents = 1,
  1914. .flags = CLK_SET_RATE_PARENT,
  1915. .ops = &clk_branch2_ops,
  1916. },
  1917. },
  1918. };
  1919. static struct clk_branch gcc_blsp1_uart1_apps_clk = {
  1920. .halt_reg = 0x0203c,
  1921. .clkr = {
  1922. .enable_reg = 0x0203c,
  1923. .enable_mask = BIT(0),
  1924. .hw.init = &(struct clk_init_data){
  1925. .name = "gcc_blsp1_uart1_apps_clk",
  1926. .parent_hws = (const struct clk_hw*[]){
  1927. &blsp1_uart1_apps_clk_src.clkr.hw,
  1928. },
  1929. .num_parents = 1,
  1930. .flags = CLK_SET_RATE_PARENT,
  1931. .ops = &clk_branch2_ops,
  1932. },
  1933. },
  1934. };
  1935. static struct clk_branch gcc_blsp1_uart2_apps_clk = {
  1936. .halt_reg = 0x0302c,
  1937. .clkr = {
  1938. .enable_reg = 0x0302c,
  1939. .enable_mask = BIT(0),
  1940. .hw.init = &(struct clk_init_data){
  1941. .name = "gcc_blsp1_uart2_apps_clk",
  1942. .parent_hws = (const struct clk_hw*[]){
  1943. &blsp1_uart2_apps_clk_src.clkr.hw,
  1944. },
  1945. .num_parents = 1,
  1946. .flags = CLK_SET_RATE_PARENT,
  1947. .ops = &clk_branch2_ops,
  1948. },
  1949. },
  1950. };
  1951. static struct clk_branch gcc_boot_rom_ahb_clk = {
  1952. .halt_reg = 0x1300c,
  1953. .halt_check = BRANCH_HALT_VOTED,
  1954. .clkr = {
  1955. .enable_reg = 0x45004,
  1956. .enable_mask = BIT(7),
  1957. .hw.init = &(struct clk_init_data){
  1958. .name = "gcc_boot_rom_ahb_clk",
  1959. .parent_hws = (const struct clk_hw*[]){
  1960. &pcnoc_bfdcd_clk_src.clkr.hw,
  1961. },
  1962. .num_parents = 1,
  1963. .ops = &clk_branch2_ops,
  1964. },
  1965. },
  1966. };
  1967. static struct clk_branch gcc_camss_cci_ahb_clk = {
  1968. .halt_reg = 0x5101c,
  1969. .clkr = {
  1970. .enable_reg = 0x5101c,
  1971. .enable_mask = BIT(0),
  1972. .hw.init = &(struct clk_init_data){
  1973. .name = "gcc_camss_cci_ahb_clk",
  1974. .parent_hws = (const struct clk_hw*[]){
  1975. &camss_ahb_clk_src.clkr.hw,
  1976. },
  1977. .num_parents = 1,
  1978. .flags = CLK_SET_RATE_PARENT,
  1979. .ops = &clk_branch2_ops,
  1980. },
  1981. },
  1982. };
  1983. static struct clk_branch gcc_camss_cci_clk = {
  1984. .halt_reg = 0x51018,
  1985. .clkr = {
  1986. .enable_reg = 0x51018,
  1987. .enable_mask = BIT(0),
  1988. .hw.init = &(struct clk_init_data){
  1989. .name = "gcc_camss_cci_clk",
  1990. .parent_hws = (const struct clk_hw*[]){
  1991. &cci_clk_src.clkr.hw,
  1992. },
  1993. .num_parents = 1,
  1994. .flags = CLK_SET_RATE_PARENT,
  1995. .ops = &clk_branch2_ops,
  1996. },
  1997. },
  1998. };
  1999. static struct clk_branch gcc_camss_csi0_ahb_clk = {
  2000. .halt_reg = 0x4e040,
  2001. .clkr = {
  2002. .enable_reg = 0x4e040,
  2003. .enable_mask = BIT(0),
  2004. .hw.init = &(struct clk_init_data){
  2005. .name = "gcc_camss_csi0_ahb_clk",
  2006. .parent_hws = (const struct clk_hw*[]){
  2007. &camss_ahb_clk_src.clkr.hw,
  2008. },
  2009. .num_parents = 1,
  2010. .flags = CLK_SET_RATE_PARENT,
  2011. .ops = &clk_branch2_ops,
  2012. },
  2013. },
  2014. };
  2015. static struct clk_branch gcc_camss_csi0_clk = {
  2016. .halt_reg = 0x4e03c,
  2017. .clkr = {
  2018. .enable_reg = 0x4e03c,
  2019. .enable_mask = BIT(0),
  2020. .hw.init = &(struct clk_init_data){
  2021. .name = "gcc_camss_csi0_clk",
  2022. .parent_hws = (const struct clk_hw*[]){
  2023. &csi0_clk_src.clkr.hw,
  2024. },
  2025. .num_parents = 1,
  2026. .flags = CLK_SET_RATE_PARENT,
  2027. .ops = &clk_branch2_ops,
  2028. },
  2029. },
  2030. };
  2031. static struct clk_branch gcc_camss_csi0phy_clk = {
  2032. .halt_reg = 0x4e048,
  2033. .clkr = {
  2034. .enable_reg = 0x4e048,
  2035. .enable_mask = BIT(0),
  2036. .hw.init = &(struct clk_init_data){
  2037. .name = "gcc_camss_csi0phy_clk",
  2038. .parent_hws = (const struct clk_hw*[]){
  2039. &csi0_clk_src.clkr.hw,
  2040. },
  2041. .num_parents = 1,
  2042. .flags = CLK_SET_RATE_PARENT,
  2043. .ops = &clk_branch2_ops,
  2044. },
  2045. },
  2046. };
  2047. static struct clk_branch gcc_camss_csi0pix_clk = {
  2048. .halt_reg = 0x4e058,
  2049. .clkr = {
  2050. .enable_reg = 0x4e058,
  2051. .enable_mask = BIT(0),
  2052. .hw.init = &(struct clk_init_data){
  2053. .name = "gcc_camss_csi0pix_clk",
  2054. .parent_hws = (const struct clk_hw*[]){
  2055. &csi0_clk_src.clkr.hw,
  2056. },
  2057. .num_parents = 1,
  2058. .flags = CLK_SET_RATE_PARENT,
  2059. .ops = &clk_branch2_ops,
  2060. },
  2061. },
  2062. };
  2063. static struct clk_branch gcc_camss_csi0rdi_clk = {
  2064. .halt_reg = 0x4e050,
  2065. .clkr = {
  2066. .enable_reg = 0x4e050,
  2067. .enable_mask = BIT(0),
  2068. .hw.init = &(struct clk_init_data){
  2069. .name = "gcc_camss_csi0rdi_clk",
  2070. .parent_hws = (const struct clk_hw*[]){
  2071. &csi0_clk_src.clkr.hw,
  2072. },
  2073. .num_parents = 1,
  2074. .flags = CLK_SET_RATE_PARENT,
  2075. .ops = &clk_branch2_ops,
  2076. },
  2077. },
  2078. };
  2079. static struct clk_branch gcc_camss_csi1_ahb_clk = {
  2080. .halt_reg = 0x4f040,
  2081. .clkr = {
  2082. .enable_reg = 0x4f040,
  2083. .enable_mask = BIT(0),
  2084. .hw.init = &(struct clk_init_data){
  2085. .name = "gcc_camss_csi1_ahb_clk",
  2086. .parent_hws = (const struct clk_hw*[]){
  2087. &camss_ahb_clk_src.clkr.hw,
  2088. },
  2089. .num_parents = 1,
  2090. .flags = CLK_SET_RATE_PARENT,
  2091. .ops = &clk_branch2_ops,
  2092. },
  2093. },
  2094. };
  2095. static struct clk_branch gcc_camss_csi1_clk = {
  2096. .halt_reg = 0x4f03c,
  2097. .clkr = {
  2098. .enable_reg = 0x4f03c,
  2099. .enable_mask = BIT(0),
  2100. .hw.init = &(struct clk_init_data){
  2101. .name = "gcc_camss_csi1_clk",
  2102. .parent_hws = (const struct clk_hw*[]){
  2103. &csi1_clk_src.clkr.hw,
  2104. },
  2105. .num_parents = 1,
  2106. .flags = CLK_SET_RATE_PARENT,
  2107. .ops = &clk_branch2_ops,
  2108. },
  2109. },
  2110. };
  2111. static struct clk_branch gcc_camss_csi1phy_clk = {
  2112. .halt_reg = 0x4f048,
  2113. .clkr = {
  2114. .enable_reg = 0x4f048,
  2115. .enable_mask = BIT(0),
  2116. .hw.init = &(struct clk_init_data){
  2117. .name = "gcc_camss_csi1phy_clk",
  2118. .parent_hws = (const struct clk_hw*[]){
  2119. &csi1_clk_src.clkr.hw,
  2120. },
  2121. .num_parents = 1,
  2122. .flags = CLK_SET_RATE_PARENT,
  2123. .ops = &clk_branch2_ops,
  2124. },
  2125. },
  2126. };
  2127. static struct clk_branch gcc_camss_csi1pix_clk = {
  2128. .halt_reg = 0x4f058,
  2129. .clkr = {
  2130. .enable_reg = 0x4f058,
  2131. .enable_mask = BIT(0),
  2132. .hw.init = &(struct clk_init_data){
  2133. .name = "gcc_camss_csi1pix_clk",
  2134. .parent_hws = (const struct clk_hw*[]){
  2135. &csi1_clk_src.clkr.hw,
  2136. },
  2137. .num_parents = 1,
  2138. .flags = CLK_SET_RATE_PARENT,
  2139. .ops = &clk_branch2_ops,
  2140. },
  2141. },
  2142. };
  2143. static struct clk_branch gcc_camss_csi1rdi_clk = {
  2144. .halt_reg = 0x4f050,
  2145. .clkr = {
  2146. .enable_reg = 0x4f050,
  2147. .enable_mask = BIT(0),
  2148. .hw.init = &(struct clk_init_data){
  2149. .name = "gcc_camss_csi1rdi_clk",
  2150. .parent_hws = (const struct clk_hw*[]){
  2151. &csi1_clk_src.clkr.hw,
  2152. },
  2153. .num_parents = 1,
  2154. .flags = CLK_SET_RATE_PARENT,
  2155. .ops = &clk_branch2_ops,
  2156. },
  2157. },
  2158. };
  2159. static struct clk_branch gcc_camss_csi_vfe0_clk = {
  2160. .halt_reg = 0x58050,
  2161. .clkr = {
  2162. .enable_reg = 0x58050,
  2163. .enable_mask = BIT(0),
  2164. .hw.init = &(struct clk_init_data){
  2165. .name = "gcc_camss_csi_vfe0_clk",
  2166. .parent_hws = (const struct clk_hw*[]){
  2167. &vfe0_clk_src.clkr.hw,
  2168. },
  2169. .num_parents = 1,
  2170. .flags = CLK_SET_RATE_PARENT,
  2171. .ops = &clk_branch2_ops,
  2172. },
  2173. },
  2174. };
  2175. static struct clk_branch gcc_camss_gp0_clk = {
  2176. .halt_reg = 0x54018,
  2177. .clkr = {
  2178. .enable_reg = 0x54018,
  2179. .enable_mask = BIT(0),
  2180. .hw.init = &(struct clk_init_data){
  2181. .name = "gcc_camss_gp0_clk",
  2182. .parent_hws = (const struct clk_hw*[]){
  2183. &camss_gp0_clk_src.clkr.hw,
  2184. },
  2185. .num_parents = 1,
  2186. .flags = CLK_SET_RATE_PARENT,
  2187. .ops = &clk_branch2_ops,
  2188. },
  2189. },
  2190. };
  2191. static struct clk_branch gcc_camss_gp1_clk = {
  2192. .halt_reg = 0x55018,
  2193. .clkr = {
  2194. .enable_reg = 0x55018,
  2195. .enable_mask = BIT(0),
  2196. .hw.init = &(struct clk_init_data){
  2197. .name = "gcc_camss_gp1_clk",
  2198. .parent_hws = (const struct clk_hw*[]){
  2199. &camss_gp1_clk_src.clkr.hw,
  2200. },
  2201. .num_parents = 1,
  2202. .flags = CLK_SET_RATE_PARENT,
  2203. .ops = &clk_branch2_ops,
  2204. },
  2205. },
  2206. };
  2207. static struct clk_branch gcc_camss_ispif_ahb_clk = {
  2208. .halt_reg = 0x50004,
  2209. .clkr = {
  2210. .enable_reg = 0x50004,
  2211. .enable_mask = BIT(0),
  2212. .hw.init = &(struct clk_init_data){
  2213. .name = "gcc_camss_ispif_ahb_clk",
  2214. .parent_hws = (const struct clk_hw*[]){
  2215. &camss_ahb_clk_src.clkr.hw,
  2216. },
  2217. .num_parents = 1,
  2218. .flags = CLK_SET_RATE_PARENT,
  2219. .ops = &clk_branch2_ops,
  2220. },
  2221. },
  2222. };
  2223. static struct clk_branch gcc_camss_jpeg0_clk = {
  2224. .halt_reg = 0x57020,
  2225. .clkr = {
  2226. .enable_reg = 0x57020,
  2227. .enable_mask = BIT(0),
  2228. .hw.init = &(struct clk_init_data){
  2229. .name = "gcc_camss_jpeg0_clk",
  2230. .parent_hws = (const struct clk_hw*[]){
  2231. &jpeg0_clk_src.clkr.hw,
  2232. },
  2233. .num_parents = 1,
  2234. .flags = CLK_SET_RATE_PARENT,
  2235. .ops = &clk_branch2_ops,
  2236. },
  2237. },
  2238. };
  2239. static struct clk_branch gcc_camss_jpeg_ahb_clk = {
  2240. .halt_reg = 0x57024,
  2241. .clkr = {
  2242. .enable_reg = 0x57024,
  2243. .enable_mask = BIT(0),
  2244. .hw.init = &(struct clk_init_data){
  2245. .name = "gcc_camss_jpeg_ahb_clk",
  2246. .parent_hws = (const struct clk_hw*[]){
  2247. &camss_ahb_clk_src.clkr.hw,
  2248. },
  2249. .num_parents = 1,
  2250. .flags = CLK_SET_RATE_PARENT,
  2251. .ops = &clk_branch2_ops,
  2252. },
  2253. },
  2254. };
  2255. static struct clk_branch gcc_camss_jpeg_axi_clk = {
  2256. .halt_reg = 0x57028,
  2257. .clkr = {
  2258. .enable_reg = 0x57028,
  2259. .enable_mask = BIT(0),
  2260. .hw.init = &(struct clk_init_data){
  2261. .name = "gcc_camss_jpeg_axi_clk",
  2262. .parent_hws = (const struct clk_hw*[]){
  2263. &system_mm_noc_bfdcd_clk_src.clkr.hw,
  2264. },
  2265. .num_parents = 1,
  2266. .flags = CLK_SET_RATE_PARENT,
  2267. .ops = &clk_branch2_ops,
  2268. },
  2269. },
  2270. };
  2271. static struct clk_branch gcc_camss_mclk0_clk = {
  2272. .halt_reg = 0x52018,
  2273. .clkr = {
  2274. .enable_reg = 0x52018,
  2275. .enable_mask = BIT(0),
  2276. .hw.init = &(struct clk_init_data){
  2277. .name = "gcc_camss_mclk0_clk",
  2278. .parent_hws = (const struct clk_hw*[]){
  2279. &mclk0_clk_src.clkr.hw,
  2280. },
  2281. .num_parents = 1,
  2282. .flags = CLK_SET_RATE_PARENT,
  2283. .ops = &clk_branch2_ops,
  2284. },
  2285. },
  2286. };
  2287. static struct clk_branch gcc_camss_mclk1_clk = {
  2288. .halt_reg = 0x53018,
  2289. .clkr = {
  2290. .enable_reg = 0x53018,
  2291. .enable_mask = BIT(0),
  2292. .hw.init = &(struct clk_init_data){
  2293. .name = "gcc_camss_mclk1_clk",
  2294. .parent_hws = (const struct clk_hw*[]){
  2295. &mclk1_clk_src.clkr.hw,
  2296. },
  2297. .num_parents = 1,
  2298. .flags = CLK_SET_RATE_PARENT,
  2299. .ops = &clk_branch2_ops,
  2300. },
  2301. },
  2302. };
  2303. static struct clk_branch gcc_camss_micro_ahb_clk = {
  2304. .halt_reg = 0x5600c,
  2305. .clkr = {
  2306. .enable_reg = 0x5600c,
  2307. .enable_mask = BIT(0),
  2308. .hw.init = &(struct clk_init_data){
  2309. .name = "gcc_camss_micro_ahb_clk",
  2310. .parent_hws = (const struct clk_hw*[]){
  2311. &camss_ahb_clk_src.clkr.hw,
  2312. },
  2313. .num_parents = 1,
  2314. .flags = CLK_SET_RATE_PARENT,
  2315. .ops = &clk_branch2_ops,
  2316. },
  2317. },
  2318. };
  2319. static struct clk_branch gcc_camss_csi0phytimer_clk = {
  2320. .halt_reg = 0x4e01c,
  2321. .clkr = {
  2322. .enable_reg = 0x4e01c,
  2323. .enable_mask = BIT(0),
  2324. .hw.init = &(struct clk_init_data){
  2325. .name = "gcc_camss_csi0phytimer_clk",
  2326. .parent_hws = (const struct clk_hw*[]){
  2327. &csi0phytimer_clk_src.clkr.hw,
  2328. },
  2329. .num_parents = 1,
  2330. .flags = CLK_SET_RATE_PARENT,
  2331. .ops = &clk_branch2_ops,
  2332. },
  2333. },
  2334. };
  2335. static struct clk_branch gcc_camss_csi1phytimer_clk = {
  2336. .halt_reg = 0x4f01c,
  2337. .clkr = {
  2338. .enable_reg = 0x4f01c,
  2339. .enable_mask = BIT(0),
  2340. .hw.init = &(struct clk_init_data){
  2341. .name = "gcc_camss_csi1phytimer_clk",
  2342. .parent_hws = (const struct clk_hw*[]){
  2343. &csi1phytimer_clk_src.clkr.hw,
  2344. },
  2345. .num_parents = 1,
  2346. .flags = CLK_SET_RATE_PARENT,
  2347. .ops = &clk_branch2_ops,
  2348. },
  2349. },
  2350. };
  2351. static struct clk_branch gcc_camss_ahb_clk = {
  2352. .halt_reg = 0x5a014,
  2353. .clkr = {
  2354. .enable_reg = 0x5a014,
  2355. .enable_mask = BIT(0),
  2356. .hw.init = &(struct clk_init_data){
  2357. .name = "gcc_camss_ahb_clk",
  2358. .parent_hws = (const struct clk_hw*[]){
  2359. &camss_ahb_clk_src.clkr.hw,
  2360. },
  2361. .num_parents = 1,
  2362. .flags = CLK_SET_RATE_PARENT,
  2363. .ops = &clk_branch2_ops,
  2364. },
  2365. },
  2366. };
  2367. static struct clk_branch gcc_camss_top_ahb_clk = {
  2368. .halt_reg = 0x56004,
  2369. .clkr = {
  2370. .enable_reg = 0x56004,
  2371. .enable_mask = BIT(0),
  2372. .hw.init = &(struct clk_init_data){
  2373. .name = "gcc_camss_top_ahb_clk",
  2374. .parent_hws = (const struct clk_hw*[]){
  2375. &pcnoc_bfdcd_clk_src.clkr.hw,
  2376. },
  2377. .num_parents = 1,
  2378. .flags = CLK_SET_RATE_PARENT,
  2379. .ops = &clk_branch2_ops,
  2380. },
  2381. },
  2382. };
  2383. static struct clk_branch gcc_camss_cpp_ahb_clk = {
  2384. .halt_reg = 0x58040,
  2385. .clkr = {
  2386. .enable_reg = 0x58040,
  2387. .enable_mask = BIT(0),
  2388. .hw.init = &(struct clk_init_data){
  2389. .name = "gcc_camss_cpp_ahb_clk",
  2390. .parent_hws = (const struct clk_hw*[]){
  2391. &camss_ahb_clk_src.clkr.hw,
  2392. },
  2393. .num_parents = 1,
  2394. .flags = CLK_SET_RATE_PARENT,
  2395. .ops = &clk_branch2_ops,
  2396. },
  2397. },
  2398. };
  2399. static struct clk_branch gcc_camss_cpp_clk = {
  2400. .halt_reg = 0x5803c,
  2401. .clkr = {
  2402. .enable_reg = 0x5803c,
  2403. .enable_mask = BIT(0),
  2404. .hw.init = &(struct clk_init_data){
  2405. .name = "gcc_camss_cpp_clk",
  2406. .parent_hws = (const struct clk_hw*[]){
  2407. &cpp_clk_src.clkr.hw,
  2408. },
  2409. .num_parents = 1,
  2410. .flags = CLK_SET_RATE_PARENT,
  2411. .ops = &clk_branch2_ops,
  2412. },
  2413. },
  2414. };
  2415. static struct clk_branch gcc_camss_vfe0_clk = {
  2416. .halt_reg = 0x58038,
  2417. .clkr = {
  2418. .enable_reg = 0x58038,
  2419. .enable_mask = BIT(0),
  2420. .hw.init = &(struct clk_init_data){
  2421. .name = "gcc_camss_vfe0_clk",
  2422. .parent_hws = (const struct clk_hw*[]){
  2423. &vfe0_clk_src.clkr.hw,
  2424. },
  2425. .num_parents = 1,
  2426. .flags = CLK_SET_RATE_PARENT,
  2427. .ops = &clk_branch2_ops,
  2428. },
  2429. },
  2430. };
  2431. static struct clk_branch gcc_camss_vfe_ahb_clk = {
  2432. .halt_reg = 0x58044,
  2433. .clkr = {
  2434. .enable_reg = 0x58044,
  2435. .enable_mask = BIT(0),
  2436. .hw.init = &(struct clk_init_data){
  2437. .name = "gcc_camss_vfe_ahb_clk",
  2438. .parent_hws = (const struct clk_hw*[]){
  2439. &camss_ahb_clk_src.clkr.hw,
  2440. },
  2441. .num_parents = 1,
  2442. .flags = CLK_SET_RATE_PARENT,
  2443. .ops = &clk_branch2_ops,
  2444. },
  2445. },
  2446. };
  2447. static struct clk_branch gcc_camss_vfe_axi_clk = {
  2448. .halt_reg = 0x58048,
  2449. .clkr = {
  2450. .enable_reg = 0x58048,
  2451. .enable_mask = BIT(0),
  2452. .hw.init = &(struct clk_init_data){
  2453. .name = "gcc_camss_vfe_axi_clk",
  2454. .parent_hws = (const struct clk_hw*[]){
  2455. &system_mm_noc_bfdcd_clk_src.clkr.hw,
  2456. },
  2457. .num_parents = 1,
  2458. .flags = CLK_SET_RATE_PARENT,
  2459. .ops = &clk_branch2_ops,
  2460. },
  2461. },
  2462. };
  2463. static struct clk_branch gcc_crypto_ahb_clk = {
  2464. .halt_reg = 0x16024,
  2465. .halt_check = BRANCH_HALT_VOTED,
  2466. .clkr = {
  2467. .enable_reg = 0x45004,
  2468. .enable_mask = BIT(0),
  2469. .hw.init = &(struct clk_init_data){
  2470. .name = "gcc_crypto_ahb_clk",
  2471. .parent_hws = (const struct clk_hw*[]){
  2472. &pcnoc_bfdcd_clk_src.clkr.hw,
  2473. },
  2474. .num_parents = 1,
  2475. .flags = CLK_SET_RATE_PARENT,
  2476. .ops = &clk_branch2_ops,
  2477. },
  2478. },
  2479. };
  2480. static struct clk_branch gcc_crypto_axi_clk = {
  2481. .halt_reg = 0x16020,
  2482. .halt_check = BRANCH_HALT_VOTED,
  2483. .clkr = {
  2484. .enable_reg = 0x45004,
  2485. .enable_mask = BIT(1),
  2486. .hw.init = &(struct clk_init_data){
  2487. .name = "gcc_crypto_axi_clk",
  2488. .parent_hws = (const struct clk_hw*[]){
  2489. &pcnoc_bfdcd_clk_src.clkr.hw,
  2490. },
  2491. .num_parents = 1,
  2492. .flags = CLK_SET_RATE_PARENT,
  2493. .ops = &clk_branch2_ops,
  2494. },
  2495. },
  2496. };
  2497. static struct clk_branch gcc_crypto_clk = {
  2498. .halt_reg = 0x1601c,
  2499. .halt_check = BRANCH_HALT_VOTED,
  2500. .clkr = {
  2501. .enable_reg = 0x45004,
  2502. .enable_mask = BIT(2),
  2503. .hw.init = &(struct clk_init_data){
  2504. .name = "gcc_crypto_clk",
  2505. .parent_hws = (const struct clk_hw*[]){
  2506. &crypto_clk_src.clkr.hw,
  2507. },
  2508. .num_parents = 1,
  2509. .flags = CLK_SET_RATE_PARENT,
  2510. .ops = &clk_branch2_ops,
  2511. },
  2512. },
  2513. };
  2514. static struct clk_branch gcc_oxili_gmem_clk = {
  2515. .halt_reg = 0x59024,
  2516. .clkr = {
  2517. .enable_reg = 0x59024,
  2518. .enable_mask = BIT(0),
  2519. .hw.init = &(struct clk_init_data){
  2520. .name = "gcc_oxili_gmem_clk",
  2521. .parent_hws = (const struct clk_hw*[]){
  2522. &gfx3d_clk_src.clkr.hw,
  2523. },
  2524. .num_parents = 1,
  2525. .flags = CLK_SET_RATE_PARENT,
  2526. .ops = &clk_branch2_ops,
  2527. },
  2528. },
  2529. };
  2530. static struct clk_branch gcc_gp1_clk = {
  2531. .halt_reg = 0x08000,
  2532. .clkr = {
  2533. .enable_reg = 0x08000,
  2534. .enable_mask = BIT(0),
  2535. .hw.init = &(struct clk_init_data){
  2536. .name = "gcc_gp1_clk",
  2537. .parent_hws = (const struct clk_hw*[]){
  2538. &gp1_clk_src.clkr.hw,
  2539. },
  2540. .num_parents = 1,
  2541. .flags = CLK_SET_RATE_PARENT,
  2542. .ops = &clk_branch2_ops,
  2543. },
  2544. },
  2545. };
  2546. static struct clk_branch gcc_gp2_clk = {
  2547. .halt_reg = 0x09000,
  2548. .clkr = {
  2549. .enable_reg = 0x09000,
  2550. .enable_mask = BIT(0),
  2551. .hw.init = &(struct clk_init_data){
  2552. .name = "gcc_gp2_clk",
  2553. .parent_hws = (const struct clk_hw*[]){
  2554. &gp2_clk_src.clkr.hw,
  2555. },
  2556. .num_parents = 1,
  2557. .flags = CLK_SET_RATE_PARENT,
  2558. .ops = &clk_branch2_ops,
  2559. },
  2560. },
  2561. };
  2562. static struct clk_branch gcc_gp3_clk = {
  2563. .halt_reg = 0x0a000,
  2564. .clkr = {
  2565. .enable_reg = 0x0a000,
  2566. .enable_mask = BIT(0),
  2567. .hw.init = &(struct clk_init_data){
  2568. .name = "gcc_gp3_clk",
  2569. .parent_hws = (const struct clk_hw*[]){
  2570. &gp3_clk_src.clkr.hw,
  2571. },
  2572. .num_parents = 1,
  2573. .flags = CLK_SET_RATE_PARENT,
  2574. .ops = &clk_branch2_ops,
  2575. },
  2576. },
  2577. };
  2578. static struct clk_branch gcc_mdss_ahb_clk = {
  2579. .halt_reg = 0x4d07c,
  2580. .clkr = {
  2581. .enable_reg = 0x4d07c,
  2582. .enable_mask = BIT(0),
  2583. .hw.init = &(struct clk_init_data){
  2584. .name = "gcc_mdss_ahb_clk",
  2585. .parent_hws = (const struct clk_hw*[]){
  2586. &pcnoc_bfdcd_clk_src.clkr.hw,
  2587. },
  2588. .num_parents = 1,
  2589. .flags = CLK_SET_RATE_PARENT,
  2590. .ops = &clk_branch2_ops,
  2591. },
  2592. },
  2593. };
  2594. static struct clk_branch gcc_mdss_axi_clk = {
  2595. .halt_reg = 0x4d080,
  2596. .clkr = {
  2597. .enable_reg = 0x4d080,
  2598. .enable_mask = BIT(0),
  2599. .hw.init = &(struct clk_init_data){
  2600. .name = "gcc_mdss_axi_clk",
  2601. .parent_hws = (const struct clk_hw*[]){
  2602. &system_mm_noc_bfdcd_clk_src.clkr.hw,
  2603. },
  2604. .num_parents = 1,
  2605. .flags = CLK_SET_RATE_PARENT,
  2606. .ops = &clk_branch2_ops,
  2607. },
  2608. },
  2609. };
  2610. static struct clk_branch gcc_mdss_byte0_clk = {
  2611. .halt_reg = 0x4d094,
  2612. .clkr = {
  2613. .enable_reg = 0x4d094,
  2614. .enable_mask = BIT(0),
  2615. .hw.init = &(struct clk_init_data){
  2616. .name = "gcc_mdss_byte0_clk",
  2617. .parent_hws = (const struct clk_hw*[]){
  2618. &byte0_clk_src.clkr.hw,
  2619. },
  2620. .num_parents = 1,
  2621. .flags = CLK_SET_RATE_PARENT,
  2622. .ops = &clk_branch2_ops,
  2623. },
  2624. },
  2625. };
  2626. static struct clk_branch gcc_mdss_byte1_clk = {
  2627. .halt_reg = 0x4d0a0,
  2628. .clkr = {
  2629. .enable_reg = 0x4d0a0,
  2630. .enable_mask = BIT(0),
  2631. .hw.init = &(struct clk_init_data){
  2632. .name = "gcc_mdss_byte1_clk",
  2633. .parent_hws = (const struct clk_hw*[]){
  2634. &byte1_clk_src.clkr.hw,
  2635. },
  2636. .num_parents = 1,
  2637. .flags = CLK_SET_RATE_PARENT,
  2638. .ops = &clk_branch2_ops,
  2639. },
  2640. },
  2641. };
  2642. static struct clk_branch gcc_mdss_esc0_clk = {
  2643. .halt_reg = 0x4d098,
  2644. .clkr = {
  2645. .enable_reg = 0x4d098,
  2646. .enable_mask = BIT(0),
  2647. .hw.init = &(struct clk_init_data){
  2648. .name = "gcc_mdss_esc0_clk",
  2649. .parent_hws = (const struct clk_hw*[]){
  2650. &esc0_clk_src.clkr.hw,
  2651. },
  2652. .num_parents = 1,
  2653. .flags = CLK_SET_RATE_PARENT,
  2654. .ops = &clk_branch2_ops,
  2655. },
  2656. },
  2657. };
  2658. static struct clk_branch gcc_mdss_esc1_clk = {
  2659. .halt_reg = 0x4d09c,
  2660. .clkr = {
  2661. .enable_reg = 0x4d09c,
  2662. .enable_mask = BIT(0),
  2663. .hw.init = &(struct clk_init_data){
  2664. .name = "gcc_mdss_esc1_clk",
  2665. .parent_hws = (const struct clk_hw*[]){
  2666. &esc1_clk_src.clkr.hw,
  2667. },
  2668. .num_parents = 1,
  2669. .flags = CLK_SET_RATE_PARENT,
  2670. .ops = &clk_branch2_ops,
  2671. },
  2672. },
  2673. };
  2674. static struct clk_branch gcc_mdss_mdp_clk = {
  2675. .halt_reg = 0x4D088,
  2676. .clkr = {
  2677. .enable_reg = 0x4D088,
  2678. .enable_mask = BIT(0),
  2679. .hw.init = &(struct clk_init_data){
  2680. .name = "gcc_mdss_mdp_clk",
  2681. .parent_hws = (const struct clk_hw*[]){
  2682. &mdp_clk_src.clkr.hw,
  2683. },
  2684. .num_parents = 1,
  2685. .flags = CLK_SET_RATE_PARENT,
  2686. .ops = &clk_branch2_ops,
  2687. },
  2688. },
  2689. };
  2690. static struct clk_branch gcc_mdss_pclk0_clk = {
  2691. .halt_reg = 0x4d084,
  2692. .clkr = {
  2693. .enable_reg = 0x4d084,
  2694. .enable_mask = BIT(0),
  2695. .hw.init = &(struct clk_init_data){
  2696. .name = "gcc_mdss_pclk0_clk",
  2697. .parent_hws = (const struct clk_hw*[]){
  2698. &pclk0_clk_src.clkr.hw,
  2699. },
  2700. .num_parents = 1,
  2701. .flags = CLK_SET_RATE_PARENT,
  2702. .ops = &clk_branch2_ops,
  2703. },
  2704. },
  2705. };
  2706. static struct clk_branch gcc_mdss_pclk1_clk = {
  2707. .halt_reg = 0x4d0a4,
  2708. .clkr = {
  2709. .enable_reg = 0x4d0a4,
  2710. .enable_mask = BIT(0),
  2711. .hw.init = &(struct clk_init_data){
  2712. .name = "gcc_mdss_pclk1_clk",
  2713. .parent_hws = (const struct clk_hw*[]){
  2714. &pclk1_clk_src.clkr.hw,
  2715. },
  2716. .num_parents = 1,
  2717. .flags = CLK_SET_RATE_PARENT,
  2718. .ops = &clk_branch2_ops,
  2719. },
  2720. },
  2721. };
  2722. static struct clk_branch gcc_mdss_vsync_clk = {
  2723. .halt_reg = 0x4d090,
  2724. .clkr = {
  2725. .enable_reg = 0x4d090,
  2726. .enable_mask = BIT(0),
  2727. .hw.init = &(struct clk_init_data){
  2728. .name = "gcc_mdss_vsync_clk",
  2729. .parent_hws = (const struct clk_hw*[]){
  2730. &vsync_clk_src.clkr.hw,
  2731. },
  2732. .num_parents = 1,
  2733. .flags = CLK_SET_RATE_PARENT,
  2734. .ops = &clk_branch2_ops,
  2735. },
  2736. },
  2737. };
  2738. static struct clk_branch gcc_mss_cfg_ahb_clk = {
  2739. .halt_reg = 0x49000,
  2740. .clkr = {
  2741. .enable_reg = 0x49000,
  2742. .enable_mask = BIT(0),
  2743. .hw.init = &(struct clk_init_data){
  2744. .name = "gcc_mss_cfg_ahb_clk",
  2745. .parent_hws = (const struct clk_hw*[]){
  2746. &pcnoc_bfdcd_clk_src.clkr.hw,
  2747. },
  2748. .num_parents = 1,
  2749. .flags = CLK_SET_RATE_PARENT,
  2750. .ops = &clk_branch2_ops,
  2751. },
  2752. },
  2753. };
  2754. static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
  2755. .halt_reg = 0x49004,
  2756. .clkr = {
  2757. .enable_reg = 0x49004,
  2758. .enable_mask = BIT(0),
  2759. .hw.init = &(struct clk_init_data){
  2760. .name = "gcc_mss_q6_bimc_axi_clk",
  2761. .parent_hws = (const struct clk_hw*[]){
  2762. &bimc_ddr_clk_src.clkr.hw,
  2763. },
  2764. .num_parents = 1,
  2765. .flags = CLK_SET_RATE_PARENT,
  2766. .ops = &clk_branch2_ops,
  2767. },
  2768. },
  2769. };
  2770. static struct clk_branch gcc_oxili_ahb_clk = {
  2771. .halt_reg = 0x59028,
  2772. .clkr = {
  2773. .enable_reg = 0x59028,
  2774. .enable_mask = BIT(0),
  2775. .hw.init = &(struct clk_init_data){
  2776. .name = "gcc_oxili_ahb_clk",
  2777. .parent_hws = (const struct clk_hw*[]){
  2778. &pcnoc_bfdcd_clk_src.clkr.hw,
  2779. },
  2780. .num_parents = 1,
  2781. .flags = CLK_SET_RATE_PARENT,
  2782. .ops = &clk_branch2_ops,
  2783. },
  2784. },
  2785. };
  2786. static struct clk_branch gcc_oxili_gfx3d_clk = {
  2787. .halt_reg = 0x59020,
  2788. .clkr = {
  2789. .enable_reg = 0x59020,
  2790. .enable_mask = BIT(0),
  2791. .hw.init = &(struct clk_init_data){
  2792. .name = "gcc_oxili_gfx3d_clk",
  2793. .parent_hws = (const struct clk_hw*[]){
  2794. &gfx3d_clk_src.clkr.hw,
  2795. },
  2796. .num_parents = 1,
  2797. .flags = CLK_SET_RATE_PARENT,
  2798. .ops = &clk_branch2_ops,
  2799. },
  2800. },
  2801. };
  2802. static struct clk_branch gcc_pdm2_clk = {
  2803. .halt_reg = 0x4400c,
  2804. .clkr = {
  2805. .enable_reg = 0x4400c,
  2806. .enable_mask = BIT(0),
  2807. .hw.init = &(struct clk_init_data){
  2808. .name = "gcc_pdm2_clk",
  2809. .parent_hws = (const struct clk_hw*[]){
  2810. &pdm2_clk_src.clkr.hw,
  2811. },
  2812. .num_parents = 1,
  2813. .flags = CLK_SET_RATE_PARENT,
  2814. .ops = &clk_branch2_ops,
  2815. },
  2816. },
  2817. };
  2818. static struct clk_branch gcc_pdm_ahb_clk = {
  2819. .halt_reg = 0x44004,
  2820. .clkr = {
  2821. .enable_reg = 0x44004,
  2822. .enable_mask = BIT(0),
  2823. .hw.init = &(struct clk_init_data){
  2824. .name = "gcc_pdm_ahb_clk",
  2825. .parent_hws = (const struct clk_hw*[]){
  2826. &pcnoc_bfdcd_clk_src.clkr.hw,
  2827. },
  2828. .num_parents = 1,
  2829. .flags = CLK_SET_RATE_PARENT,
  2830. .ops = &clk_branch2_ops,
  2831. },
  2832. },
  2833. };
  2834. static struct clk_branch gcc_prng_ahb_clk = {
  2835. .halt_reg = 0x13004,
  2836. .halt_check = BRANCH_HALT_VOTED,
  2837. .clkr = {
  2838. .enable_reg = 0x45004,
  2839. .enable_mask = BIT(8),
  2840. .hw.init = &(struct clk_init_data){
  2841. .name = "gcc_prng_ahb_clk",
  2842. .parent_hws = (const struct clk_hw*[]){
  2843. &pcnoc_bfdcd_clk_src.clkr.hw,
  2844. },
  2845. .num_parents = 1,
  2846. .ops = &clk_branch2_ops,
  2847. },
  2848. },
  2849. };
  2850. static struct clk_branch gcc_sdcc1_ahb_clk = {
  2851. .halt_reg = 0x4201c,
  2852. .clkr = {
  2853. .enable_reg = 0x4201c,
  2854. .enable_mask = BIT(0),
  2855. .hw.init = &(struct clk_init_data){
  2856. .name = "gcc_sdcc1_ahb_clk",
  2857. .parent_hws = (const struct clk_hw*[]){
  2858. &pcnoc_bfdcd_clk_src.clkr.hw,
  2859. },
  2860. .num_parents = 1,
  2861. .flags = CLK_SET_RATE_PARENT,
  2862. .ops = &clk_branch2_ops,
  2863. },
  2864. },
  2865. };
  2866. static struct clk_branch gcc_sdcc1_apps_clk = {
  2867. .halt_reg = 0x42018,
  2868. .clkr = {
  2869. .enable_reg = 0x42018,
  2870. .enable_mask = BIT(0),
  2871. .hw.init = &(struct clk_init_data){
  2872. .name = "gcc_sdcc1_apps_clk",
  2873. .parent_hws = (const struct clk_hw*[]){
  2874. &sdcc1_apps_clk_src.clkr.hw,
  2875. },
  2876. .num_parents = 1,
  2877. .flags = CLK_SET_RATE_PARENT,
  2878. .ops = &clk_branch2_ops,
  2879. },
  2880. },
  2881. };
  2882. static struct clk_branch gcc_sdcc2_ahb_clk = {
  2883. .halt_reg = 0x4301c,
  2884. .clkr = {
  2885. .enable_reg = 0x4301c,
  2886. .enable_mask = BIT(0),
  2887. .hw.init = &(struct clk_init_data){
  2888. .name = "gcc_sdcc2_ahb_clk",
  2889. .parent_hws = (const struct clk_hw*[]){
  2890. &pcnoc_bfdcd_clk_src.clkr.hw,
  2891. },
  2892. .num_parents = 1,
  2893. .flags = CLK_SET_RATE_PARENT,
  2894. .ops = &clk_branch2_ops,
  2895. },
  2896. },
  2897. };
  2898. static struct clk_branch gcc_sdcc2_apps_clk = {
  2899. .halt_reg = 0x43018,
  2900. .clkr = {
  2901. .enable_reg = 0x43018,
  2902. .enable_mask = BIT(0),
  2903. .hw.init = &(struct clk_init_data){
  2904. .name = "gcc_sdcc2_apps_clk",
  2905. .parent_hws = (const struct clk_hw*[]){
  2906. &sdcc2_apps_clk_src.clkr.hw,
  2907. },
  2908. .num_parents = 1,
  2909. .flags = CLK_SET_RATE_PARENT,
  2910. .ops = &clk_branch2_ops,
  2911. },
  2912. },
  2913. };
  2914. static struct clk_branch gcc_apss_tcu_clk = {
  2915. .halt_reg = 0x12018,
  2916. .halt_check = BRANCH_HALT_VOTED,
  2917. .clkr = {
  2918. .enable_reg = 0x4500c,
  2919. .enable_mask = BIT(1),
  2920. .hw.init = &(struct clk_init_data){
  2921. .name = "gcc_apss_tcu_clk",
  2922. .parent_hws = (const struct clk_hw*[]){
  2923. &bimc_ddr_clk_src.clkr.hw,
  2924. },
  2925. .num_parents = 1,
  2926. .ops = &clk_branch2_ops,
  2927. },
  2928. },
  2929. };
  2930. static struct clk_branch gcc_gfx_tcu_clk = {
  2931. .halt_reg = 0x12020,
  2932. .halt_check = BRANCH_HALT_VOTED,
  2933. .clkr = {
  2934. .enable_reg = 0x4500c,
  2935. .enable_mask = BIT(2),
  2936. .hw.init = &(struct clk_init_data){
  2937. .name = "gcc_gfx_tcu_clk",
  2938. .parent_hws = (const struct clk_hw*[]){
  2939. &bimc_ddr_clk_src.clkr.hw,
  2940. },
  2941. .num_parents = 1,
  2942. .ops = &clk_branch2_ops,
  2943. },
  2944. },
  2945. };
  2946. static struct clk_branch gcc_gfx_tbu_clk = {
  2947. .halt_reg = 0x12010,
  2948. .halt_check = BRANCH_HALT_VOTED,
  2949. .clkr = {
  2950. .enable_reg = 0x4500c,
  2951. .enable_mask = BIT(3),
  2952. .hw.init = &(struct clk_init_data){
  2953. .name = "gcc_gfx_tbu_clk",
  2954. .parent_hws = (const struct clk_hw*[]){
  2955. &bimc_ddr_clk_src.clkr.hw,
  2956. },
  2957. .num_parents = 1,
  2958. .ops = &clk_branch2_ops,
  2959. },
  2960. },
  2961. };
  2962. static struct clk_branch gcc_mdp_tbu_clk = {
  2963. .halt_reg = 0x1201c,
  2964. .halt_check = BRANCH_HALT_VOTED,
  2965. .clkr = {
  2966. .enable_reg = 0x4500c,
  2967. .enable_mask = BIT(4),
  2968. .hw.init = &(struct clk_init_data){
  2969. .name = "gcc_mdp_tbu_clk",
  2970. .parent_hws = (const struct clk_hw*[]){
  2971. &system_mm_noc_bfdcd_clk_src.clkr.hw,
  2972. },
  2973. .num_parents = 1,
  2974. .flags = CLK_SET_RATE_PARENT,
  2975. .ops = &clk_branch2_ops,
  2976. },
  2977. },
  2978. };
  2979. static struct clk_branch gcc_venus_tbu_clk = {
  2980. .halt_reg = 0x12014,
  2981. .halt_check = BRANCH_HALT_VOTED,
  2982. .clkr = {
  2983. .enable_reg = 0x4500c,
  2984. .enable_mask = BIT(5),
  2985. .hw.init = &(struct clk_init_data){
  2986. .name = "gcc_venus_tbu_clk",
  2987. .parent_hws = (const struct clk_hw*[]){
  2988. &system_mm_noc_bfdcd_clk_src.clkr.hw,
  2989. },
  2990. .num_parents = 1,
  2991. .flags = CLK_SET_RATE_PARENT,
  2992. .ops = &clk_branch2_ops,
  2993. },
  2994. },
  2995. };
  2996. static struct clk_branch gcc_vfe_tbu_clk = {
  2997. .halt_reg = 0x1203c,
  2998. .halt_check = BRANCH_HALT_VOTED,
  2999. .clkr = {
  3000. .enable_reg = 0x4500c,
  3001. .enable_mask = BIT(9),
  3002. .hw.init = &(struct clk_init_data){
  3003. .name = "gcc_vfe_tbu_clk",
  3004. .parent_hws = (const struct clk_hw*[]){
  3005. &system_mm_noc_bfdcd_clk_src.clkr.hw,
  3006. },
  3007. .num_parents = 1,
  3008. .flags = CLK_SET_RATE_PARENT,
  3009. .ops = &clk_branch2_ops,
  3010. },
  3011. },
  3012. };
  3013. static struct clk_branch gcc_jpeg_tbu_clk = {
  3014. .halt_reg = 0x12034,
  3015. .halt_check = BRANCH_HALT_VOTED,
  3016. .clkr = {
  3017. .enable_reg = 0x4500c,
  3018. .enable_mask = BIT(10),
  3019. .hw.init = &(struct clk_init_data){
  3020. .name = "gcc_jpeg_tbu_clk",
  3021. .parent_hws = (const struct clk_hw*[]){
  3022. &system_mm_noc_bfdcd_clk_src.clkr.hw,
  3023. },
  3024. .num_parents = 1,
  3025. .flags = CLK_SET_RATE_PARENT,
  3026. .ops = &clk_branch2_ops,
  3027. },
  3028. },
  3029. };
  3030. static struct clk_branch gcc_smmu_cfg_clk = {
  3031. .halt_reg = 0x12038,
  3032. .halt_check = BRANCH_HALT_VOTED,
  3033. .clkr = {
  3034. .enable_reg = 0x4500c,
  3035. .enable_mask = BIT(12),
  3036. .hw.init = &(struct clk_init_data){
  3037. .name = "gcc_smmu_cfg_clk",
  3038. .parent_hws = (const struct clk_hw*[]){
  3039. &pcnoc_bfdcd_clk_src.clkr.hw,
  3040. },
  3041. .num_parents = 1,
  3042. .flags = CLK_SET_RATE_PARENT,
  3043. .ops = &clk_branch2_ops,
  3044. },
  3045. },
  3046. };
  3047. static struct clk_branch gcc_gtcu_ahb_clk = {
  3048. .halt_reg = 0x12044,
  3049. .halt_check = BRANCH_HALT_VOTED,
  3050. .clkr = {
  3051. .enable_reg = 0x4500c,
  3052. .enable_mask = BIT(13),
  3053. .hw.init = &(struct clk_init_data){
  3054. .name = "gcc_gtcu_ahb_clk",
  3055. .parent_hws = (const struct clk_hw*[]){
  3056. &pcnoc_bfdcd_clk_src.clkr.hw,
  3057. },
  3058. .num_parents = 1,
  3059. .flags = CLK_SET_RATE_PARENT,
  3060. .ops = &clk_branch2_ops,
  3061. },
  3062. },
  3063. };
  3064. static struct clk_branch gcc_cpp_tbu_clk = {
  3065. .halt_reg = 0x12040,
  3066. .halt_check = BRANCH_HALT_VOTED,
  3067. .clkr = {
  3068. .enable_reg = 0x4500c,
  3069. .enable_mask = BIT(14),
  3070. .hw.init = &(struct clk_init_data){
  3071. .name = "gcc_cpp_tbu_clk",
  3072. .parent_hws = (const struct clk_hw*[]){
  3073. &pcnoc_bfdcd_clk_src.clkr.hw,
  3074. },
  3075. .num_parents = 1,
  3076. .flags = CLK_SET_RATE_PARENT,
  3077. .ops = &clk_branch2_ops,
  3078. },
  3079. },
  3080. };
  3081. static struct clk_branch gcc_mdp_rt_tbu_clk = {
  3082. .halt_reg = 0x1201c,
  3083. .halt_check = BRANCH_HALT_VOTED,
  3084. .clkr = {
  3085. .enable_reg = 0x4500c,
  3086. .enable_mask = BIT(15),
  3087. .hw.init = &(struct clk_init_data){
  3088. .name = "gcc_mdp_rt_tbu_clk",
  3089. .parent_hws = (const struct clk_hw*[]){
  3090. &pcnoc_bfdcd_clk_src.clkr.hw,
  3091. },
  3092. .num_parents = 1,
  3093. .flags = CLK_SET_RATE_PARENT,
  3094. .ops = &clk_branch2_ops,
  3095. },
  3096. },
  3097. };
  3098. static struct clk_branch gcc_bimc_gfx_clk = {
  3099. .halt_reg = 0x31024,
  3100. .clkr = {
  3101. .enable_reg = 0x31024,
  3102. .enable_mask = BIT(0),
  3103. .hw.init = &(struct clk_init_data){
  3104. .name = "gcc_bimc_gfx_clk",
  3105. .parent_hws = (const struct clk_hw*[]){
  3106. &bimc_gpu_clk_src.clkr.hw,
  3107. },
  3108. .num_parents = 1,
  3109. .flags = CLK_SET_RATE_PARENT,
  3110. .ops = &clk_branch2_ops,
  3111. },
  3112. },
  3113. };
  3114. static struct clk_branch gcc_bimc_gpu_clk = {
  3115. .halt_reg = 0x31040,
  3116. .clkr = {
  3117. .enable_reg = 0x31040,
  3118. .enable_mask = BIT(0),
  3119. .hw.init = &(struct clk_init_data){
  3120. .name = "gcc_bimc_gpu_clk",
  3121. .parent_hws = (const struct clk_hw*[]){
  3122. &bimc_gpu_clk_src.clkr.hw,
  3123. },
  3124. .num_parents = 1,
  3125. .flags = CLK_SET_RATE_PARENT,
  3126. .ops = &clk_branch2_ops,
  3127. },
  3128. },
  3129. };
  3130. static struct clk_branch gcc_usb2a_phy_sleep_clk = {
  3131. .halt_reg = 0x4102c,
  3132. .clkr = {
  3133. .enable_reg = 0x4102c,
  3134. .enable_mask = BIT(0),
  3135. .hw.init = &(struct clk_init_data){
  3136. .name = "gcc_usb2a_phy_sleep_clk",
  3137. .ops = &clk_branch2_ops,
  3138. },
  3139. },
  3140. };
  3141. static struct clk_branch gcc_usb_fs_ahb_clk = {
  3142. .halt_reg = 0x3f008,
  3143. .clkr = {
  3144. .enable_reg = 0x3f008,
  3145. .enable_mask = BIT(0),
  3146. .hw.init = &(struct clk_init_data){
  3147. .name = "gcc_usb_fs_ahb_clk",
  3148. .parent_hws = (const struct clk_hw*[]){
  3149. &pcnoc_bfdcd_clk_src.clkr.hw,
  3150. },
  3151. .num_parents = 1,
  3152. .flags = CLK_SET_RATE_PARENT,
  3153. .ops = &clk_branch2_ops,
  3154. },
  3155. },
  3156. };
  3157. static struct clk_branch gcc_usb_fs_ic_clk = {
  3158. .halt_reg = 0x3f030,
  3159. .clkr = {
  3160. .enable_reg = 0x3f030,
  3161. .enable_mask = BIT(0),
  3162. .hw.init = &(struct clk_init_data){
  3163. .name = "gcc_usb_fs_ic_clk",
  3164. .parent_hws = (const struct clk_hw*[]){
  3165. &usb_fs_ic_clk_src.clkr.hw,
  3166. },
  3167. .num_parents = 1,
  3168. .flags = CLK_SET_RATE_PARENT,
  3169. .ops = &clk_branch2_ops,
  3170. },
  3171. },
  3172. };
  3173. static struct clk_branch gcc_usb_fs_system_clk = {
  3174. .halt_reg = 0x3f004,
  3175. .clkr = {
  3176. .enable_reg = 0x3f004,
  3177. .enable_mask = BIT(0),
  3178. .hw.init = &(struct clk_init_data){
  3179. .name = "gcc_usb_fs_system_clk",
  3180. .parent_hws = (const struct clk_hw*[]){
  3181. &usb_fs_system_clk_src.clkr.hw,
  3182. },
  3183. .num_parents = 1,
  3184. .flags = CLK_SET_RATE_PARENT,
  3185. .ops = &clk_branch2_ops,
  3186. },
  3187. },
  3188. };
  3189. static struct clk_branch gcc_usb_hs_ahb_clk = {
  3190. .halt_reg = 0x41008,
  3191. .clkr = {
  3192. .enable_reg = 0x41008,
  3193. .enable_mask = BIT(0),
  3194. .hw.init = &(struct clk_init_data){
  3195. .name = "gcc_usb_hs_ahb_clk",
  3196. .parent_hws = (const struct clk_hw*[]){
  3197. &pcnoc_bfdcd_clk_src.clkr.hw,
  3198. },
  3199. .num_parents = 1,
  3200. .flags = CLK_SET_RATE_PARENT,
  3201. .ops = &clk_branch2_ops,
  3202. },
  3203. },
  3204. };
  3205. static struct clk_branch gcc_usb_hs_system_clk = {
  3206. .halt_reg = 0x41004,
  3207. .clkr = {
  3208. .enable_reg = 0x41004,
  3209. .enable_mask = BIT(0),
  3210. .hw.init = &(struct clk_init_data){
  3211. .name = "gcc_usb_hs_system_clk",
  3212. .parent_hws = (const struct clk_hw*[]){
  3213. &usb_hs_system_clk_src.clkr.hw,
  3214. },
  3215. .num_parents = 1,
  3216. .flags = CLK_SET_RATE_PARENT,
  3217. .ops = &clk_branch2_ops,
  3218. },
  3219. },
  3220. };
  3221. static struct clk_branch gcc_venus0_ahb_clk = {
  3222. .halt_reg = 0x4c020,
  3223. .clkr = {
  3224. .enable_reg = 0x4c020,
  3225. .enable_mask = BIT(0),
  3226. .hw.init = &(struct clk_init_data){
  3227. .name = "gcc_venus0_ahb_clk",
  3228. .parent_hws = (const struct clk_hw*[]){
  3229. &pcnoc_bfdcd_clk_src.clkr.hw,
  3230. },
  3231. .num_parents = 1,
  3232. .flags = CLK_SET_RATE_PARENT,
  3233. .ops = &clk_branch2_ops,
  3234. },
  3235. },
  3236. };
  3237. static struct clk_branch gcc_venus0_axi_clk = {
  3238. .halt_reg = 0x4c024,
  3239. .clkr = {
  3240. .enable_reg = 0x4c024,
  3241. .enable_mask = BIT(0),
  3242. .hw.init = &(struct clk_init_data){
  3243. .name = "gcc_venus0_axi_clk",
  3244. .parent_hws = (const struct clk_hw*[]){
  3245. &system_mm_noc_bfdcd_clk_src.clkr.hw,
  3246. },
  3247. .num_parents = 1,
  3248. .flags = CLK_SET_RATE_PARENT,
  3249. .ops = &clk_branch2_ops,
  3250. },
  3251. },
  3252. };
  3253. static struct clk_branch gcc_venus0_vcodec0_clk = {
  3254. .halt_reg = 0x4c01c,
  3255. .clkr = {
  3256. .enable_reg = 0x4c01c,
  3257. .enable_mask = BIT(0),
  3258. .hw.init = &(struct clk_init_data){
  3259. .name = "gcc_venus0_vcodec0_clk",
  3260. .parent_hws = (const struct clk_hw*[]){
  3261. &vcodec0_clk_src.clkr.hw,
  3262. },
  3263. .num_parents = 1,
  3264. .flags = CLK_SET_RATE_PARENT,
  3265. .ops = &clk_branch2_ops,
  3266. },
  3267. },
  3268. };
  3269. static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
  3270. .halt_reg = 0x4c02c,
  3271. .clkr = {
  3272. .enable_reg = 0x4c02c,
  3273. .enable_mask = BIT(0),
  3274. .hw.init = &(struct clk_init_data){
  3275. .name = "gcc_venus0_core0_vcodec0_clk",
  3276. .parent_hws = (const struct clk_hw*[]){
  3277. &vcodec0_clk_src.clkr.hw,
  3278. },
  3279. .num_parents = 1,
  3280. .flags = CLK_SET_RATE_PARENT,
  3281. .ops = &clk_branch2_ops,
  3282. },
  3283. },
  3284. };
  3285. static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
  3286. .halt_reg = 0x4c034,
  3287. .clkr = {
  3288. .enable_reg = 0x4c034,
  3289. .enable_mask = BIT(0),
  3290. .hw.init = &(struct clk_init_data){
  3291. .name = "gcc_venus0_core1_vcodec0_clk",
  3292. .parent_hws = (const struct clk_hw*[]){
  3293. &vcodec0_clk_src.clkr.hw,
  3294. },
  3295. .num_parents = 1,
  3296. .flags = CLK_SET_RATE_PARENT,
  3297. .ops = &clk_branch2_ops,
  3298. },
  3299. },
  3300. };
  3301. static struct clk_branch gcc_oxili_timer_clk = {
  3302. .halt_reg = 0x59040,
  3303. .clkr = {
  3304. .enable_reg = 0x59040,
  3305. .enable_mask = BIT(0),
  3306. .hw.init = &(struct clk_init_data){
  3307. .name = "gcc_oxili_timer_clk",
  3308. .ops = &clk_branch2_ops,
  3309. },
  3310. },
  3311. };
  3312. static struct gdsc venus_gdsc = {
  3313. .gdscr = 0x4c018,
  3314. .pd = {
  3315. .name = "venus",
  3316. },
  3317. .pwrsts = PWRSTS_OFF_ON,
  3318. };
  3319. static struct gdsc mdss_gdsc = {
  3320. .gdscr = 0x4d078,
  3321. .pd = {
  3322. .name = "mdss",
  3323. },
  3324. .pwrsts = PWRSTS_OFF_ON,
  3325. };
  3326. static struct gdsc jpeg_gdsc = {
  3327. .gdscr = 0x5701c,
  3328. .pd = {
  3329. .name = "jpeg",
  3330. },
  3331. .pwrsts = PWRSTS_OFF_ON,
  3332. };
  3333. static struct gdsc vfe_gdsc = {
  3334. .gdscr = 0x58034,
  3335. .pd = {
  3336. .name = "vfe",
  3337. },
  3338. .pwrsts = PWRSTS_OFF_ON,
  3339. };
  3340. static struct gdsc oxili_gdsc = {
  3341. .gdscr = 0x5901c,
  3342. .pd = {
  3343. .name = "oxili",
  3344. },
  3345. .pwrsts = PWRSTS_OFF_ON,
  3346. };
  3347. static struct gdsc venus_core0_gdsc = {
  3348. .gdscr = 0x4c028,
  3349. .pd = {
  3350. .name = "venus_core0",
  3351. },
  3352. .pwrsts = PWRSTS_OFF_ON,
  3353. };
  3354. static struct gdsc venus_core1_gdsc = {
  3355. .gdscr = 0x4c030,
  3356. .pd = {
  3357. .name = "venus_core1",
  3358. },
  3359. .pwrsts = PWRSTS_OFF_ON,
  3360. };
  3361. static struct clk_regmap *gcc_msm8939_clocks[] = {
  3362. [GPLL0] = &gpll0.clkr,
  3363. [GPLL0_VOTE] = &gpll0_vote,
  3364. [BIMC_PLL] = &bimc_pll.clkr,
  3365. [BIMC_PLL_VOTE] = &bimc_pll_vote,
  3366. [GPLL1] = &gpll1.clkr,
  3367. [GPLL1_VOTE] = &gpll1_vote,
  3368. [GPLL2] = &gpll2.clkr,
  3369. [GPLL2_VOTE] = &gpll2_vote,
  3370. [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
  3371. [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
  3372. [SYSTEM_MM_NOC_BFDCD_CLK_SRC] = &system_mm_noc_bfdcd_clk_src.clkr,
  3373. [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
  3374. [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
  3375. [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
  3376. [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
  3377. [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
  3378. [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
  3379. [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
  3380. [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
  3381. [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
  3382. [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
  3383. [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
  3384. [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
  3385. [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
  3386. [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
  3387. [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
  3388. [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
  3389. [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
  3390. [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
  3391. [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
  3392. [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
  3393. [CCI_CLK_SRC] = &cci_clk_src.clkr,
  3394. [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
  3395. [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
  3396. [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
  3397. [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
  3398. [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
  3399. [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
  3400. [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
  3401. [CPP_CLK_SRC] = &cpp_clk_src.clkr,
  3402. [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
  3403. [GP1_CLK_SRC] = &gp1_clk_src.clkr,
  3404. [GP2_CLK_SRC] = &gp2_clk_src.clkr,
  3405. [GP3_CLK_SRC] = &gp3_clk_src.clkr,
  3406. [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
  3407. [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
  3408. [MDP_CLK_SRC] = &mdp_clk_src.clkr,
  3409. [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
  3410. [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
  3411. [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
  3412. [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
  3413. [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
  3414. [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
  3415. [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
  3416. [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
  3417. [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
  3418. [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
  3419. [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
  3420. [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
  3421. [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
  3422. [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
  3423. [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
  3424. [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
  3425. [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
  3426. [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
  3427. [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
  3428. [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
  3429. [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
  3430. [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
  3431. [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
  3432. [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
  3433. [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
  3434. [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
  3435. [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
  3436. [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
  3437. [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
  3438. [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
  3439. [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
  3440. [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
  3441. [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
  3442. [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
  3443. [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
  3444. [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
  3445. [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
  3446. [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
  3447. [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
  3448. [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
  3449. [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
  3450. [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
  3451. [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
  3452. [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
  3453. [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
  3454. [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
  3455. [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
  3456. [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
  3457. [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
  3458. [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
  3459. [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
  3460. [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
  3461. [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
  3462. [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
  3463. [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
  3464. [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
  3465. [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
  3466. [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
  3467. [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
  3468. [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
  3469. [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
  3470. [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
  3471. [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
  3472. [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
  3473. [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
  3474. [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
  3475. [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
  3476. [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
  3477. [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
  3478. [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
  3479. [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
  3480. [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
  3481. [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
  3482. [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
  3483. [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
  3484. [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
  3485. [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
  3486. [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
  3487. [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
  3488. [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
  3489. [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
  3490. [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
  3491. [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
  3492. [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
  3493. [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
  3494. [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
  3495. [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
  3496. [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
  3497. [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
  3498. [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
  3499. [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
  3500. [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
  3501. [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
  3502. [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
  3503. [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
  3504. [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
  3505. [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
  3506. [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
  3507. [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
  3508. [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
  3509. [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
  3510. [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
  3511. [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
  3512. [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
  3513. [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
  3514. [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
  3515. [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
  3516. [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
  3517. [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
  3518. [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
  3519. [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
  3520. [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
  3521. [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
  3522. [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
  3523. [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
  3524. [GPLL3] = &gpll3.clkr,
  3525. [GPLL3_VOTE] = &gpll3_vote,
  3526. [GPLL4] = &gpll4.clkr,
  3527. [GPLL4_VOTE] = &gpll4_vote,
  3528. [GPLL5] = &gpll5.clkr,
  3529. [GPLL5_VOTE] = &gpll5_vote,
  3530. [GPLL6] = &gpll6.clkr,
  3531. [GPLL6_VOTE] = &gpll6_vote,
  3532. [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
  3533. [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
  3534. [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
  3535. [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
  3536. [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
  3537. [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
  3538. [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
  3539. [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
  3540. [GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,
  3541. [USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,
  3542. [USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,
  3543. [GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,
  3544. [GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,
  3545. [GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,
  3546. [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
  3547. [GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,
  3548. [GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
  3549. };
  3550. static struct gdsc *gcc_msm8939_gdscs[] = {
  3551. [VENUS_GDSC] = &venus_gdsc,
  3552. [MDSS_GDSC] = &mdss_gdsc,
  3553. [JPEG_GDSC] = &jpeg_gdsc,
  3554. [VFE_GDSC] = &vfe_gdsc,
  3555. [OXILI_GDSC] = &oxili_gdsc,
  3556. [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
  3557. [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
  3558. };
  3559. static const struct qcom_reset_map gcc_msm8939_resets[] = {
  3560. [GCC_BLSP1_BCR] = { 0x01000 },
  3561. [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
  3562. [GCC_BLSP1_UART1_BCR] = { 0x02038 },
  3563. [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
  3564. [GCC_BLSP1_UART2_BCR] = { 0x03028 },
  3565. [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
  3566. [GCC_BLSP1_UART3_BCR] = { 0x04038 },
  3567. [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
  3568. [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
  3569. [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
  3570. [GCC_IMEM_BCR] = { 0x0e000 },
  3571. [GCC_SMMU_BCR] = { 0x12000 },
  3572. [GCC_APSS_TCU_BCR] = { 0x12050 },
  3573. [GCC_SMMU_XPU_BCR] = { 0x12054 },
  3574. [GCC_PCNOC_TBU_BCR] = { 0x12058 },
  3575. [GCC_PRNG_BCR] = { 0x13000 },
  3576. [GCC_BOOT_ROM_BCR] = { 0x13008 },
  3577. [GCC_CRYPTO_BCR] = { 0x16000 },
  3578. [GCC_SEC_CTRL_BCR] = { 0x1a000 },
  3579. [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
  3580. [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
  3581. [GCC_DEHR_BCR] = { 0x1f000 },
  3582. [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
  3583. [GCC_PCNOC_BCR] = { 0x27018 },
  3584. [GCC_TCSR_BCR] = { 0x28000 },
  3585. [GCC_QDSS_BCR] = { 0x29000 },
  3586. [GCC_DCD_BCR] = { 0x2a000 },
  3587. [GCC_MSG_RAM_BCR] = { 0x2b000 },
  3588. [GCC_MPM_BCR] = { 0x2c000 },
  3589. [GCC_SPMI_BCR] = { 0x2e000 },
  3590. [GCC_SPDM_BCR] = { 0x2f000 },
  3591. [GCC_MM_SPDM_BCR] = { 0x2f024 },
  3592. [GCC_BIMC_BCR] = { 0x31000 },
  3593. [GCC_RBCPR_BCR] = { 0x33000 },
  3594. [GCC_TLMM_BCR] = { 0x34000 },
  3595. [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
  3596. [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
  3597. [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
  3598. [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
  3599. [GCC_USB_FS_BCR] = { 0x3f000 },
  3600. [GCC_USB_HS_BCR] = { 0x41000 },
  3601. [GCC_USB2A_PHY_BCR] = { 0x41028 },
  3602. [GCC_SDCC1_BCR] = { 0x42000 },
  3603. [GCC_SDCC2_BCR] = { 0x43000 },
  3604. [GCC_PDM_BCR] = { 0x44000 },
  3605. [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
  3606. [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
  3607. [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
  3608. [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
  3609. [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
  3610. [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
  3611. [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
  3612. [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
  3613. [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
  3614. [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
  3615. [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
  3616. [GCC_MMSS_BCR] = { 0x4b000 },
  3617. [GCC_VENUS0_BCR] = { 0x4c014 },
  3618. [GCC_MDSS_BCR] = { 0x4d074 },
  3619. [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
  3620. [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
  3621. [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
  3622. [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
  3623. [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
  3624. [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
  3625. [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
  3626. [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
  3627. [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
  3628. [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
  3629. [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
  3630. [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
  3631. [GCC_CAMSS_CCI_BCR] = { 0x51014 },
  3632. [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
  3633. [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
  3634. [GCC_CAMSS_GP0_BCR] = { 0x54014 },
  3635. [GCC_CAMSS_GP1_BCR] = { 0x55014 },
  3636. [GCC_CAMSS_TOP_BCR] = { 0x56000 },
  3637. [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
  3638. [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
  3639. [GCC_CAMSS_VFE_BCR] = { 0x58030 },
  3640. [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
  3641. [GCC_OXILI_BCR] = { 0x59018 },
  3642. [GCC_GMEM_BCR] = { 0x5902c },
  3643. [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
  3644. [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
  3645. [GCC_MDP_TBU_BCR] = { 0x62000 },
  3646. [GCC_GFX_TBU_BCR] = { 0x63000 },
  3647. [GCC_GFX_TCU_BCR] = { 0x64000 },
  3648. [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
  3649. [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
  3650. [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
  3651. [GCC_GTCU_AHB_BCR] = { 0x68000 },
  3652. [GCC_SMMU_CFG_BCR] = { 0x69000 },
  3653. [GCC_VFE_TBU_BCR] = { 0x6a000 },
  3654. [GCC_VENUS_TBU_BCR] = { 0x6b000 },
  3655. [GCC_JPEG_TBU_BCR] = { 0x6c000 },
  3656. [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
  3657. [GCC_CPP_TBU_BCR] = { 0x6e000 },
  3658. [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
  3659. [GCC_SMMU_CATS_BCR] = { 0x7c000 },
  3660. };
  3661. static const struct regmap_config gcc_msm8939_regmap_config = {
  3662. .reg_bits = 32,
  3663. .reg_stride = 4,
  3664. .val_bits = 32,
  3665. .max_register = 0x80000,
  3666. .fast_io = true,
  3667. };
  3668. static const struct qcom_cc_desc gcc_msm8939_desc = {
  3669. .config = &gcc_msm8939_regmap_config,
  3670. .clks = gcc_msm8939_clocks,
  3671. .num_clks = ARRAY_SIZE(gcc_msm8939_clocks),
  3672. .resets = gcc_msm8939_resets,
  3673. .num_resets = ARRAY_SIZE(gcc_msm8939_resets),
  3674. .gdscs = gcc_msm8939_gdscs,
  3675. .num_gdscs = ARRAY_SIZE(gcc_msm8939_gdscs),
  3676. };
  3677. static const struct of_device_id gcc_msm8939_match_table[] = {
  3678. { .compatible = "qcom,gcc-msm8939" },
  3679. { }
  3680. };
  3681. MODULE_DEVICE_TABLE(of, gcc_msm8939_match_table);
  3682. static int gcc_msm8939_probe(struct platform_device *pdev)
  3683. {
  3684. struct regmap *regmap;
  3685. regmap = qcom_cc_map(pdev, &gcc_msm8939_desc);
  3686. if (IS_ERR(regmap))
  3687. return PTR_ERR(regmap);
  3688. clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
  3689. clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
  3690. return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap);
  3691. }
  3692. static struct platform_driver gcc_msm8939_driver = {
  3693. .probe = gcc_msm8939_probe,
  3694. .driver = {
  3695. .name = "gcc-msm8939",
  3696. .of_match_table = gcc_msm8939_match_table,
  3697. },
  3698. };
  3699. static int __init gcc_msm8939_init(void)
  3700. {
  3701. return platform_driver_register(&gcc_msm8939_driver);
  3702. }
  3703. core_initcall(gcc_msm8939_init);
  3704. static void __exit gcc_msm8939_exit(void)
  3705. {
  3706. platform_driver_unregister(&gcc_msm8939_driver);
  3707. }
  3708. module_exit(gcc_msm8939_exit);
  3709. MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver");
  3710. MODULE_LICENSE("GPL v2");