a7-pll.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Qualcomm A7 PLL driver
  4. *
  5. * Copyright (c) 2020, Linaro Limited
  6. * Author: Manivannan Sadhasivam <[email protected]>
  7. */
  8. #include <linux/clk-provider.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/regmap.h>
  12. #include "clk-alpha-pll.h"
  13. #define LUCID_PLL_OFF_L_VAL 0x04
  14. static const struct pll_vco lucid_vco[] = {
  15. { 249600000, 2000000000, 0 },
  16. };
  17. static struct clk_alpha_pll a7pll = {
  18. .offset = 0x100,
  19. .vco_table = lucid_vco,
  20. .num_vco = ARRAY_SIZE(lucid_vco),
  21. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  22. .clkr = {
  23. .hw.init = &(struct clk_init_data){
  24. .name = "a7pll",
  25. .parent_data = &(const struct clk_parent_data){
  26. .fw_name = "bi_tcxo",
  27. },
  28. .num_parents = 1,
  29. .ops = &clk_alpha_pll_lucid_ops,
  30. },
  31. },
  32. };
  33. static const struct alpha_pll_config a7pll_config = {
  34. .l = 0x39,
  35. .config_ctl_val = 0x20485699,
  36. .config_ctl_hi_val = 0x2261,
  37. .config_ctl_hi1_val = 0x029A699C,
  38. .user_ctl_val = 0x1,
  39. .user_ctl_hi_val = 0x805,
  40. };
  41. static const struct regmap_config a7pll_regmap_config = {
  42. .reg_bits = 32,
  43. .reg_stride = 4,
  44. .val_bits = 32,
  45. .max_register = 0x1000,
  46. .fast_io = true,
  47. };
  48. static int qcom_a7pll_probe(struct platform_device *pdev)
  49. {
  50. struct device *dev = &pdev->dev;
  51. struct regmap *regmap;
  52. void __iomem *base;
  53. u32 l_val;
  54. int ret;
  55. base = devm_platform_ioremap_resource(pdev, 0);
  56. if (IS_ERR(base))
  57. return PTR_ERR(base);
  58. regmap = devm_regmap_init_mmio(dev, base, &a7pll_regmap_config);
  59. if (IS_ERR(regmap))
  60. return PTR_ERR(regmap);
  61. /* Configure PLL only if the l_val is zero */
  62. regmap_read(regmap, a7pll.offset + LUCID_PLL_OFF_L_VAL, &l_val);
  63. if (!l_val)
  64. clk_lucid_pll_configure(&a7pll, regmap, &a7pll_config);
  65. ret = devm_clk_register_regmap(dev, &a7pll.clkr);
  66. if (ret)
  67. return ret;
  68. return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
  69. &a7pll.clkr.hw);
  70. }
  71. static const struct of_device_id qcom_a7pll_match_table[] = {
  72. { .compatible = "qcom,sdx55-a7pll" },
  73. { }
  74. };
  75. MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table);
  76. static struct platform_driver qcom_a7pll_driver = {
  77. .probe = qcom_a7pll_probe,
  78. .driver = {
  79. .name = "qcom-a7pll",
  80. .of_match_table = qcom_a7pll_match_table,
  81. },
  82. };
  83. module_platform_driver(qcom_a7pll_driver);
  84. MODULE_DESCRIPTION("Qualcomm A7 PLL Driver");
  85. MODULE_LICENSE("GPL v2");