clk-pxa25x.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Marvell PXA25x family clocks
  4. *
  5. * Copyright (C) 2014 Robert Jarzmik
  6. *
  7. * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
  8. *
  9. * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
  10. * should go away.
  11. */
  12. #include <linux/clk-provider.h>
  13. #include <linux/clk.h>
  14. #include <linux/clkdev.h>
  15. #include <linux/io.h>
  16. #include <linux/of.h>
  17. #include <linux/soc/pxa/smemc.h>
  18. #include <dt-bindings/clock/pxa-clock.h>
  19. #include "clk-pxa.h"
  20. #include "clk-pxa2xx.h"
  21. #define KHz 1000
  22. #define MHz (1000 * 1000)
  23. enum {
  24. PXA_CORE_RUN = 0,
  25. PXA_CORE_TURBO,
  26. };
  27. #define PXA25x_CLKCFG(T) \
  28. (CLKCFG_FCS | \
  29. ((T) ? CLKCFG_TURBO : 0))
  30. #define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L)
  31. /* Define the refresh period in mSec for the SDRAM and the number of rows */
  32. #define SDRAM_TREF 64 /* standard 64ms SDRAM */
  33. /*
  34. * Various clock factors driven by the CCCR register.
  35. */
  36. static void __iomem *clk_regs;
  37. /* Crystal Frequency to Memory Frequency Multiplier (L) */
  38. static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
  39. /* Memory Frequency to Run Mode Frequency Multiplier (M) */
  40. static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
  41. /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
  42. /* Note: we store the value N * 2 here. */
  43. static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
  44. static const char * const get_freq_khz[] = {
  45. "core", "run", "cpll", "memory"
  46. };
  47. static u32 mdrefr_dri(unsigned int freq_khz)
  48. {
  49. u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();
  50. return interval / 32;
  51. }
  52. /*
  53. * Get the clock frequency as reflected by CCCR and the turbo flag.
  54. * We assume these values have been applied via a fcs.
  55. * If info is not 0 we also display the current settings.
  56. */
  57. unsigned int pxa25x_get_clk_frequency_khz(int info)
  58. {
  59. struct clk *clk;
  60. unsigned long clks[5];
  61. int i;
  62. for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
  63. clk = clk_get(NULL, get_freq_khz[i]);
  64. if (IS_ERR(clk)) {
  65. clks[i] = 0;
  66. } else {
  67. clks[i] = clk_get_rate(clk);
  68. clk_put(clk);
  69. }
  70. }
  71. if (info) {
  72. pr_info("Run Mode clock: %ld.%02ldMHz\n",
  73. clks[1] / 1000000, (clks[1] % 1000000) / 10000);
  74. pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
  75. clks[2] / 1000000, (clks[2] % 1000000) / 10000);
  76. pr_info("Memory clock: %ld.%02ldMHz\n",
  77. clks[3] / 1000000, (clks[3] % 1000000) / 10000);
  78. }
  79. return (unsigned int)clks[0] / KHz;
  80. }
  81. static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
  82. unsigned long parent_rate)
  83. {
  84. unsigned long cccr = readl(clk_regs + CCCR);
  85. unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
  86. return parent_rate / m;
  87. }
  88. PARENTS(clk_pxa25x_memory) = { "run" };
  89. RATE_RO_OPS(clk_pxa25x_memory, "memory");
  90. PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
  91. PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
  92. PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
  93. #define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \
  94. bit, is_lp, flags) \
  95. PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \
  96. is_lp, CKEN, CKEN_ ## bit, flags)
  97. #define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
  98. PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \
  99. div_hp, bit, NULL, 0)
  100. #define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
  101. PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp, \
  102. div_hp, bit, NULL, 0)
  103. #define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
  104. PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp, \
  105. div_hp, bit, NULL, 0)
  106. #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
  107. PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
  108. CKEN, CKEN_ ## bit, 0)
  109. #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
  110. PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
  111. CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
  112. static struct desc_clk_cken pxa25x_clocks[] __initdata = {
  113. PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
  114. PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
  115. PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
  116. PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
  117. PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
  118. PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
  119. PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
  120. PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
  121. PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
  122. PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
  123. PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
  124. PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
  125. PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
  126. PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
  127. PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),
  128. PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
  129. PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
  130. clk_pxa25x_memory_parents, 0),
  131. };
  132. /*
  133. * In this table, PXA25x_CCCR(N2, M, L) has the following meaning, where :
  134. * - freq_cpll = n * m * L * 3.6864 MHz
  135. * - n = N2 / 2
  136. * - m = 2^(M - 1), where 1 <= M <= 3
  137. * - l = L_clk_mult[L], ie. { 0, 27, 32, 36, 40, 45, 0, }[L]
  138. */
  139. static struct pxa2xx_freq pxa25x_freqs[] = {
  140. /* CPU MEMBUS CCCR DIV2 CCLKCFG */
  141. { 99532800, 99500, PXA25x_CCCR(2, 1, 1), 1, PXA25x_CLKCFG(1)},
  142. {199065600, 99500, PXA25x_CCCR(4, 1, 1), 0, PXA25x_CLKCFG(1)},
  143. {298598400, 99500, PXA25x_CCCR(3, 2, 1), 0, PXA25x_CLKCFG(1)},
  144. {398131200, 99500, PXA25x_CCCR(4, 2, 1), 0, PXA25x_CLKCFG(1)},
  145. };
  146. static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
  147. {
  148. unsigned long clkcfg;
  149. unsigned int t;
  150. asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
  151. t = clkcfg & (1 << 0);
  152. if (t)
  153. return PXA_CORE_TURBO;
  154. return PXA_CORE_RUN;
  155. }
  156. static int clk_pxa25x_core_set_parent(struct clk_hw *hw, u8 index)
  157. {
  158. if (index > PXA_CORE_TURBO)
  159. return -EINVAL;
  160. pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
  161. return 0;
  162. }
  163. static int clk_pxa25x_core_determine_rate(struct clk_hw *hw,
  164. struct clk_rate_request *req)
  165. {
  166. return __clk_mux_determine_rate(hw, req);
  167. }
  168. PARENTS(clk_pxa25x_core) = { "run", "cpll" };
  169. MUX_OPS(clk_pxa25x_core, "core", CLK_SET_RATE_PARENT);
  170. static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
  171. unsigned long parent_rate)
  172. {
  173. unsigned long cccr = readl(clk_regs + CCCR);
  174. unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
  175. return (parent_rate / n2) * 2;
  176. }
  177. PARENTS(clk_pxa25x_run) = { "cpll" };
  178. RATE_RO_OPS(clk_pxa25x_run, "run");
  179. static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
  180. unsigned long parent_rate)
  181. {
  182. unsigned long clkcfg, cccr = readl(clk_regs + CCCR);
  183. unsigned int l, m, n2, t;
  184. asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
  185. t = clkcfg & (1 << 0);
  186. l = L_clk_mult[(cccr >> 0) & 0x1f];
  187. m = M_clk_mult[(cccr >> 5) & 0x03];
  188. n2 = N2_clk_mult[(cccr >> 7) & 0x07];
  189. return m * l * n2 * parent_rate / 2;
  190. }
  191. static int clk_pxa25x_cpll_determine_rate(struct clk_hw *hw,
  192. struct clk_rate_request *req)
  193. {
  194. return pxa2xx_determine_rate(req, pxa25x_freqs,
  195. ARRAY_SIZE(pxa25x_freqs));
  196. }
  197. static int clk_pxa25x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
  198. unsigned long parent_rate)
  199. {
  200. int i;
  201. pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
  202. for (i = 0; i < ARRAY_SIZE(pxa25x_freqs); i++)
  203. if (pxa25x_freqs[i].cpll == rate)
  204. break;
  205. if (i >= ARRAY_SIZE(pxa25x_freqs))
  206. return -EINVAL;
  207. pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, clk_regs + CCCR);
  208. return 0;
  209. }
  210. PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
  211. RATE_OPS(clk_pxa25x_cpll, "cpll");
  212. static void __init pxa25x_register_core(void)
  213. {
  214. clkdev_pxa_register(CLK_NONE, "cpll", NULL,
  215. clk_register_clk_pxa25x_cpll());
  216. clkdev_pxa_register(CLK_NONE, "run", NULL,
  217. clk_register_clk_pxa25x_run());
  218. clkdev_pxa_register(CLK_CORE, "core", NULL,
  219. clk_register_clk_pxa25x_core());
  220. }
  221. static void __init pxa25x_register_plls(void)
  222. {
  223. clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
  224. CLK_GET_RATE_NOCACHE, 3686400);
  225. clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
  226. clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
  227. CLK_GET_RATE_NOCACHE,
  228. 32768));
  229. clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
  230. clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
  231. 0, 26, 1);
  232. clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
  233. 0, 40, 1);
  234. }
  235. static void __init pxa25x_base_clocks_init(void)
  236. {
  237. pxa25x_register_plls();
  238. pxa25x_register_core();
  239. clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
  240. clk_register_clk_pxa25x_memory());
  241. }
  242. #define DUMMY_CLK(_con_id, _dev_id, _parent) \
  243. { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
  244. struct dummy_clk {
  245. const char *con_id;
  246. const char *dev_id;
  247. const char *parent;
  248. };
  249. static struct dummy_clk dummy_clks[] __initdata = {
  250. DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
  251. DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
  252. DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
  253. DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
  254. DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
  255. DUMMY_CLK("OSTIMER0", NULL, "osc_3_6864mhz"),
  256. DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
  257. };
  258. static void __init pxa25x_dummy_clocks_init(void)
  259. {
  260. struct clk *clk;
  261. struct dummy_clk *d;
  262. const char *name;
  263. int i;
  264. /*
  265. * All pinctrl logic has been wiped out of the clock driver, especially
  266. * for gpio11 and gpio12 outputs. Machine code should ensure proper pin
  267. * control (ie. pxa2xx_mfp_config() invocation).
  268. */
  269. for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
  270. d = &dummy_clks[i];
  271. name = d->dev_id ? d->dev_id : d->con_id;
  272. clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
  273. clk_register_clkdev(clk, d->con_id, d->dev_id);
  274. }
  275. }
  276. int __init pxa25x_clocks_init(void __iomem *regs)
  277. {
  278. clk_regs = regs;
  279. pxa25x_base_clocks_init();
  280. pxa25x_dummy_clocks_init();
  281. return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks), clk_regs);
  282. }
  283. static void __init pxa25x_dt_clocks_init(struct device_node *np)
  284. {
  285. pxa25x_clocks_init(ioremap(0x41300000ul, 0x10));
  286. clk_pxa_dt_common_init(np);
  287. }
  288. CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
  289. pxa25x_dt_clocks_init);