clk-msc313-mpll.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MStar MSC313 MPLL driver
  4. *
  5. * Copyright (C) 2020 Daniel Palmer <[email protected]>
  6. */
  7. #include <linux/platform_device.h>
  8. #include <linux/of_address.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/regmap.h>
  11. #define REG_CONFIG1 0x8
  12. #define REG_CONFIG2 0xc
  13. static const struct regmap_config msc313_mpll_regmap_config = {
  14. .reg_bits = 16,
  15. .val_bits = 16,
  16. .reg_stride = 4,
  17. };
  18. static const struct reg_field config1_loop_div_first = REG_FIELD(REG_CONFIG1, 8, 9);
  19. static const struct reg_field config1_input_div_first = REG_FIELD(REG_CONFIG1, 4, 5);
  20. static const struct reg_field config2_output_div_first = REG_FIELD(REG_CONFIG2, 12, 13);
  21. static const struct reg_field config2_loop_div_second = REG_FIELD(REG_CONFIG2, 0, 7);
  22. static const unsigned int output_dividers[] = {
  23. 2, 3, 4, 5, 6, 7, 10
  24. };
  25. #define NUMOUTPUTS (ARRAY_SIZE(output_dividers) + 1)
  26. struct msc313_mpll {
  27. struct clk_hw clk_hw;
  28. struct regmap_field *input_div;
  29. struct regmap_field *loop_div_first;
  30. struct regmap_field *loop_div_second;
  31. struct regmap_field *output_div;
  32. struct clk_hw_onecell_data *clk_data;
  33. };
  34. #define to_mpll(_hw) container_of(_hw, struct msc313_mpll, clk_hw)
  35. static unsigned long msc313_mpll_recalc_rate(struct clk_hw *hw,
  36. unsigned long parent_rate)
  37. {
  38. struct msc313_mpll *mpll = to_mpll(hw);
  39. unsigned int input_div, output_div, loop_first, loop_second;
  40. unsigned long output_rate;
  41. regmap_field_read(mpll->input_div, &input_div);
  42. regmap_field_read(mpll->output_div, &output_div);
  43. regmap_field_read(mpll->loop_div_first, &loop_first);
  44. regmap_field_read(mpll->loop_div_second, &loop_second);
  45. output_rate = parent_rate / (1 << input_div);
  46. output_rate *= (1 << loop_first) * max(loop_second, 1U);
  47. output_rate /= max(output_div, 1U);
  48. return output_rate;
  49. }
  50. static const struct clk_ops msc313_mpll_ops = {
  51. .recalc_rate = msc313_mpll_recalc_rate,
  52. };
  53. static const struct clk_parent_data mpll_parent = {
  54. .index = 0,
  55. };
  56. static int msc313_mpll_probe(struct platform_device *pdev)
  57. {
  58. void __iomem *base;
  59. struct msc313_mpll *mpll;
  60. struct clk_init_data clk_init = { };
  61. struct device *dev = &pdev->dev;
  62. struct regmap *regmap;
  63. char *outputname;
  64. struct clk_hw *divhw;
  65. int ret, i;
  66. mpll = devm_kzalloc(dev, sizeof(*mpll), GFP_KERNEL);
  67. if (!mpll)
  68. return -ENOMEM;
  69. base = devm_platform_ioremap_resource(pdev, 0);
  70. if (IS_ERR(base))
  71. return PTR_ERR(base);
  72. regmap = devm_regmap_init_mmio(dev, base, &msc313_mpll_regmap_config);
  73. if (IS_ERR(regmap))
  74. return PTR_ERR(regmap);
  75. mpll->input_div = devm_regmap_field_alloc(dev, regmap, config1_input_div_first);
  76. if (IS_ERR(mpll->input_div))
  77. return PTR_ERR(mpll->input_div);
  78. mpll->output_div = devm_regmap_field_alloc(dev, regmap, config2_output_div_first);
  79. if (IS_ERR(mpll->output_div))
  80. return PTR_ERR(mpll->output_div);
  81. mpll->loop_div_first = devm_regmap_field_alloc(dev, regmap, config1_loop_div_first);
  82. if (IS_ERR(mpll->loop_div_first))
  83. return PTR_ERR(mpll->loop_div_first);
  84. mpll->loop_div_second = devm_regmap_field_alloc(dev, regmap, config2_loop_div_second);
  85. if (IS_ERR(mpll->loop_div_second))
  86. return PTR_ERR(mpll->loop_div_second);
  87. mpll->clk_data = devm_kzalloc(dev, struct_size(mpll->clk_data, hws,
  88. ARRAY_SIZE(output_dividers)), GFP_KERNEL);
  89. if (!mpll->clk_data)
  90. return -ENOMEM;
  91. clk_init.name = dev_name(dev);
  92. clk_init.ops = &msc313_mpll_ops;
  93. clk_init.parent_data = &mpll_parent;
  94. clk_init.num_parents = 1;
  95. mpll->clk_hw.init = &clk_init;
  96. ret = devm_clk_hw_register(dev, &mpll->clk_hw);
  97. if (ret)
  98. return ret;
  99. mpll->clk_data->num = NUMOUTPUTS;
  100. mpll->clk_data->hws[0] = &mpll->clk_hw;
  101. for (i = 0; i < ARRAY_SIZE(output_dividers); i++) {
  102. outputname = devm_kasprintf(dev, GFP_KERNEL, "%s_div_%u",
  103. clk_init.name, output_dividers[i]);
  104. if (!outputname)
  105. return -ENOMEM;
  106. divhw = devm_clk_hw_register_fixed_factor(dev, outputname,
  107. clk_init.name, 0, 1, output_dividers[i]);
  108. if (IS_ERR(divhw))
  109. return PTR_ERR(divhw);
  110. mpll->clk_data->hws[i + 1] = divhw;
  111. }
  112. platform_set_drvdata(pdev, mpll);
  113. return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
  114. mpll->clk_data);
  115. }
  116. static const struct of_device_id msc313_mpll_of_match[] = {
  117. { .compatible = "mstar,msc313-mpll", },
  118. {}
  119. };
  120. static struct platform_driver msc313_mpll_driver = {
  121. .driver = {
  122. .name = "mstar-msc313-mpll",
  123. .of_match_table = msc313_mpll_of_match,
  124. },
  125. .probe = msc313_mpll_probe,
  126. };
  127. builtin_platform_driver(msc313_mpll_driver);