clk-apmu.c 1.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * mmp AXI peripharal clock operation source file
  4. *
  5. * Copyright (C) 2012 Marvell
  6. * Chao Xie <[email protected]>
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/io.h>
  10. #include <linux/err.h>
  11. #include <linux/delay.h>
  12. #include <linux/slab.h>
  13. #include "clk.h"
  14. #define to_clk_apmu(clk) (container_of(clk, struct clk_apmu, clk))
  15. struct clk_apmu {
  16. struct clk_hw hw;
  17. void __iomem *base;
  18. u32 rst_mask;
  19. u32 enable_mask;
  20. spinlock_t *lock;
  21. };
  22. static int clk_apmu_enable(struct clk_hw *hw)
  23. {
  24. struct clk_apmu *apmu = to_clk_apmu(hw);
  25. unsigned long data;
  26. unsigned long flags = 0;
  27. if (apmu->lock)
  28. spin_lock_irqsave(apmu->lock, flags);
  29. data = readl_relaxed(apmu->base) | apmu->enable_mask;
  30. writel_relaxed(data, apmu->base);
  31. if (apmu->lock)
  32. spin_unlock_irqrestore(apmu->lock, flags);
  33. return 0;
  34. }
  35. static void clk_apmu_disable(struct clk_hw *hw)
  36. {
  37. struct clk_apmu *apmu = to_clk_apmu(hw);
  38. unsigned long data;
  39. unsigned long flags = 0;
  40. if (apmu->lock)
  41. spin_lock_irqsave(apmu->lock, flags);
  42. data = readl_relaxed(apmu->base) & ~apmu->enable_mask;
  43. writel_relaxed(data, apmu->base);
  44. if (apmu->lock)
  45. spin_unlock_irqrestore(apmu->lock, flags);
  46. }
  47. static const struct clk_ops clk_apmu_ops = {
  48. .enable = clk_apmu_enable,
  49. .disable = clk_apmu_disable,
  50. };
  51. struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name,
  52. void __iomem *base, u32 enable_mask, spinlock_t *lock)
  53. {
  54. struct clk_apmu *apmu;
  55. struct clk *clk;
  56. struct clk_init_data init;
  57. apmu = kzalloc(sizeof(*apmu), GFP_KERNEL);
  58. if (!apmu)
  59. return NULL;
  60. init.name = name;
  61. init.ops = &clk_apmu_ops;
  62. init.flags = CLK_SET_RATE_PARENT;
  63. init.parent_names = (parent_name ? &parent_name : NULL);
  64. init.num_parents = (parent_name ? 1 : 0);
  65. apmu->base = base;
  66. apmu->enable_mask = enable_mask;
  67. apmu->lock = lock;
  68. apmu->hw.init = &init;
  69. clk = clk_register(NULL, &apmu->hw);
  70. if (IS_ERR(clk))
  71. kfree(apmu);
  72. return clk;
  73. }