clk-mt8195-vdec.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // Copyright (c) 2021 MediaTek Inc.
  4. // Author: Chun-Jie Chen <[email protected]>
  5. #include "clk-gate.h"
  6. #include "clk-mtk.h"
  7. #include <dt-bindings/clock/mt8195-clk.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/platform_device.h>
  10. static const struct mtk_gate_regs vdec0_cg_regs = {
  11. .set_ofs = 0x0,
  12. .clr_ofs = 0x4,
  13. .sta_ofs = 0x0,
  14. };
  15. static const struct mtk_gate_regs vdec1_cg_regs = {
  16. .set_ofs = 0x200,
  17. .clr_ofs = 0x204,
  18. .sta_ofs = 0x200,
  19. };
  20. static const struct mtk_gate_regs vdec2_cg_regs = {
  21. .set_ofs = 0x8,
  22. .clr_ofs = 0xc,
  23. .sta_ofs = 0x8,
  24. };
  25. #define GATE_VDEC0(_id, _name, _parent, _shift) \
  26. GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
  27. #define GATE_VDEC1(_id, _name, _parent, _shift) \
  28. GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
  29. #define GATE_VDEC2(_id, _name, _parent, _shift) \
  30. GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
  31. static const struct mtk_gate vdec_clks[] = {
  32. /* VDEC0 */
  33. GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "top_vdec", 0),
  34. /* VDEC1 */
  35. GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "top_vdec", 0),
  36. /* VDEC2 */
  37. GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "top_vdec", 0),
  38. };
  39. static const struct mtk_gate vdec_core1_clks[] = {
  40. /* VDEC0 */
  41. GATE_VDEC0(CLK_VDEC_CORE1_VDEC, "vdec_core1_vdec", "top_vdec", 0),
  42. /* VDEC1 */
  43. GATE_VDEC1(CLK_VDEC_CORE1_LAT, "vdec_core1_lat", "top_vdec", 0),
  44. /* VDEC2 */
  45. GATE_VDEC2(CLK_VDEC_CORE1_LARB1, "vdec_core1_larb1", "top_vdec", 0),
  46. };
  47. static const struct mtk_gate vdec_soc_clks[] = {
  48. /* VDEC0 */
  49. GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "top_vdec", 0),
  50. /* VDEC1 */
  51. GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "top_vdec", 0),
  52. /* VDEC2 */
  53. GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "top_vdec", 0),
  54. };
  55. static const struct mtk_clk_desc vdec_desc = {
  56. .clks = vdec_clks,
  57. .num_clks = ARRAY_SIZE(vdec_clks),
  58. };
  59. static const struct mtk_clk_desc vdec_core1_desc = {
  60. .clks = vdec_core1_clks,
  61. .num_clks = ARRAY_SIZE(vdec_core1_clks),
  62. };
  63. static const struct mtk_clk_desc vdec_soc_desc = {
  64. .clks = vdec_soc_clks,
  65. .num_clks = ARRAY_SIZE(vdec_soc_clks),
  66. };
  67. static const struct of_device_id of_match_clk_mt8195_vdec[] = {
  68. {
  69. .compatible = "mediatek,mt8195-vdecsys",
  70. .data = &vdec_desc,
  71. }, {
  72. .compatible = "mediatek,mt8195-vdecsys_core1",
  73. .data = &vdec_core1_desc,
  74. }, {
  75. .compatible = "mediatek,mt8195-vdecsys_soc",
  76. .data = &vdec_soc_desc,
  77. }, {
  78. /* sentinel */
  79. }
  80. };
  81. static struct platform_driver clk_mt8195_vdec_drv = {
  82. .probe = mtk_clk_simple_probe,
  83. .remove = mtk_clk_simple_remove,
  84. .driver = {
  85. .name = "clk-mt8195-vdec",
  86. .of_match_table = of_match_clk_mt8195_vdec,
  87. },
  88. };
  89. builtin_platform_driver(clk_mt8195_vdec_drv);