clk-mt8167-mm.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2020 MediaTek Inc.
  4. * Copyright (c) 2020 BayLibre, SAS
  5. * Author: James Liao <[email protected]>
  6. * Fabien Parent <[email protected]>
  7. */
  8. #include <linux/clk-provider.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include "clk-mtk.h"
  14. #include "clk-gate.h"
  15. #include <dt-bindings/clock/mt8167-clk.h>
  16. static const struct mtk_gate_regs mm0_cg_regs = {
  17. .set_ofs = 0x104,
  18. .clr_ofs = 0x108,
  19. .sta_ofs = 0x100,
  20. };
  21. static const struct mtk_gate_regs mm1_cg_regs = {
  22. .set_ofs = 0x114,
  23. .clr_ofs = 0x118,
  24. .sta_ofs = 0x110,
  25. };
  26. #define GATE_MM0(_id, _name, _parent, _shift) \
  27. GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  28. #define GATE_MM1(_id, _name, _parent, _shift) \
  29. GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  30. static const struct mtk_gate mm_clks[] = {
  31. /* MM0 */
  32. GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "smi_mm", 0),
  33. GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "smi_mm", 1),
  34. GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "smi_mm", 2),
  35. GATE_MM0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "smi_mm", 3),
  36. GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "smi_mm", 4),
  37. GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "smi_mm", 5),
  38. GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "smi_mm", 6),
  39. GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "smi_mm", 7),
  40. GATE_MM0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "smi_mm", 8),
  41. GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "smi_mm", 9),
  42. GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "smi_mm", 10),
  43. GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "smi_mm", 11),
  44. GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "smi_mm", 12),
  45. GATE_MM0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "smi_mm", 13),
  46. GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "smi_mm", 14),
  47. GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "smi_mm", 15),
  48. GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "smi_mm", 16),
  49. GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "smi_mm", 17),
  50. GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "smi_mm", 18),
  51. GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "smi_mm", 19),
  52. /* MM1 */
  53. GATE_MM1(CLK_MM_DISP_PWM_MM, "mm_disp_pwm_mm", "smi_mm", 0),
  54. GATE_MM1(CLK_MM_DISP_PWM_26M, "mm_disp_pwm_26m", "smi_mm", 1),
  55. GATE_MM1(CLK_MM_DSI_ENGINE, "mm_dsi_engine", "smi_mm", 2),
  56. GATE_MM1(CLK_MM_DSI_DIGITAL, "mm_dsi_digital", "dsi0_lntc_dsick", 3),
  57. GATE_MM1(CLK_MM_DPI0_ENGINE, "mm_dpi0_engine", "smi_mm", 4),
  58. GATE_MM1(CLK_MM_DPI0_PXL, "mm_dpi0_pxl", "rg_fdpi0", 5),
  59. GATE_MM1(CLK_MM_LVDS_PXL, "mm_lvds_pxl", "vpll_dpix", 14),
  60. GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx_dig_cts", 15),
  61. GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "smi_mm", 16),
  62. GATE_MM1(CLK_MM_DPI1_PXL, "mm_dpi1_pxl", "rg_fdpi1", 17),
  63. GATE_MM1(CLK_MM_HDMI_PXL, "mm_hdmi_pxl", "rg_fdpi1", 18),
  64. GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll12_div6", 19),
  65. GATE_MM1(CLK_MM_HDMI_ADSP_BCK, "mm_hdmi_adsp_b", "apll12_div4b", 20),
  66. GATE_MM1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmtx_dig_cts", 21),
  67. };
  68. struct clk_mt8167_mm_driver_data {
  69. const struct mtk_gate *gates_clk;
  70. int gates_num;
  71. };
  72. static const struct clk_mt8167_mm_driver_data mt8167_mmsys_driver_data = {
  73. .gates_clk = mm_clks,
  74. .gates_num = ARRAY_SIZE(mm_clks),
  75. };
  76. static int clk_mt8167_mm_probe(struct platform_device *pdev)
  77. {
  78. struct device *dev = &pdev->dev;
  79. struct device_node *node = dev->parent->of_node;
  80. const struct clk_mt8167_mm_driver_data *data;
  81. struct clk_hw_onecell_data *clk_data;
  82. int ret;
  83. clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
  84. if (!clk_data)
  85. return -ENOMEM;
  86. data = &mt8167_mmsys_driver_data;
  87. ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num,
  88. clk_data);
  89. if (ret)
  90. return ret;
  91. ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  92. if (ret)
  93. return ret;
  94. return 0;
  95. }
  96. static struct platform_driver clk_mt8173_mm_drv = {
  97. .driver = {
  98. .name = "clk-mt8167-mm",
  99. },
  100. .probe = clk_mt8167_mm_probe,
  101. };
  102. builtin_platform_driver(clk_mt8173_mm_drv);