clk-programmable.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2013 Boris BREZILLON <[email protected]>
  4. */
  5. #include <linux/clk-provider.h>
  6. #include <linux/clkdev.h>
  7. #include <linux/clk/at91_pmc.h>
  8. #include <linux/of.h>
  9. #include <linux/mfd/syscon.h>
  10. #include <linux/regmap.h>
  11. #include "pmc.h"
  12. #define PROG_ID_MAX 7
  13. #define PROG_STATUS_MASK(id) (1 << ((id) + 8))
  14. #define PROG_PRES(layout, pckr) ((pckr >> layout->pres_shift) & layout->pres_mask)
  15. #define PROG_MAX_RM9200_CSS 3
  16. struct clk_programmable {
  17. struct clk_hw hw;
  18. struct regmap *regmap;
  19. u32 *mux_table;
  20. u8 id;
  21. const struct clk_programmable_layout *layout;
  22. struct at91_clk_pms pms;
  23. };
  24. #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)
  25. static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
  26. unsigned long parent_rate)
  27. {
  28. struct clk_programmable *prog = to_clk_programmable(hw);
  29. const struct clk_programmable_layout *layout = prog->layout;
  30. unsigned int pckr;
  31. unsigned long rate;
  32. regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr);
  33. if (layout->is_pres_direct)
  34. rate = parent_rate / (PROG_PRES(layout, pckr) + 1);
  35. else
  36. rate = parent_rate >> PROG_PRES(layout, pckr);
  37. return rate;
  38. }
  39. static int clk_programmable_determine_rate(struct clk_hw *hw,
  40. struct clk_rate_request *req)
  41. {
  42. struct clk_programmable *prog = to_clk_programmable(hw);
  43. const struct clk_programmable_layout *layout = prog->layout;
  44. struct clk_hw *parent;
  45. long best_rate = -EINVAL;
  46. unsigned long parent_rate;
  47. unsigned long tmp_rate = 0;
  48. int shift;
  49. int i;
  50. for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
  51. parent = clk_hw_get_parent_by_index(hw, i);
  52. if (!parent)
  53. continue;
  54. parent_rate = clk_hw_get_rate(parent);
  55. if (layout->is_pres_direct) {
  56. for (shift = 0; shift <= layout->pres_mask; shift++) {
  57. tmp_rate = parent_rate / (shift + 1);
  58. if (tmp_rate <= req->rate)
  59. break;
  60. }
  61. } else {
  62. for (shift = 0; shift < layout->pres_mask; shift++) {
  63. tmp_rate = parent_rate >> shift;
  64. if (tmp_rate <= req->rate)
  65. break;
  66. }
  67. }
  68. if (tmp_rate > req->rate)
  69. continue;
  70. if (best_rate < 0 ||
  71. (req->rate - tmp_rate) < (req->rate - best_rate)) {
  72. best_rate = tmp_rate;
  73. req->best_parent_rate = parent_rate;
  74. req->best_parent_hw = parent;
  75. }
  76. if (!best_rate)
  77. break;
  78. }
  79. if (best_rate < 0)
  80. return best_rate;
  81. req->rate = best_rate;
  82. return 0;
  83. }
  84. static int clk_programmable_set_parent(struct clk_hw *hw, u8 index)
  85. {
  86. struct clk_programmable *prog = to_clk_programmable(hw);
  87. const struct clk_programmable_layout *layout = prog->layout;
  88. unsigned int mask = layout->css_mask;
  89. unsigned int pckr = index;
  90. if (layout->have_slck_mck)
  91. mask |= AT91_PMC_CSSMCK_MCK;
  92. if (prog->mux_table)
  93. pckr = clk_mux_index_to_val(prog->mux_table, 0, index);
  94. if (index > layout->css_mask) {
  95. if (index > PROG_MAX_RM9200_CSS && !layout->have_slck_mck)
  96. return -EINVAL;
  97. pckr |= AT91_PMC_CSSMCK_MCK;
  98. }
  99. regmap_update_bits(prog->regmap, AT91_PMC_PCKR(prog->id), mask, pckr);
  100. return 0;
  101. }
  102. static u8 clk_programmable_get_parent(struct clk_hw *hw)
  103. {
  104. struct clk_programmable *prog = to_clk_programmable(hw);
  105. const struct clk_programmable_layout *layout = prog->layout;
  106. unsigned int pckr;
  107. u8 ret;
  108. regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr);
  109. ret = pckr & layout->css_mask;
  110. if (layout->have_slck_mck && (pckr & AT91_PMC_CSSMCK_MCK) && !ret)
  111. ret = PROG_MAX_RM9200_CSS + 1;
  112. if (prog->mux_table)
  113. ret = clk_mux_val_to_index(&prog->hw, prog->mux_table, 0, ret);
  114. return ret;
  115. }
  116. static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate,
  117. unsigned long parent_rate)
  118. {
  119. struct clk_programmable *prog = to_clk_programmable(hw);
  120. const struct clk_programmable_layout *layout = prog->layout;
  121. unsigned long div = parent_rate / rate;
  122. int shift = 0;
  123. if (!div)
  124. return -EINVAL;
  125. if (layout->is_pres_direct) {
  126. shift = div - 1;
  127. if (shift > layout->pres_mask)
  128. return -EINVAL;
  129. } else {
  130. shift = fls(div) - 1;
  131. if (div != (1 << shift))
  132. return -EINVAL;
  133. if (shift >= layout->pres_mask)
  134. return -EINVAL;
  135. }
  136. regmap_update_bits(prog->regmap, AT91_PMC_PCKR(prog->id),
  137. layout->pres_mask << layout->pres_shift,
  138. shift << layout->pres_shift);
  139. return 0;
  140. }
  141. static int clk_programmable_save_context(struct clk_hw *hw)
  142. {
  143. struct clk_programmable *prog = to_clk_programmable(hw);
  144. struct clk_hw *parent_hw = clk_hw_get_parent(hw);
  145. prog->pms.parent = clk_programmable_get_parent(hw);
  146. prog->pms.parent_rate = clk_hw_get_rate(parent_hw);
  147. prog->pms.rate = clk_programmable_recalc_rate(hw, prog->pms.parent_rate);
  148. return 0;
  149. }
  150. static void clk_programmable_restore_context(struct clk_hw *hw)
  151. {
  152. struct clk_programmable *prog = to_clk_programmable(hw);
  153. int ret;
  154. ret = clk_programmable_set_parent(hw, prog->pms.parent);
  155. if (ret)
  156. return;
  157. clk_programmable_set_rate(hw, prog->pms.rate, prog->pms.parent_rate);
  158. }
  159. static const struct clk_ops programmable_ops = {
  160. .recalc_rate = clk_programmable_recalc_rate,
  161. .determine_rate = clk_programmable_determine_rate,
  162. .get_parent = clk_programmable_get_parent,
  163. .set_parent = clk_programmable_set_parent,
  164. .set_rate = clk_programmable_set_rate,
  165. .save_context = clk_programmable_save_context,
  166. .restore_context = clk_programmable_restore_context,
  167. };
  168. struct clk_hw * __init
  169. at91_clk_register_programmable(struct regmap *regmap,
  170. const char *name, const char **parent_names,
  171. u8 num_parents, u8 id,
  172. const struct clk_programmable_layout *layout,
  173. u32 *mux_table)
  174. {
  175. struct clk_programmable *prog;
  176. struct clk_hw *hw;
  177. struct clk_init_data init;
  178. int ret;
  179. if (id > PROG_ID_MAX)
  180. return ERR_PTR(-EINVAL);
  181. prog = kzalloc(sizeof(*prog), GFP_KERNEL);
  182. if (!prog)
  183. return ERR_PTR(-ENOMEM);
  184. init.name = name;
  185. init.ops = &programmable_ops;
  186. init.parent_names = parent_names;
  187. init.num_parents = num_parents;
  188. init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
  189. prog->id = id;
  190. prog->layout = layout;
  191. prog->hw.init = &init;
  192. prog->regmap = regmap;
  193. prog->mux_table = mux_table;
  194. hw = &prog->hw;
  195. ret = clk_hw_register(NULL, &prog->hw);
  196. if (ret) {
  197. kfree(prog);
  198. hw = ERR_PTR(ret);
  199. }
  200. return hw;
  201. }
  202. const struct clk_programmable_layout at91rm9200_programmable_layout = {
  203. .pres_mask = 0x7,
  204. .pres_shift = 2,
  205. .css_mask = 0x3,
  206. .have_slck_mck = 0,
  207. .is_pres_direct = 0,
  208. };
  209. const struct clk_programmable_layout at91sam9g45_programmable_layout = {
  210. .pres_mask = 0x7,
  211. .pres_shift = 2,
  212. .css_mask = 0x3,
  213. .have_slck_mck = 1,
  214. .is_pres_direct = 0,
  215. };
  216. const struct clk_programmable_layout at91sam9x5_programmable_layout = {
  217. .pres_mask = 0x7,
  218. .pres_shift = 4,
  219. .css_mask = 0x7,
  220. .have_slck_mck = 0,
  221. .is_pres_direct = 0,
  222. };