tpm_tis_i2c.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2014-2021 Nuvoton Technology corporation
  4. * Copyright (C) 2019-2022 Infineon Technologies AG
  5. *
  6. * This device driver implements the TPM interface as defined in the TCG PC
  7. * Client Platform TPM Profile (PTP) Specification for TPM 2.0 v1.04
  8. * Revision 14.
  9. *
  10. * It is based on the tpm_tis_spi device driver.
  11. */
  12. #include <linux/i2c.h>
  13. #include <linux/crc-ccitt.h>
  14. #include "tpm_tis_core.h"
  15. /* TPM registers */
  16. #define TPM_I2C_LOC_SEL 0x00
  17. #define TPM_I2C_ACCESS 0x04
  18. #define TPM_I2C_INTERFACE_CAPABILITY 0x30
  19. #define TPM_I2C_DEVICE_ADDRESS 0x38
  20. #define TPM_I2C_DATA_CSUM_ENABLE 0x40
  21. #define TPM_DATA_CSUM 0x44
  22. #define TPM_I2C_DID_VID 0x48
  23. #define TPM_I2C_RID 0x4C
  24. /* TIS-compatible register address to avoid clash with TPM_ACCESS (0x00) */
  25. #define TPM_LOC_SEL 0x0FFF
  26. /* Mask to extract the I2C register from TIS register addresses */
  27. #define TPM_TIS_REGISTER_MASK 0x0FFF
  28. /* Default Guard Time of 250µs until interface capability register is read */
  29. #define GUARD_TIME_DEFAULT_MIN 250
  30. #define GUARD_TIME_DEFAULT_MAX 300
  31. /* Guard Time of 250µs after I2C slave NACK */
  32. #define GUARD_TIME_ERR_MIN 250
  33. #define GUARD_TIME_ERR_MAX 300
  34. /* Guard Time bit masks; SR is repeated start, RW is read then write, etc. */
  35. #define TPM_GUARD_TIME_SR_MASK 0x40000000
  36. #define TPM_GUARD_TIME_RR_MASK 0x00100000
  37. #define TPM_GUARD_TIME_RW_MASK 0x00080000
  38. #define TPM_GUARD_TIME_WR_MASK 0x00040000
  39. #define TPM_GUARD_TIME_WW_MASK 0x00020000
  40. #define TPM_GUARD_TIME_MIN_MASK 0x0001FE00
  41. #define TPM_GUARD_TIME_MIN_SHIFT 9
  42. /* Masks with bits that must be read zero */
  43. #define TPM_ACCESS_READ_ZERO 0x48
  44. #define TPM_INT_ENABLE_ZERO 0x7FFFFF60
  45. #define TPM_STS_READ_ZERO 0x23
  46. #define TPM_INTF_CAPABILITY_ZERO 0x0FFFF000
  47. #define TPM_I2C_INTERFACE_CAPABILITY_ZERO 0x80000000
  48. struct tpm_tis_i2c_phy {
  49. struct tpm_tis_data priv;
  50. struct i2c_client *i2c_client;
  51. bool guard_time_read;
  52. bool guard_time_write;
  53. u16 guard_time_min;
  54. u16 guard_time_max;
  55. u8 *io_buf;
  56. };
  57. static inline struct tpm_tis_i2c_phy *
  58. to_tpm_tis_i2c_phy(struct tpm_tis_data *data)
  59. {
  60. return container_of(data, struct tpm_tis_i2c_phy, priv);
  61. }
  62. /*
  63. * tpm_tis_core uses the register addresses as defined in Table 19 "Allocation
  64. * of Register Space for FIFO TPM Access" of the TCG PC Client PTP
  65. * Specification. In order for this code to work together with tpm_tis_core,
  66. * those addresses need to mapped to the registers defined for I2C TPMs in
  67. * Table 51 "I2C-TPM Register Overview".
  68. *
  69. * For most addresses this can be done by simply stripping off the locality
  70. * information from the address. A few addresses need to be mapped explicitly,
  71. * since the corresponding I2C registers have been moved around. TPM_LOC_SEL is
  72. * only defined for I2C TPMs and is also mapped explicitly here to distinguish
  73. * it from TPM_ACCESS(0).
  74. *
  75. * Locality information is ignored, since this driver assumes exclusive access
  76. * to the TPM and always uses locality 0.
  77. */
  78. static u8 tpm_tis_i2c_address_to_register(u32 addr)
  79. {
  80. addr &= TPM_TIS_REGISTER_MASK;
  81. switch (addr) {
  82. case TPM_ACCESS(0):
  83. return TPM_I2C_ACCESS;
  84. case TPM_LOC_SEL:
  85. return TPM_I2C_LOC_SEL;
  86. case TPM_DID_VID(0):
  87. return TPM_I2C_DID_VID;
  88. case TPM_RID(0):
  89. return TPM_I2C_RID;
  90. default:
  91. return addr;
  92. }
  93. }
  94. static int tpm_tis_i2c_retry_transfer_until_ack(struct tpm_tis_data *data,
  95. struct i2c_msg *msg)
  96. {
  97. struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
  98. bool guard_time;
  99. int i = 0;
  100. int ret;
  101. if (msg->flags & I2C_M_RD)
  102. guard_time = phy->guard_time_read;
  103. else
  104. guard_time = phy->guard_time_write;
  105. do {
  106. ret = i2c_transfer(phy->i2c_client->adapter, msg, 1);
  107. if (ret < 0)
  108. usleep_range(GUARD_TIME_ERR_MIN, GUARD_TIME_ERR_MAX);
  109. else if (guard_time)
  110. usleep_range(phy->guard_time_min, phy->guard_time_max);
  111. /* retry on TPM NACK */
  112. } while (ret < 0 && i++ < TPM_RETRY);
  113. return ret;
  114. }
  115. /* Check that bits which must be read zero are not set */
  116. static int tpm_tis_i2c_sanity_check_read(u8 reg, u16 len, u8 *buf)
  117. {
  118. u32 zero_mask;
  119. u32 value;
  120. switch (len) {
  121. case sizeof(u8):
  122. value = buf[0];
  123. break;
  124. case sizeof(u16):
  125. value = le16_to_cpup((__le16 *)buf);
  126. break;
  127. case sizeof(u32):
  128. value = le32_to_cpup((__le32 *)buf);
  129. break;
  130. default:
  131. /* unknown length, skip check */
  132. return 0;
  133. }
  134. switch (reg) {
  135. case TPM_I2C_ACCESS:
  136. zero_mask = TPM_ACCESS_READ_ZERO;
  137. break;
  138. case TPM_INT_ENABLE(0) & TPM_TIS_REGISTER_MASK:
  139. zero_mask = TPM_INT_ENABLE_ZERO;
  140. break;
  141. case TPM_STS(0) & TPM_TIS_REGISTER_MASK:
  142. zero_mask = TPM_STS_READ_ZERO;
  143. break;
  144. case TPM_INTF_CAPS(0) & TPM_TIS_REGISTER_MASK:
  145. zero_mask = TPM_INTF_CAPABILITY_ZERO;
  146. break;
  147. case TPM_I2C_INTERFACE_CAPABILITY:
  148. zero_mask = TPM_I2C_INTERFACE_CAPABILITY_ZERO;
  149. break;
  150. default:
  151. /* unknown register, skip check */
  152. return 0;
  153. }
  154. if (unlikely((value & zero_mask) != 0x00)) {
  155. pr_debug("TPM I2C read of register 0x%02x failed sanity check: 0x%x\n", reg, value);
  156. return -EIO;
  157. }
  158. return 0;
  159. }
  160. static int tpm_tis_i2c_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
  161. u8 *result, enum tpm_tis_io_mode io_mode)
  162. {
  163. struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
  164. struct i2c_msg msg = { .addr = phy->i2c_client->addr };
  165. u8 reg = tpm_tis_i2c_address_to_register(addr);
  166. int i;
  167. int ret;
  168. for (i = 0; i < TPM_RETRY; i++) {
  169. u16 read = 0;
  170. while (read < len) {
  171. /* write register */
  172. msg.len = sizeof(reg);
  173. msg.buf = &reg;
  174. msg.flags = 0;
  175. ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
  176. if (ret < 0)
  177. return ret;
  178. /* read data */
  179. msg.buf = result + read;
  180. msg.len = len - read;
  181. msg.flags = I2C_M_RD;
  182. if (msg.len > I2C_SMBUS_BLOCK_MAX)
  183. msg.len = I2C_SMBUS_BLOCK_MAX;
  184. ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
  185. if (ret < 0)
  186. return ret;
  187. read += msg.len;
  188. }
  189. ret = tpm_tis_i2c_sanity_check_read(reg, len, result);
  190. if (ret == 0)
  191. return 0;
  192. usleep_range(GUARD_TIME_ERR_MIN, GUARD_TIME_ERR_MAX);
  193. }
  194. return ret;
  195. }
  196. static int tpm_tis_i2c_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
  197. const u8 *value,
  198. enum tpm_tis_io_mode io_mode)
  199. {
  200. struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
  201. struct i2c_msg msg = { .addr = phy->i2c_client->addr };
  202. u8 reg = tpm_tis_i2c_address_to_register(addr);
  203. int ret;
  204. u16 wrote = 0;
  205. if (len > TPM_BUFSIZE - 1)
  206. return -EIO;
  207. phy->io_buf[0] = reg;
  208. msg.buf = phy->io_buf;
  209. while (wrote < len) {
  210. /* write register and data in one go */
  211. msg.len = sizeof(reg) + len - wrote;
  212. if (msg.len > I2C_SMBUS_BLOCK_MAX)
  213. msg.len = I2C_SMBUS_BLOCK_MAX;
  214. memcpy(phy->io_buf + sizeof(reg), value + wrote,
  215. msg.len - sizeof(reg));
  216. ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
  217. if (ret < 0)
  218. return ret;
  219. wrote += msg.len - sizeof(reg);
  220. }
  221. return 0;
  222. }
  223. static int tpm_tis_i2c_verify_crc(struct tpm_tis_data *data, size_t len,
  224. const u8 *value)
  225. {
  226. u16 crc_tpm, crc_host;
  227. int rc;
  228. rc = tpm_tis_read16(data, TPM_DATA_CSUM, &crc_tpm);
  229. if (rc < 0)
  230. return rc;
  231. /* reflect crc result, regardless of host endianness */
  232. crc_host = swab16(crc_ccitt(0, value, len));
  233. if (crc_tpm != crc_host)
  234. return -EIO;
  235. return 0;
  236. }
  237. /*
  238. * Guard Time:
  239. * After each I2C operation, the TPM might require the master to wait.
  240. * The time period is vendor-specific and must be read from the
  241. * TPM_I2C_INTERFACE_CAPABILITY register.
  242. *
  243. * Before the Guard Time is read (or after the TPM failed to send an I2C NACK),
  244. * a Guard Time of 250µs applies.
  245. *
  246. * Various flags in the same register indicate if a guard time is needed:
  247. * - SR: <I2C read with repeated start> <guard time> <I2C read>
  248. * - RR: <I2C read> <guard time> <I2C read>
  249. * - RW: <I2C read> <guard time> <I2C write>
  250. * - WR: <I2C write> <guard time> <I2C read>
  251. * - WW: <I2C write> <guard time> <I2C write>
  252. *
  253. * See TCG PC Client PTP Specification v1.04, 8.1.10 GUARD_TIME
  254. */
  255. static int tpm_tis_i2c_init_guard_time(struct tpm_tis_i2c_phy *phy)
  256. {
  257. u32 i2c_caps;
  258. int ret;
  259. phy->guard_time_read = true;
  260. phy->guard_time_write = true;
  261. phy->guard_time_min = GUARD_TIME_DEFAULT_MIN;
  262. phy->guard_time_max = GUARD_TIME_DEFAULT_MAX;
  263. ret = tpm_tis_i2c_read_bytes(&phy->priv, TPM_I2C_INTERFACE_CAPABILITY,
  264. sizeof(i2c_caps), (u8 *)&i2c_caps,
  265. TPM_TIS_PHYS_32);
  266. if (ret)
  267. return ret;
  268. phy->guard_time_read = (i2c_caps & TPM_GUARD_TIME_RR_MASK) ||
  269. (i2c_caps & TPM_GUARD_TIME_RW_MASK);
  270. phy->guard_time_write = (i2c_caps & TPM_GUARD_TIME_WR_MASK) ||
  271. (i2c_caps & TPM_GUARD_TIME_WW_MASK);
  272. phy->guard_time_min = (i2c_caps & TPM_GUARD_TIME_MIN_MASK) >>
  273. TPM_GUARD_TIME_MIN_SHIFT;
  274. /* guard_time_max = guard_time_min * 1.2 */
  275. phy->guard_time_max = phy->guard_time_min + phy->guard_time_min / 5;
  276. return 0;
  277. }
  278. static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
  279. static const struct tpm_tis_phy_ops tpm_i2c_phy_ops = {
  280. .read_bytes = tpm_tis_i2c_read_bytes,
  281. .write_bytes = tpm_tis_i2c_write_bytes,
  282. .verify_crc = tpm_tis_i2c_verify_crc,
  283. };
  284. static int tpm_tis_i2c_probe(struct i2c_client *dev,
  285. const struct i2c_device_id *id)
  286. {
  287. struct tpm_tis_i2c_phy *phy;
  288. const u8 crc_enable = 1;
  289. const u8 locality = 0;
  290. int ret;
  291. phy = devm_kzalloc(&dev->dev, sizeof(struct tpm_tis_i2c_phy),
  292. GFP_KERNEL);
  293. if (!phy)
  294. return -ENOMEM;
  295. phy->io_buf = devm_kzalloc(&dev->dev, TPM_BUFSIZE, GFP_KERNEL);
  296. if (!phy->io_buf)
  297. return -ENOMEM;
  298. set_bit(TPM_TIS_DEFAULT_CANCELLATION, &phy->priv.flags);
  299. phy->i2c_client = dev;
  300. /* must precede all communication with the tpm */
  301. ret = tpm_tis_i2c_init_guard_time(phy);
  302. if (ret)
  303. return ret;
  304. ret = tpm_tis_i2c_write_bytes(&phy->priv, TPM_LOC_SEL, sizeof(locality),
  305. &locality, TPM_TIS_PHYS_8);
  306. if (ret)
  307. return ret;
  308. ret = tpm_tis_i2c_write_bytes(&phy->priv, TPM_I2C_DATA_CSUM_ENABLE,
  309. sizeof(crc_enable), &crc_enable,
  310. TPM_TIS_PHYS_8);
  311. if (ret)
  312. return ret;
  313. return tpm_tis_core_init(&dev->dev, &phy->priv, -1, &tpm_i2c_phy_ops,
  314. NULL);
  315. }
  316. static void tpm_tis_i2c_remove(struct i2c_client *client)
  317. {
  318. struct tpm_chip *chip = i2c_get_clientdata(client);
  319. tpm_chip_unregister(chip);
  320. tpm_tis_remove(chip);
  321. }
  322. static const struct i2c_device_id tpm_tis_i2c_id[] = {
  323. { "tpm_tis_i2c", 0 },
  324. {}
  325. };
  326. MODULE_DEVICE_TABLE(i2c, tpm_tis_i2c_id);
  327. #ifdef CONFIG_OF
  328. static const struct of_device_id of_tis_i2c_match[] = {
  329. { .compatible = "infineon,slb9673", },
  330. {}
  331. };
  332. MODULE_DEVICE_TABLE(of, of_tis_i2c_match);
  333. #endif
  334. static struct i2c_driver tpm_tis_i2c_driver = {
  335. .driver = {
  336. .name = "tpm_tis_i2c",
  337. .pm = &tpm_tis_pm,
  338. .of_match_table = of_match_ptr(of_tis_i2c_match),
  339. },
  340. .probe = tpm_tis_i2c_probe,
  341. .remove = tpm_tis_i2c_remove,
  342. .id_table = tpm_tis_i2c_id,
  343. };
  344. module_i2c_driver(tpm_tis_i2c_driver);
  345. MODULE_DESCRIPTION("TPM Driver for native I2C access");
  346. MODULE_LICENSE("GPL");