hci_qca.c 61 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Bluetooth Software UART Qualcomm protocol
  4. *
  5. * HCI_IBS (HCI In-Band Sleep) is Qualcomm's power management
  6. * protocol extension to H4.
  7. *
  8. * Copyright (C) 2007 Texas Instruments, Inc.
  9. * Copyright (c) 2010, 2012, 2018 The Linux Foundation. All rights reserved.
  10. *
  11. * Acknowledgements:
  12. * This file is based on hci_ll.c, which was...
  13. * Written by Ohad Ben-Cohen <[email protected]>
  14. * which was in turn based on hci_h4.c, which was written
  15. * by Maxim Krasnyansky and Marcel Holtmann.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/clk.h>
  19. #include <linux/completion.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/delay.h>
  22. #include <linux/devcoredump.h>
  23. #include <linux/device.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/mod_devicetable.h>
  26. #include <linux/module.h>
  27. #include <linux/of_device.h>
  28. #include <linux/acpi.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/regulator/consumer.h>
  31. #include <linux/serdev.h>
  32. #include <linux/mutex.h>
  33. #include <asm/unaligned.h>
  34. #include <net/bluetooth/bluetooth.h>
  35. #include <net/bluetooth/hci_core.h>
  36. #include "hci_uart.h"
  37. #include "btqca.h"
  38. /* HCI_IBS protocol messages */
  39. #define HCI_IBS_SLEEP_IND 0xFE
  40. #define HCI_IBS_WAKE_IND 0xFD
  41. #define HCI_IBS_WAKE_ACK 0xFC
  42. #define HCI_MAX_IBS_SIZE 10
  43. #define IBS_WAKE_RETRANS_TIMEOUT_MS 100
  44. #define IBS_BTSOC_TX_IDLE_TIMEOUT_MS 200
  45. #define IBS_HOST_TX_IDLE_TIMEOUT_MS 2000
  46. #define CMD_TRANS_TIMEOUT_MS 100
  47. #define MEMDUMP_TIMEOUT_MS 8000
  48. #define IBS_DISABLE_SSR_TIMEOUT_MS \
  49. (MEMDUMP_TIMEOUT_MS + FW_DOWNLOAD_TIMEOUT_MS)
  50. #define FW_DOWNLOAD_TIMEOUT_MS 3000
  51. /* susclk rate */
  52. #define SUSCLK_RATE_32KHZ 32768
  53. /* Controller debug log header */
  54. #define QCA_DEBUG_HANDLE 0x2EDC
  55. /* max retry count when init fails */
  56. #define MAX_INIT_RETRIES 3
  57. /* Controller dump header */
  58. #define QCA_SSR_DUMP_HANDLE 0x0108
  59. #define QCA_DUMP_PACKET_SIZE 255
  60. #define QCA_LAST_SEQUENCE_NUM 0xFFFF
  61. #define QCA_CRASHBYTE_PACKET_LEN 1096
  62. #define QCA_MEMDUMP_BYTE 0xFB
  63. enum qca_flags {
  64. QCA_IBS_DISABLED,
  65. QCA_DROP_VENDOR_EVENT,
  66. QCA_SUSPENDING,
  67. QCA_MEMDUMP_COLLECTION,
  68. QCA_HW_ERROR_EVENT,
  69. QCA_SSR_TRIGGERED,
  70. QCA_BT_OFF,
  71. QCA_ROM_FW,
  72. QCA_DEBUGFS_CREATED,
  73. };
  74. enum qca_capabilities {
  75. QCA_CAP_WIDEBAND_SPEECH = BIT(0),
  76. QCA_CAP_VALID_LE_STATES = BIT(1),
  77. };
  78. /* HCI_IBS transmit side sleep protocol states */
  79. enum tx_ibs_states {
  80. HCI_IBS_TX_ASLEEP,
  81. HCI_IBS_TX_WAKING,
  82. HCI_IBS_TX_AWAKE,
  83. };
  84. /* HCI_IBS receive side sleep protocol states */
  85. enum rx_states {
  86. HCI_IBS_RX_ASLEEP,
  87. HCI_IBS_RX_AWAKE,
  88. };
  89. /* HCI_IBS transmit and receive side clock state vote */
  90. enum hci_ibs_clock_state_vote {
  91. HCI_IBS_VOTE_STATS_UPDATE,
  92. HCI_IBS_TX_VOTE_CLOCK_ON,
  93. HCI_IBS_TX_VOTE_CLOCK_OFF,
  94. HCI_IBS_RX_VOTE_CLOCK_ON,
  95. HCI_IBS_RX_VOTE_CLOCK_OFF,
  96. };
  97. /* Controller memory dump states */
  98. enum qca_memdump_states {
  99. QCA_MEMDUMP_IDLE,
  100. QCA_MEMDUMP_COLLECTING,
  101. QCA_MEMDUMP_COLLECTED,
  102. QCA_MEMDUMP_TIMEOUT,
  103. };
  104. struct qca_memdump_data {
  105. char *memdump_buf_head;
  106. char *memdump_buf_tail;
  107. u32 current_seq_no;
  108. u32 received_dump;
  109. u32 ram_dump_size;
  110. };
  111. struct qca_memdump_event_hdr {
  112. __u8 evt;
  113. __u8 plen;
  114. __u16 opcode;
  115. __u16 seq_no;
  116. __u8 reserved;
  117. } __packed;
  118. struct qca_dump_size {
  119. u32 dump_size;
  120. } __packed;
  121. struct qca_data {
  122. struct hci_uart *hu;
  123. struct sk_buff *rx_skb;
  124. struct sk_buff_head txq;
  125. struct sk_buff_head tx_wait_q; /* HCI_IBS wait queue */
  126. struct sk_buff_head rx_memdump_q; /* Memdump wait queue */
  127. spinlock_t hci_ibs_lock; /* HCI_IBS state lock */
  128. u8 tx_ibs_state; /* HCI_IBS transmit side power state*/
  129. u8 rx_ibs_state; /* HCI_IBS receive side power state */
  130. bool tx_vote; /* Clock must be on for TX */
  131. bool rx_vote; /* Clock must be on for RX */
  132. struct timer_list tx_idle_timer;
  133. u32 tx_idle_delay;
  134. struct timer_list wake_retrans_timer;
  135. u32 wake_retrans;
  136. struct workqueue_struct *workqueue;
  137. struct work_struct ws_awake_rx;
  138. struct work_struct ws_awake_device;
  139. struct work_struct ws_rx_vote_off;
  140. struct work_struct ws_tx_vote_off;
  141. struct work_struct ctrl_memdump_evt;
  142. struct delayed_work ctrl_memdump_timeout;
  143. struct qca_memdump_data *qca_memdump;
  144. unsigned long flags;
  145. struct completion drop_ev_comp;
  146. wait_queue_head_t suspend_wait_q;
  147. enum qca_memdump_states memdump_state;
  148. struct mutex hci_memdump_lock;
  149. /* For debugging purpose */
  150. u64 ibs_sent_wacks;
  151. u64 ibs_sent_slps;
  152. u64 ibs_sent_wakes;
  153. u64 ibs_recv_wacks;
  154. u64 ibs_recv_slps;
  155. u64 ibs_recv_wakes;
  156. u64 vote_last_jif;
  157. u32 vote_on_ms;
  158. u32 vote_off_ms;
  159. u64 tx_votes_on;
  160. u64 rx_votes_on;
  161. u64 tx_votes_off;
  162. u64 rx_votes_off;
  163. u64 votes_on;
  164. u64 votes_off;
  165. };
  166. enum qca_speed_type {
  167. QCA_INIT_SPEED = 1,
  168. QCA_OPER_SPEED
  169. };
  170. /*
  171. * Voltage regulator information required for configuring the
  172. * QCA Bluetooth chipset
  173. */
  174. struct qca_vreg {
  175. const char *name;
  176. unsigned int load_uA;
  177. };
  178. struct qca_device_data {
  179. enum qca_btsoc_type soc_type;
  180. struct qca_vreg *vregs;
  181. size_t num_vregs;
  182. uint32_t capabilities;
  183. };
  184. /*
  185. * Platform data for the QCA Bluetooth power driver.
  186. */
  187. struct qca_power {
  188. struct device *dev;
  189. struct regulator_bulk_data *vreg_bulk;
  190. int num_vregs;
  191. bool vregs_on;
  192. };
  193. struct qca_serdev {
  194. struct hci_uart serdev_hu;
  195. struct gpio_desc *bt_en;
  196. struct gpio_desc *sw_ctrl;
  197. struct clk *susclk;
  198. enum qca_btsoc_type btsoc_type;
  199. struct qca_power *bt_power;
  200. u32 init_speed;
  201. u32 oper_speed;
  202. const char *firmware_name;
  203. };
  204. static int qca_regulator_enable(struct qca_serdev *qcadev);
  205. static void qca_regulator_disable(struct qca_serdev *qcadev);
  206. static void qca_power_shutdown(struct hci_uart *hu);
  207. static int qca_power_off(struct hci_dev *hdev);
  208. static void qca_controller_memdump(struct work_struct *work);
  209. static enum qca_btsoc_type qca_soc_type(struct hci_uart *hu)
  210. {
  211. enum qca_btsoc_type soc_type;
  212. if (hu->serdev) {
  213. struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
  214. soc_type = qsd->btsoc_type;
  215. } else {
  216. soc_type = QCA_ROME;
  217. }
  218. return soc_type;
  219. }
  220. static const char *qca_get_firmware_name(struct hci_uart *hu)
  221. {
  222. if (hu->serdev) {
  223. struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
  224. return qsd->firmware_name;
  225. } else {
  226. return NULL;
  227. }
  228. }
  229. static void __serial_clock_on(struct tty_struct *tty)
  230. {
  231. /* TODO: Some chipset requires to enable UART clock on client
  232. * side to save power consumption or manual work is required.
  233. * Please put your code to control UART clock here if needed
  234. */
  235. }
  236. static void __serial_clock_off(struct tty_struct *tty)
  237. {
  238. /* TODO: Some chipset requires to disable UART clock on client
  239. * side to save power consumption or manual work is required.
  240. * Please put your code to control UART clock off here if needed
  241. */
  242. }
  243. /* serial_clock_vote needs to be called with the ibs lock held */
  244. static void serial_clock_vote(unsigned long vote, struct hci_uart *hu)
  245. {
  246. struct qca_data *qca = hu->priv;
  247. unsigned int diff;
  248. bool old_vote = (qca->tx_vote | qca->rx_vote);
  249. bool new_vote;
  250. switch (vote) {
  251. case HCI_IBS_VOTE_STATS_UPDATE:
  252. diff = jiffies_to_msecs(jiffies - qca->vote_last_jif);
  253. if (old_vote)
  254. qca->vote_off_ms += diff;
  255. else
  256. qca->vote_on_ms += diff;
  257. return;
  258. case HCI_IBS_TX_VOTE_CLOCK_ON:
  259. qca->tx_vote = true;
  260. qca->tx_votes_on++;
  261. break;
  262. case HCI_IBS_RX_VOTE_CLOCK_ON:
  263. qca->rx_vote = true;
  264. qca->rx_votes_on++;
  265. break;
  266. case HCI_IBS_TX_VOTE_CLOCK_OFF:
  267. qca->tx_vote = false;
  268. qca->tx_votes_off++;
  269. break;
  270. case HCI_IBS_RX_VOTE_CLOCK_OFF:
  271. qca->rx_vote = false;
  272. qca->rx_votes_off++;
  273. break;
  274. default:
  275. BT_ERR("Voting irregularity");
  276. return;
  277. }
  278. new_vote = qca->rx_vote | qca->tx_vote;
  279. if (new_vote != old_vote) {
  280. if (new_vote)
  281. __serial_clock_on(hu->tty);
  282. else
  283. __serial_clock_off(hu->tty);
  284. BT_DBG("Vote serial clock %s(%s)", new_vote ? "true" : "false",
  285. vote ? "true" : "false");
  286. diff = jiffies_to_msecs(jiffies - qca->vote_last_jif);
  287. if (new_vote) {
  288. qca->votes_on++;
  289. qca->vote_off_ms += diff;
  290. } else {
  291. qca->votes_off++;
  292. qca->vote_on_ms += diff;
  293. }
  294. qca->vote_last_jif = jiffies;
  295. }
  296. }
  297. /* Builds and sends an HCI_IBS command packet.
  298. * These are very simple packets with only 1 cmd byte.
  299. */
  300. static int send_hci_ibs_cmd(u8 cmd, struct hci_uart *hu)
  301. {
  302. int err = 0;
  303. struct sk_buff *skb = NULL;
  304. struct qca_data *qca = hu->priv;
  305. BT_DBG("hu %p send hci ibs cmd 0x%x", hu, cmd);
  306. skb = bt_skb_alloc(1, GFP_ATOMIC);
  307. if (!skb) {
  308. BT_ERR("Failed to allocate memory for HCI_IBS packet");
  309. return -ENOMEM;
  310. }
  311. /* Assign HCI_IBS type */
  312. skb_put_u8(skb, cmd);
  313. skb_queue_tail(&qca->txq, skb);
  314. return err;
  315. }
  316. static void qca_wq_awake_device(struct work_struct *work)
  317. {
  318. struct qca_data *qca = container_of(work, struct qca_data,
  319. ws_awake_device);
  320. struct hci_uart *hu = qca->hu;
  321. unsigned long retrans_delay;
  322. unsigned long flags;
  323. BT_DBG("hu %p wq awake device", hu);
  324. /* Vote for serial clock */
  325. serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_ON, hu);
  326. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  327. /* Send wake indication to device */
  328. if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0)
  329. BT_ERR("Failed to send WAKE to device");
  330. qca->ibs_sent_wakes++;
  331. /* Start retransmit timer */
  332. retrans_delay = msecs_to_jiffies(qca->wake_retrans);
  333. mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay);
  334. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  335. /* Actually send the packets */
  336. hci_uart_tx_wakeup(hu);
  337. }
  338. static void qca_wq_awake_rx(struct work_struct *work)
  339. {
  340. struct qca_data *qca = container_of(work, struct qca_data,
  341. ws_awake_rx);
  342. struct hci_uart *hu = qca->hu;
  343. unsigned long flags;
  344. BT_DBG("hu %p wq awake rx", hu);
  345. serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_ON, hu);
  346. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  347. qca->rx_ibs_state = HCI_IBS_RX_AWAKE;
  348. /* Always acknowledge device wake up,
  349. * sending IBS message doesn't count as TX ON.
  350. */
  351. if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0)
  352. BT_ERR("Failed to acknowledge device wake up");
  353. qca->ibs_sent_wacks++;
  354. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  355. /* Actually send the packets */
  356. hci_uart_tx_wakeup(hu);
  357. }
  358. static void qca_wq_serial_rx_clock_vote_off(struct work_struct *work)
  359. {
  360. struct qca_data *qca = container_of(work, struct qca_data,
  361. ws_rx_vote_off);
  362. struct hci_uart *hu = qca->hu;
  363. BT_DBG("hu %p rx clock vote off", hu);
  364. serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_OFF, hu);
  365. }
  366. static void qca_wq_serial_tx_clock_vote_off(struct work_struct *work)
  367. {
  368. struct qca_data *qca = container_of(work, struct qca_data,
  369. ws_tx_vote_off);
  370. struct hci_uart *hu = qca->hu;
  371. BT_DBG("hu %p tx clock vote off", hu);
  372. /* Run HCI tx handling unlocked */
  373. hci_uart_tx_wakeup(hu);
  374. /* Now that message queued to tty driver, vote for tty clocks off.
  375. * It is up to the tty driver to pend the clocks off until tx done.
  376. */
  377. serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
  378. }
  379. static void hci_ibs_tx_idle_timeout(struct timer_list *t)
  380. {
  381. struct qca_data *qca = from_timer(qca, t, tx_idle_timer);
  382. struct hci_uart *hu = qca->hu;
  383. unsigned long flags;
  384. BT_DBG("hu %p idle timeout in %d state", hu, qca->tx_ibs_state);
  385. spin_lock_irqsave_nested(&qca->hci_ibs_lock,
  386. flags, SINGLE_DEPTH_NESTING);
  387. switch (qca->tx_ibs_state) {
  388. case HCI_IBS_TX_AWAKE:
  389. /* TX_IDLE, go to SLEEP */
  390. if (send_hci_ibs_cmd(HCI_IBS_SLEEP_IND, hu) < 0) {
  391. BT_ERR("Failed to send SLEEP to device");
  392. break;
  393. }
  394. qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
  395. qca->ibs_sent_slps++;
  396. queue_work(qca->workqueue, &qca->ws_tx_vote_off);
  397. break;
  398. case HCI_IBS_TX_ASLEEP:
  399. case HCI_IBS_TX_WAKING:
  400. default:
  401. BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state);
  402. break;
  403. }
  404. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  405. }
  406. static void hci_ibs_wake_retrans_timeout(struct timer_list *t)
  407. {
  408. struct qca_data *qca = from_timer(qca, t, wake_retrans_timer);
  409. struct hci_uart *hu = qca->hu;
  410. unsigned long flags, retrans_delay;
  411. bool retransmit = false;
  412. BT_DBG("hu %p wake retransmit timeout in %d state",
  413. hu, qca->tx_ibs_state);
  414. spin_lock_irqsave_nested(&qca->hci_ibs_lock,
  415. flags, SINGLE_DEPTH_NESTING);
  416. /* Don't retransmit the HCI_IBS_WAKE_IND when suspending. */
  417. if (test_bit(QCA_SUSPENDING, &qca->flags)) {
  418. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  419. return;
  420. }
  421. switch (qca->tx_ibs_state) {
  422. case HCI_IBS_TX_WAKING:
  423. /* No WAKE_ACK, retransmit WAKE */
  424. retransmit = true;
  425. if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0) {
  426. BT_ERR("Failed to acknowledge device wake up");
  427. break;
  428. }
  429. qca->ibs_sent_wakes++;
  430. retrans_delay = msecs_to_jiffies(qca->wake_retrans);
  431. mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay);
  432. break;
  433. case HCI_IBS_TX_ASLEEP:
  434. case HCI_IBS_TX_AWAKE:
  435. default:
  436. BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state);
  437. break;
  438. }
  439. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  440. if (retransmit)
  441. hci_uart_tx_wakeup(hu);
  442. }
  443. static void qca_controller_memdump_timeout(struct work_struct *work)
  444. {
  445. struct qca_data *qca = container_of(work, struct qca_data,
  446. ctrl_memdump_timeout.work);
  447. struct hci_uart *hu = qca->hu;
  448. mutex_lock(&qca->hci_memdump_lock);
  449. if (test_bit(QCA_MEMDUMP_COLLECTION, &qca->flags)) {
  450. qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
  451. if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) {
  452. /* Inject hw error event to reset the device
  453. * and driver.
  454. */
  455. hci_reset_dev(hu->hdev);
  456. }
  457. }
  458. mutex_unlock(&qca->hci_memdump_lock);
  459. }
  460. /* Initialize protocol */
  461. static int qca_open(struct hci_uart *hu)
  462. {
  463. struct qca_serdev *qcadev;
  464. struct qca_data *qca;
  465. BT_DBG("hu %p qca_open", hu);
  466. if (!hci_uart_has_flow_control(hu))
  467. return -EOPNOTSUPP;
  468. qca = kzalloc(sizeof(struct qca_data), GFP_KERNEL);
  469. if (!qca)
  470. return -ENOMEM;
  471. skb_queue_head_init(&qca->txq);
  472. skb_queue_head_init(&qca->tx_wait_q);
  473. skb_queue_head_init(&qca->rx_memdump_q);
  474. spin_lock_init(&qca->hci_ibs_lock);
  475. mutex_init(&qca->hci_memdump_lock);
  476. qca->workqueue = alloc_ordered_workqueue("qca_wq", 0);
  477. if (!qca->workqueue) {
  478. BT_ERR("QCA Workqueue not initialized properly");
  479. kfree(qca);
  480. return -ENOMEM;
  481. }
  482. INIT_WORK(&qca->ws_awake_rx, qca_wq_awake_rx);
  483. INIT_WORK(&qca->ws_awake_device, qca_wq_awake_device);
  484. INIT_WORK(&qca->ws_rx_vote_off, qca_wq_serial_rx_clock_vote_off);
  485. INIT_WORK(&qca->ws_tx_vote_off, qca_wq_serial_tx_clock_vote_off);
  486. INIT_WORK(&qca->ctrl_memdump_evt, qca_controller_memdump);
  487. INIT_DELAYED_WORK(&qca->ctrl_memdump_timeout,
  488. qca_controller_memdump_timeout);
  489. init_waitqueue_head(&qca->suspend_wait_q);
  490. qca->hu = hu;
  491. init_completion(&qca->drop_ev_comp);
  492. /* Assume we start with both sides asleep -- extra wakes OK */
  493. qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
  494. qca->rx_ibs_state = HCI_IBS_RX_ASLEEP;
  495. qca->vote_last_jif = jiffies;
  496. hu->priv = qca;
  497. if (hu->serdev) {
  498. qcadev = serdev_device_get_drvdata(hu->serdev);
  499. if (qca_is_wcn399x(qcadev->btsoc_type) ||
  500. qca_is_wcn6750(qcadev->btsoc_type))
  501. hu->init_speed = qcadev->init_speed;
  502. if (qcadev->oper_speed)
  503. hu->oper_speed = qcadev->oper_speed;
  504. }
  505. timer_setup(&qca->wake_retrans_timer, hci_ibs_wake_retrans_timeout, 0);
  506. qca->wake_retrans = IBS_WAKE_RETRANS_TIMEOUT_MS;
  507. timer_setup(&qca->tx_idle_timer, hci_ibs_tx_idle_timeout, 0);
  508. qca->tx_idle_delay = IBS_HOST_TX_IDLE_TIMEOUT_MS;
  509. BT_DBG("HCI_UART_QCA open, tx_idle_delay=%u, wake_retrans=%u",
  510. qca->tx_idle_delay, qca->wake_retrans);
  511. return 0;
  512. }
  513. static void qca_debugfs_init(struct hci_dev *hdev)
  514. {
  515. struct hci_uart *hu = hci_get_drvdata(hdev);
  516. struct qca_data *qca = hu->priv;
  517. struct dentry *ibs_dir;
  518. umode_t mode;
  519. if (!hdev->debugfs)
  520. return;
  521. if (test_and_set_bit(QCA_DEBUGFS_CREATED, &qca->flags))
  522. return;
  523. ibs_dir = debugfs_create_dir("ibs", hdev->debugfs);
  524. /* read only */
  525. mode = 0444;
  526. debugfs_create_u8("tx_ibs_state", mode, ibs_dir, &qca->tx_ibs_state);
  527. debugfs_create_u8("rx_ibs_state", mode, ibs_dir, &qca->rx_ibs_state);
  528. debugfs_create_u64("ibs_sent_sleeps", mode, ibs_dir,
  529. &qca->ibs_sent_slps);
  530. debugfs_create_u64("ibs_sent_wakes", mode, ibs_dir,
  531. &qca->ibs_sent_wakes);
  532. debugfs_create_u64("ibs_sent_wake_acks", mode, ibs_dir,
  533. &qca->ibs_sent_wacks);
  534. debugfs_create_u64("ibs_recv_sleeps", mode, ibs_dir,
  535. &qca->ibs_recv_slps);
  536. debugfs_create_u64("ibs_recv_wakes", mode, ibs_dir,
  537. &qca->ibs_recv_wakes);
  538. debugfs_create_u64("ibs_recv_wake_acks", mode, ibs_dir,
  539. &qca->ibs_recv_wacks);
  540. debugfs_create_bool("tx_vote", mode, ibs_dir, &qca->tx_vote);
  541. debugfs_create_u64("tx_votes_on", mode, ibs_dir, &qca->tx_votes_on);
  542. debugfs_create_u64("tx_votes_off", mode, ibs_dir, &qca->tx_votes_off);
  543. debugfs_create_bool("rx_vote", mode, ibs_dir, &qca->rx_vote);
  544. debugfs_create_u64("rx_votes_on", mode, ibs_dir, &qca->rx_votes_on);
  545. debugfs_create_u64("rx_votes_off", mode, ibs_dir, &qca->rx_votes_off);
  546. debugfs_create_u64("votes_on", mode, ibs_dir, &qca->votes_on);
  547. debugfs_create_u64("votes_off", mode, ibs_dir, &qca->votes_off);
  548. debugfs_create_u32("vote_on_ms", mode, ibs_dir, &qca->vote_on_ms);
  549. debugfs_create_u32("vote_off_ms", mode, ibs_dir, &qca->vote_off_ms);
  550. /* read/write */
  551. mode = 0644;
  552. debugfs_create_u32("wake_retrans", mode, ibs_dir, &qca->wake_retrans);
  553. debugfs_create_u32("tx_idle_delay", mode, ibs_dir,
  554. &qca->tx_idle_delay);
  555. }
  556. /* Flush protocol data */
  557. static int qca_flush(struct hci_uart *hu)
  558. {
  559. struct qca_data *qca = hu->priv;
  560. BT_DBG("hu %p qca flush", hu);
  561. skb_queue_purge(&qca->tx_wait_q);
  562. skb_queue_purge(&qca->txq);
  563. return 0;
  564. }
  565. /* Close protocol */
  566. static int qca_close(struct hci_uart *hu)
  567. {
  568. struct qca_data *qca = hu->priv;
  569. BT_DBG("hu %p qca close", hu);
  570. serial_clock_vote(HCI_IBS_VOTE_STATS_UPDATE, hu);
  571. skb_queue_purge(&qca->tx_wait_q);
  572. skb_queue_purge(&qca->txq);
  573. skb_queue_purge(&qca->rx_memdump_q);
  574. destroy_workqueue(qca->workqueue);
  575. del_timer_sync(&qca->tx_idle_timer);
  576. del_timer_sync(&qca->wake_retrans_timer);
  577. qca->hu = NULL;
  578. kfree_skb(qca->rx_skb);
  579. hu->priv = NULL;
  580. kfree(qca);
  581. return 0;
  582. }
  583. /* Called upon a wake-up-indication from the device.
  584. */
  585. static void device_want_to_wakeup(struct hci_uart *hu)
  586. {
  587. unsigned long flags;
  588. struct qca_data *qca = hu->priv;
  589. BT_DBG("hu %p want to wake up", hu);
  590. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  591. qca->ibs_recv_wakes++;
  592. /* Don't wake the rx up when suspending. */
  593. if (test_bit(QCA_SUSPENDING, &qca->flags)) {
  594. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  595. return;
  596. }
  597. switch (qca->rx_ibs_state) {
  598. case HCI_IBS_RX_ASLEEP:
  599. /* Make sure clock is on - we may have turned clock off since
  600. * receiving the wake up indicator awake rx clock.
  601. */
  602. queue_work(qca->workqueue, &qca->ws_awake_rx);
  603. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  604. return;
  605. case HCI_IBS_RX_AWAKE:
  606. /* Always acknowledge device wake up,
  607. * sending IBS message doesn't count as TX ON.
  608. */
  609. if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0) {
  610. BT_ERR("Failed to acknowledge device wake up");
  611. break;
  612. }
  613. qca->ibs_sent_wacks++;
  614. break;
  615. default:
  616. /* Any other state is illegal */
  617. BT_ERR("Received HCI_IBS_WAKE_IND in rx state %d",
  618. qca->rx_ibs_state);
  619. break;
  620. }
  621. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  622. /* Actually send the packets */
  623. hci_uart_tx_wakeup(hu);
  624. }
  625. /* Called upon a sleep-indication from the device.
  626. */
  627. static void device_want_to_sleep(struct hci_uart *hu)
  628. {
  629. unsigned long flags;
  630. struct qca_data *qca = hu->priv;
  631. BT_DBG("hu %p want to sleep in %d state", hu, qca->rx_ibs_state);
  632. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  633. qca->ibs_recv_slps++;
  634. switch (qca->rx_ibs_state) {
  635. case HCI_IBS_RX_AWAKE:
  636. /* Update state */
  637. qca->rx_ibs_state = HCI_IBS_RX_ASLEEP;
  638. /* Vote off rx clock under workqueue */
  639. queue_work(qca->workqueue, &qca->ws_rx_vote_off);
  640. break;
  641. case HCI_IBS_RX_ASLEEP:
  642. break;
  643. default:
  644. /* Any other state is illegal */
  645. BT_ERR("Received HCI_IBS_SLEEP_IND in rx state %d",
  646. qca->rx_ibs_state);
  647. break;
  648. }
  649. wake_up_interruptible(&qca->suspend_wait_q);
  650. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  651. }
  652. /* Called upon wake-up-acknowledgement from the device
  653. */
  654. static void device_woke_up(struct hci_uart *hu)
  655. {
  656. unsigned long flags, idle_delay;
  657. struct qca_data *qca = hu->priv;
  658. struct sk_buff *skb = NULL;
  659. BT_DBG("hu %p woke up", hu);
  660. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  661. qca->ibs_recv_wacks++;
  662. /* Don't react to the wake-up-acknowledgment when suspending. */
  663. if (test_bit(QCA_SUSPENDING, &qca->flags)) {
  664. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  665. return;
  666. }
  667. switch (qca->tx_ibs_state) {
  668. case HCI_IBS_TX_AWAKE:
  669. /* Expect one if we send 2 WAKEs */
  670. BT_DBG("Received HCI_IBS_WAKE_ACK in tx state %d",
  671. qca->tx_ibs_state);
  672. break;
  673. case HCI_IBS_TX_WAKING:
  674. /* Send pending packets */
  675. while ((skb = skb_dequeue(&qca->tx_wait_q)))
  676. skb_queue_tail(&qca->txq, skb);
  677. /* Switch timers and change state to HCI_IBS_TX_AWAKE */
  678. del_timer(&qca->wake_retrans_timer);
  679. idle_delay = msecs_to_jiffies(qca->tx_idle_delay);
  680. mod_timer(&qca->tx_idle_timer, jiffies + idle_delay);
  681. qca->tx_ibs_state = HCI_IBS_TX_AWAKE;
  682. break;
  683. case HCI_IBS_TX_ASLEEP:
  684. default:
  685. BT_ERR("Received HCI_IBS_WAKE_ACK in tx state %d",
  686. qca->tx_ibs_state);
  687. break;
  688. }
  689. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  690. /* Actually send the packets */
  691. hci_uart_tx_wakeup(hu);
  692. }
  693. /* Enqueue frame for transmittion (padding, crc, etc) may be called from
  694. * two simultaneous tasklets.
  695. */
  696. static int qca_enqueue(struct hci_uart *hu, struct sk_buff *skb)
  697. {
  698. unsigned long flags = 0, idle_delay;
  699. struct qca_data *qca = hu->priv;
  700. BT_DBG("hu %p qca enq skb %p tx_ibs_state %d", hu, skb,
  701. qca->tx_ibs_state);
  702. if (test_bit(QCA_SSR_TRIGGERED, &qca->flags)) {
  703. /* As SSR is in progress, ignore the packets */
  704. bt_dev_dbg(hu->hdev, "SSR is in progress");
  705. kfree_skb(skb);
  706. return 0;
  707. }
  708. /* Prepend skb with frame type */
  709. memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1);
  710. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  711. /* Don't go to sleep in middle of patch download or
  712. * Out-Of-Band(GPIOs control) sleep is selected.
  713. * Don't wake the device up when suspending.
  714. */
  715. if (test_bit(QCA_IBS_DISABLED, &qca->flags) ||
  716. test_bit(QCA_SUSPENDING, &qca->flags)) {
  717. skb_queue_tail(&qca->txq, skb);
  718. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  719. return 0;
  720. }
  721. /* Act according to current state */
  722. switch (qca->tx_ibs_state) {
  723. case HCI_IBS_TX_AWAKE:
  724. BT_DBG("Device awake, sending normally");
  725. skb_queue_tail(&qca->txq, skb);
  726. idle_delay = msecs_to_jiffies(qca->tx_idle_delay);
  727. mod_timer(&qca->tx_idle_timer, jiffies + idle_delay);
  728. break;
  729. case HCI_IBS_TX_ASLEEP:
  730. BT_DBG("Device asleep, waking up and queueing packet");
  731. /* Save packet for later */
  732. skb_queue_tail(&qca->tx_wait_q, skb);
  733. qca->tx_ibs_state = HCI_IBS_TX_WAKING;
  734. /* Schedule a work queue to wake up device */
  735. queue_work(qca->workqueue, &qca->ws_awake_device);
  736. break;
  737. case HCI_IBS_TX_WAKING:
  738. BT_DBG("Device waking up, queueing packet");
  739. /* Transient state; just keep packet for later */
  740. skb_queue_tail(&qca->tx_wait_q, skb);
  741. break;
  742. default:
  743. BT_ERR("Illegal tx state: %d (losing packet)",
  744. qca->tx_ibs_state);
  745. dev_kfree_skb_irq(skb);
  746. break;
  747. }
  748. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  749. return 0;
  750. }
  751. static int qca_ibs_sleep_ind(struct hci_dev *hdev, struct sk_buff *skb)
  752. {
  753. struct hci_uart *hu = hci_get_drvdata(hdev);
  754. BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_SLEEP_IND);
  755. device_want_to_sleep(hu);
  756. kfree_skb(skb);
  757. return 0;
  758. }
  759. static int qca_ibs_wake_ind(struct hci_dev *hdev, struct sk_buff *skb)
  760. {
  761. struct hci_uart *hu = hci_get_drvdata(hdev);
  762. BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_IND);
  763. device_want_to_wakeup(hu);
  764. kfree_skb(skb);
  765. return 0;
  766. }
  767. static int qca_ibs_wake_ack(struct hci_dev *hdev, struct sk_buff *skb)
  768. {
  769. struct hci_uart *hu = hci_get_drvdata(hdev);
  770. BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_ACK);
  771. device_woke_up(hu);
  772. kfree_skb(skb);
  773. return 0;
  774. }
  775. static int qca_recv_acl_data(struct hci_dev *hdev, struct sk_buff *skb)
  776. {
  777. /* We receive debug logs from chip as an ACL packets.
  778. * Instead of sending the data to ACL to decode the
  779. * received data, we are pushing them to the above layers
  780. * as a diagnostic packet.
  781. */
  782. if (get_unaligned_le16(skb->data) == QCA_DEBUG_HANDLE)
  783. return hci_recv_diag(hdev, skb);
  784. return hci_recv_frame(hdev, skb);
  785. }
  786. static void qca_controller_memdump(struct work_struct *work)
  787. {
  788. struct qca_data *qca = container_of(work, struct qca_data,
  789. ctrl_memdump_evt);
  790. struct hci_uart *hu = qca->hu;
  791. struct sk_buff *skb;
  792. struct qca_memdump_event_hdr *cmd_hdr;
  793. struct qca_memdump_data *qca_memdump = qca->qca_memdump;
  794. struct qca_dump_size *dump;
  795. char *memdump_buf;
  796. char nullBuff[QCA_DUMP_PACKET_SIZE] = { 0 };
  797. u16 seq_no;
  798. u32 dump_size;
  799. u32 rx_size;
  800. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  801. while ((skb = skb_dequeue(&qca->rx_memdump_q))) {
  802. mutex_lock(&qca->hci_memdump_lock);
  803. /* Skip processing the received packets if timeout detected
  804. * or memdump collection completed.
  805. */
  806. if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT ||
  807. qca->memdump_state == QCA_MEMDUMP_COLLECTED) {
  808. mutex_unlock(&qca->hci_memdump_lock);
  809. return;
  810. }
  811. if (!qca_memdump) {
  812. qca_memdump = kzalloc(sizeof(struct qca_memdump_data),
  813. GFP_ATOMIC);
  814. if (!qca_memdump) {
  815. mutex_unlock(&qca->hci_memdump_lock);
  816. return;
  817. }
  818. qca->qca_memdump = qca_memdump;
  819. }
  820. qca->memdump_state = QCA_MEMDUMP_COLLECTING;
  821. cmd_hdr = (void *) skb->data;
  822. seq_no = __le16_to_cpu(cmd_hdr->seq_no);
  823. skb_pull(skb, sizeof(struct qca_memdump_event_hdr));
  824. if (!seq_no) {
  825. /* This is the first frame of memdump packet from
  826. * the controller, Disable IBS to recevie dump
  827. * with out any interruption, ideally time required for
  828. * the controller to send the dump is 8 seconds. let us
  829. * start timer to handle this asynchronous activity.
  830. */
  831. set_bit(QCA_IBS_DISABLED, &qca->flags);
  832. set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  833. dump = (void *) skb->data;
  834. dump_size = __le32_to_cpu(dump->dump_size);
  835. if (!(dump_size)) {
  836. bt_dev_err(hu->hdev, "Rx invalid memdump size");
  837. kfree(qca_memdump);
  838. kfree_skb(skb);
  839. qca->qca_memdump = NULL;
  840. mutex_unlock(&qca->hci_memdump_lock);
  841. return;
  842. }
  843. bt_dev_info(hu->hdev, "QCA collecting dump of size:%u",
  844. dump_size);
  845. queue_delayed_work(qca->workqueue,
  846. &qca->ctrl_memdump_timeout,
  847. msecs_to_jiffies(MEMDUMP_TIMEOUT_MS)
  848. );
  849. skb_pull(skb, sizeof(dump_size));
  850. memdump_buf = vmalloc(dump_size);
  851. qca_memdump->ram_dump_size = dump_size;
  852. qca_memdump->memdump_buf_head = memdump_buf;
  853. qca_memdump->memdump_buf_tail = memdump_buf;
  854. }
  855. memdump_buf = qca_memdump->memdump_buf_tail;
  856. /* If sequence no 0 is missed then there is no point in
  857. * accepting the other sequences.
  858. */
  859. if (!memdump_buf) {
  860. bt_dev_err(hu->hdev, "QCA: Discarding other packets");
  861. kfree(qca_memdump);
  862. kfree_skb(skb);
  863. qca->qca_memdump = NULL;
  864. mutex_unlock(&qca->hci_memdump_lock);
  865. return;
  866. }
  867. /* There could be chance of missing some packets from
  868. * the controller. In such cases let us store the dummy
  869. * packets in the buffer.
  870. */
  871. /* For QCA6390, controller does not lost packets but
  872. * sequence number field of packet sometimes has error
  873. * bits, so skip this checking for missing packet.
  874. */
  875. while ((seq_no > qca_memdump->current_seq_no + 1) &&
  876. (soc_type != QCA_QCA6390) &&
  877. seq_no != QCA_LAST_SEQUENCE_NUM) {
  878. bt_dev_err(hu->hdev, "QCA controller missed packet:%d",
  879. qca_memdump->current_seq_no);
  880. rx_size = qca_memdump->received_dump;
  881. rx_size += QCA_DUMP_PACKET_SIZE;
  882. if (rx_size > qca_memdump->ram_dump_size) {
  883. bt_dev_err(hu->hdev,
  884. "QCA memdump received %d, no space for missed packet",
  885. qca_memdump->received_dump);
  886. break;
  887. }
  888. memcpy(memdump_buf, nullBuff, QCA_DUMP_PACKET_SIZE);
  889. memdump_buf = memdump_buf + QCA_DUMP_PACKET_SIZE;
  890. qca_memdump->received_dump += QCA_DUMP_PACKET_SIZE;
  891. qca_memdump->current_seq_no++;
  892. }
  893. rx_size = qca_memdump->received_dump + skb->len;
  894. if (rx_size <= qca_memdump->ram_dump_size) {
  895. if ((seq_no != QCA_LAST_SEQUENCE_NUM) &&
  896. (seq_no != qca_memdump->current_seq_no))
  897. bt_dev_err(hu->hdev,
  898. "QCA memdump unexpected packet %d",
  899. seq_no);
  900. bt_dev_dbg(hu->hdev,
  901. "QCA memdump packet %d with length %d",
  902. seq_no, skb->len);
  903. memcpy(memdump_buf, (unsigned char *)skb->data,
  904. skb->len);
  905. memdump_buf = memdump_buf + skb->len;
  906. qca_memdump->memdump_buf_tail = memdump_buf;
  907. qca_memdump->current_seq_no = seq_no + 1;
  908. qca_memdump->received_dump += skb->len;
  909. } else {
  910. bt_dev_err(hu->hdev,
  911. "QCA memdump received %d, no space for packet %d",
  912. qca_memdump->received_dump, seq_no);
  913. }
  914. qca->qca_memdump = qca_memdump;
  915. kfree_skb(skb);
  916. if (seq_no == QCA_LAST_SEQUENCE_NUM) {
  917. bt_dev_info(hu->hdev,
  918. "QCA memdump Done, received %d, total %d",
  919. qca_memdump->received_dump,
  920. qca_memdump->ram_dump_size);
  921. memdump_buf = qca_memdump->memdump_buf_head;
  922. dev_coredumpv(&hu->serdev->dev, memdump_buf,
  923. qca_memdump->received_dump, GFP_KERNEL);
  924. cancel_delayed_work(&qca->ctrl_memdump_timeout);
  925. kfree(qca->qca_memdump);
  926. qca->qca_memdump = NULL;
  927. qca->memdump_state = QCA_MEMDUMP_COLLECTED;
  928. clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  929. }
  930. mutex_unlock(&qca->hci_memdump_lock);
  931. }
  932. }
  933. static int qca_controller_memdump_event(struct hci_dev *hdev,
  934. struct sk_buff *skb)
  935. {
  936. struct hci_uart *hu = hci_get_drvdata(hdev);
  937. struct qca_data *qca = hu->priv;
  938. set_bit(QCA_SSR_TRIGGERED, &qca->flags);
  939. skb_queue_tail(&qca->rx_memdump_q, skb);
  940. queue_work(qca->workqueue, &qca->ctrl_memdump_evt);
  941. return 0;
  942. }
  943. static int qca_recv_event(struct hci_dev *hdev, struct sk_buff *skb)
  944. {
  945. struct hci_uart *hu = hci_get_drvdata(hdev);
  946. struct qca_data *qca = hu->priv;
  947. if (test_bit(QCA_DROP_VENDOR_EVENT, &qca->flags)) {
  948. struct hci_event_hdr *hdr = (void *)skb->data;
  949. /* For the WCN3990 the vendor command for a baudrate change
  950. * isn't sent as synchronous HCI command, because the
  951. * controller sends the corresponding vendor event with the
  952. * new baudrate. The event is received and properly decoded
  953. * after changing the baudrate of the host port. It needs to
  954. * be dropped, otherwise it can be misinterpreted as
  955. * response to a later firmware download command (also a
  956. * vendor command).
  957. */
  958. if (hdr->evt == HCI_EV_VENDOR)
  959. complete(&qca->drop_ev_comp);
  960. kfree_skb(skb);
  961. return 0;
  962. }
  963. /* We receive chip memory dump as an event packet, With a dedicated
  964. * handler followed by a hardware error event. When this event is
  965. * received we store dump into a file before closing hci. This
  966. * dump will help in triaging the issues.
  967. */
  968. if ((skb->data[0] == HCI_VENDOR_PKT) &&
  969. (get_unaligned_be16(skb->data + 2) == QCA_SSR_DUMP_HANDLE))
  970. return qca_controller_memdump_event(hdev, skb);
  971. return hci_recv_frame(hdev, skb);
  972. }
  973. #define QCA_IBS_SLEEP_IND_EVENT \
  974. .type = HCI_IBS_SLEEP_IND, \
  975. .hlen = 0, \
  976. .loff = 0, \
  977. .lsize = 0, \
  978. .maxlen = HCI_MAX_IBS_SIZE
  979. #define QCA_IBS_WAKE_IND_EVENT \
  980. .type = HCI_IBS_WAKE_IND, \
  981. .hlen = 0, \
  982. .loff = 0, \
  983. .lsize = 0, \
  984. .maxlen = HCI_MAX_IBS_SIZE
  985. #define QCA_IBS_WAKE_ACK_EVENT \
  986. .type = HCI_IBS_WAKE_ACK, \
  987. .hlen = 0, \
  988. .loff = 0, \
  989. .lsize = 0, \
  990. .maxlen = HCI_MAX_IBS_SIZE
  991. static const struct h4_recv_pkt qca_recv_pkts[] = {
  992. { H4_RECV_ACL, .recv = qca_recv_acl_data },
  993. { H4_RECV_SCO, .recv = hci_recv_frame },
  994. { H4_RECV_EVENT, .recv = qca_recv_event },
  995. { QCA_IBS_WAKE_IND_EVENT, .recv = qca_ibs_wake_ind },
  996. { QCA_IBS_WAKE_ACK_EVENT, .recv = qca_ibs_wake_ack },
  997. { QCA_IBS_SLEEP_IND_EVENT, .recv = qca_ibs_sleep_ind },
  998. };
  999. static int qca_recv(struct hci_uart *hu, const void *data, int count)
  1000. {
  1001. struct qca_data *qca = hu->priv;
  1002. if (!test_bit(HCI_UART_REGISTERED, &hu->flags))
  1003. return -EUNATCH;
  1004. qca->rx_skb = h4_recv_buf(hu->hdev, qca->rx_skb, data, count,
  1005. qca_recv_pkts, ARRAY_SIZE(qca_recv_pkts));
  1006. if (IS_ERR(qca->rx_skb)) {
  1007. int err = PTR_ERR(qca->rx_skb);
  1008. bt_dev_err(hu->hdev, "Frame reassembly failed (%d)", err);
  1009. qca->rx_skb = NULL;
  1010. return err;
  1011. }
  1012. return count;
  1013. }
  1014. static struct sk_buff *qca_dequeue(struct hci_uart *hu)
  1015. {
  1016. struct qca_data *qca = hu->priv;
  1017. return skb_dequeue(&qca->txq);
  1018. }
  1019. static uint8_t qca_get_baudrate_value(int speed)
  1020. {
  1021. switch (speed) {
  1022. case 9600:
  1023. return QCA_BAUDRATE_9600;
  1024. case 19200:
  1025. return QCA_BAUDRATE_19200;
  1026. case 38400:
  1027. return QCA_BAUDRATE_38400;
  1028. case 57600:
  1029. return QCA_BAUDRATE_57600;
  1030. case 115200:
  1031. return QCA_BAUDRATE_115200;
  1032. case 230400:
  1033. return QCA_BAUDRATE_230400;
  1034. case 460800:
  1035. return QCA_BAUDRATE_460800;
  1036. case 500000:
  1037. return QCA_BAUDRATE_500000;
  1038. case 921600:
  1039. return QCA_BAUDRATE_921600;
  1040. case 1000000:
  1041. return QCA_BAUDRATE_1000000;
  1042. case 2000000:
  1043. return QCA_BAUDRATE_2000000;
  1044. case 3000000:
  1045. return QCA_BAUDRATE_3000000;
  1046. case 3200000:
  1047. return QCA_BAUDRATE_3200000;
  1048. case 3500000:
  1049. return QCA_BAUDRATE_3500000;
  1050. default:
  1051. return QCA_BAUDRATE_115200;
  1052. }
  1053. }
  1054. static int qca_set_baudrate(struct hci_dev *hdev, uint8_t baudrate)
  1055. {
  1056. struct hci_uart *hu = hci_get_drvdata(hdev);
  1057. struct qca_data *qca = hu->priv;
  1058. struct sk_buff *skb;
  1059. u8 cmd[] = { 0x01, 0x48, 0xFC, 0x01, 0x00 };
  1060. if (baudrate > QCA_BAUDRATE_3200000)
  1061. return -EINVAL;
  1062. cmd[4] = baudrate;
  1063. skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL);
  1064. if (!skb) {
  1065. bt_dev_err(hdev, "Failed to allocate baudrate packet");
  1066. return -ENOMEM;
  1067. }
  1068. /* Assign commands to change baudrate and packet type. */
  1069. skb_put_data(skb, cmd, sizeof(cmd));
  1070. hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
  1071. skb_queue_tail(&qca->txq, skb);
  1072. hci_uart_tx_wakeup(hu);
  1073. /* Wait for the baudrate change request to be sent */
  1074. while (!skb_queue_empty(&qca->txq))
  1075. usleep_range(100, 200);
  1076. if (hu->serdev)
  1077. serdev_device_wait_until_sent(hu->serdev,
  1078. msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS));
  1079. /* Give the controller time to process the request */
  1080. if (qca_is_wcn399x(qca_soc_type(hu)) ||
  1081. qca_is_wcn6750(qca_soc_type(hu)))
  1082. usleep_range(1000, 10000);
  1083. else
  1084. msleep(300);
  1085. return 0;
  1086. }
  1087. static inline void host_set_baudrate(struct hci_uart *hu, unsigned int speed)
  1088. {
  1089. if (hu->serdev)
  1090. serdev_device_set_baudrate(hu->serdev, speed);
  1091. else
  1092. hci_uart_set_baudrate(hu, speed);
  1093. }
  1094. static int qca_send_power_pulse(struct hci_uart *hu, bool on)
  1095. {
  1096. int ret;
  1097. int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS);
  1098. u8 cmd = on ? QCA_WCN3990_POWERON_PULSE : QCA_WCN3990_POWEROFF_PULSE;
  1099. /* These power pulses are single byte command which are sent
  1100. * at required baudrate to wcn3990. On wcn3990, we have an external
  1101. * circuit at Tx pin which decodes the pulse sent at specific baudrate.
  1102. * For example, wcn3990 supports RF COEX antenna for both Wi-Fi/BT
  1103. * and also we use the same power inputs to turn on and off for
  1104. * Wi-Fi/BT. Powering up the power sources will not enable BT, until
  1105. * we send a power on pulse at 115200 bps. This algorithm will help to
  1106. * save power. Disabling hardware flow control is mandatory while
  1107. * sending power pulses to SoC.
  1108. */
  1109. bt_dev_dbg(hu->hdev, "sending power pulse %02x to controller", cmd);
  1110. serdev_device_write_flush(hu->serdev);
  1111. hci_uart_set_flow_control(hu, true);
  1112. ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd));
  1113. if (ret < 0) {
  1114. bt_dev_err(hu->hdev, "failed to send power pulse %02x", cmd);
  1115. return ret;
  1116. }
  1117. serdev_device_wait_until_sent(hu->serdev, timeout);
  1118. hci_uart_set_flow_control(hu, false);
  1119. /* Give to controller time to boot/shutdown */
  1120. if (on)
  1121. msleep(100);
  1122. else
  1123. usleep_range(1000, 10000);
  1124. return 0;
  1125. }
  1126. static unsigned int qca_get_speed(struct hci_uart *hu,
  1127. enum qca_speed_type speed_type)
  1128. {
  1129. unsigned int speed = 0;
  1130. if (speed_type == QCA_INIT_SPEED) {
  1131. if (hu->init_speed)
  1132. speed = hu->init_speed;
  1133. else if (hu->proto->init_speed)
  1134. speed = hu->proto->init_speed;
  1135. } else {
  1136. if (hu->oper_speed)
  1137. speed = hu->oper_speed;
  1138. else if (hu->proto->oper_speed)
  1139. speed = hu->proto->oper_speed;
  1140. }
  1141. return speed;
  1142. }
  1143. static int qca_check_speeds(struct hci_uart *hu)
  1144. {
  1145. if (qca_is_wcn399x(qca_soc_type(hu)) ||
  1146. qca_is_wcn6750(qca_soc_type(hu))) {
  1147. if (!qca_get_speed(hu, QCA_INIT_SPEED) &&
  1148. !qca_get_speed(hu, QCA_OPER_SPEED))
  1149. return -EINVAL;
  1150. } else {
  1151. if (!qca_get_speed(hu, QCA_INIT_SPEED) ||
  1152. !qca_get_speed(hu, QCA_OPER_SPEED))
  1153. return -EINVAL;
  1154. }
  1155. return 0;
  1156. }
  1157. static int qca_set_speed(struct hci_uart *hu, enum qca_speed_type speed_type)
  1158. {
  1159. unsigned int speed, qca_baudrate;
  1160. struct qca_data *qca = hu->priv;
  1161. int ret = 0;
  1162. if (speed_type == QCA_INIT_SPEED) {
  1163. speed = qca_get_speed(hu, QCA_INIT_SPEED);
  1164. if (speed)
  1165. host_set_baudrate(hu, speed);
  1166. } else {
  1167. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1168. speed = qca_get_speed(hu, QCA_OPER_SPEED);
  1169. if (!speed)
  1170. return 0;
  1171. /* Disable flow control for wcn3990 to deassert RTS while
  1172. * changing the baudrate of chip and host.
  1173. */
  1174. if (qca_is_wcn399x(soc_type) ||
  1175. qca_is_wcn6750(soc_type))
  1176. hci_uart_set_flow_control(hu, true);
  1177. if (soc_type == QCA_WCN3990) {
  1178. reinit_completion(&qca->drop_ev_comp);
  1179. set_bit(QCA_DROP_VENDOR_EVENT, &qca->flags);
  1180. }
  1181. qca_baudrate = qca_get_baudrate_value(speed);
  1182. bt_dev_dbg(hu->hdev, "Set UART speed to %d", speed);
  1183. ret = qca_set_baudrate(hu->hdev, qca_baudrate);
  1184. if (ret)
  1185. goto error;
  1186. host_set_baudrate(hu, speed);
  1187. error:
  1188. if (qca_is_wcn399x(soc_type) ||
  1189. qca_is_wcn6750(soc_type))
  1190. hci_uart_set_flow_control(hu, false);
  1191. if (soc_type == QCA_WCN3990) {
  1192. /* Wait for the controller to send the vendor event
  1193. * for the baudrate change command.
  1194. */
  1195. if (!wait_for_completion_timeout(&qca->drop_ev_comp,
  1196. msecs_to_jiffies(100))) {
  1197. bt_dev_err(hu->hdev,
  1198. "Failed to change controller baudrate\n");
  1199. ret = -ETIMEDOUT;
  1200. }
  1201. clear_bit(QCA_DROP_VENDOR_EVENT, &qca->flags);
  1202. }
  1203. }
  1204. return ret;
  1205. }
  1206. static int qca_send_crashbuffer(struct hci_uart *hu)
  1207. {
  1208. struct qca_data *qca = hu->priv;
  1209. struct sk_buff *skb;
  1210. skb = bt_skb_alloc(QCA_CRASHBYTE_PACKET_LEN, GFP_KERNEL);
  1211. if (!skb) {
  1212. bt_dev_err(hu->hdev, "Failed to allocate memory for skb packet");
  1213. return -ENOMEM;
  1214. }
  1215. /* We forcefully crash the controller, by sending 0xfb byte for
  1216. * 1024 times. We also might have chance of losing data, To be
  1217. * on safer side we send 1096 bytes to the SoC.
  1218. */
  1219. memset(skb_put(skb, QCA_CRASHBYTE_PACKET_LEN), QCA_MEMDUMP_BYTE,
  1220. QCA_CRASHBYTE_PACKET_LEN);
  1221. hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
  1222. bt_dev_info(hu->hdev, "crash the soc to collect controller dump");
  1223. skb_queue_tail(&qca->txq, skb);
  1224. hci_uart_tx_wakeup(hu);
  1225. return 0;
  1226. }
  1227. static void qca_wait_for_dump_collection(struct hci_dev *hdev)
  1228. {
  1229. struct hci_uart *hu = hci_get_drvdata(hdev);
  1230. struct qca_data *qca = hu->priv;
  1231. wait_on_bit_timeout(&qca->flags, QCA_MEMDUMP_COLLECTION,
  1232. TASK_UNINTERRUPTIBLE, MEMDUMP_TIMEOUT_MS);
  1233. clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  1234. }
  1235. static void qca_hw_error(struct hci_dev *hdev, u8 code)
  1236. {
  1237. struct hci_uart *hu = hci_get_drvdata(hdev);
  1238. struct qca_data *qca = hu->priv;
  1239. set_bit(QCA_SSR_TRIGGERED, &qca->flags);
  1240. set_bit(QCA_HW_ERROR_EVENT, &qca->flags);
  1241. bt_dev_info(hdev, "mem_dump_status: %d", qca->memdump_state);
  1242. if (qca->memdump_state == QCA_MEMDUMP_IDLE) {
  1243. /* If hardware error event received for other than QCA
  1244. * soc memory dump event, then we need to crash the SOC
  1245. * and wait here for 8 seconds to get the dump packets.
  1246. * This will block main thread to be on hold until we
  1247. * collect dump.
  1248. */
  1249. set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  1250. qca_send_crashbuffer(hu);
  1251. qca_wait_for_dump_collection(hdev);
  1252. } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) {
  1253. /* Let us wait here until memory dump collected or
  1254. * memory dump timer expired.
  1255. */
  1256. bt_dev_info(hdev, "waiting for dump to complete");
  1257. qca_wait_for_dump_collection(hdev);
  1258. }
  1259. mutex_lock(&qca->hci_memdump_lock);
  1260. if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) {
  1261. bt_dev_err(hu->hdev, "clearing allocated memory due to memdump timeout");
  1262. if (qca->qca_memdump) {
  1263. vfree(qca->qca_memdump->memdump_buf_head);
  1264. kfree(qca->qca_memdump);
  1265. qca->qca_memdump = NULL;
  1266. }
  1267. qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
  1268. cancel_delayed_work(&qca->ctrl_memdump_timeout);
  1269. }
  1270. mutex_unlock(&qca->hci_memdump_lock);
  1271. if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT ||
  1272. qca->memdump_state == QCA_MEMDUMP_COLLECTED) {
  1273. cancel_work_sync(&qca->ctrl_memdump_evt);
  1274. skb_queue_purge(&qca->rx_memdump_q);
  1275. }
  1276. clear_bit(QCA_HW_ERROR_EVENT, &qca->flags);
  1277. }
  1278. static void qca_cmd_timeout(struct hci_dev *hdev)
  1279. {
  1280. struct hci_uart *hu = hci_get_drvdata(hdev);
  1281. struct qca_data *qca = hu->priv;
  1282. set_bit(QCA_SSR_TRIGGERED, &qca->flags);
  1283. if (qca->memdump_state == QCA_MEMDUMP_IDLE) {
  1284. set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  1285. qca_send_crashbuffer(hu);
  1286. qca_wait_for_dump_collection(hdev);
  1287. } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) {
  1288. /* Let us wait here until memory dump collected or
  1289. * memory dump timer expired.
  1290. */
  1291. bt_dev_info(hdev, "waiting for dump to complete");
  1292. qca_wait_for_dump_collection(hdev);
  1293. }
  1294. mutex_lock(&qca->hci_memdump_lock);
  1295. if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) {
  1296. qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
  1297. if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) {
  1298. /* Inject hw error event to reset the device
  1299. * and driver.
  1300. */
  1301. hci_reset_dev(hu->hdev);
  1302. }
  1303. }
  1304. mutex_unlock(&qca->hci_memdump_lock);
  1305. }
  1306. static bool qca_wakeup(struct hci_dev *hdev)
  1307. {
  1308. struct hci_uart *hu = hci_get_drvdata(hdev);
  1309. bool wakeup;
  1310. /* BT SoC attached through the serial bus is handled by the serdev driver.
  1311. * So we need to use the device handle of the serdev driver to get the
  1312. * status of device may wakeup.
  1313. */
  1314. wakeup = device_may_wakeup(&hu->serdev->ctrl->dev);
  1315. bt_dev_dbg(hu->hdev, "wakeup status : %d", wakeup);
  1316. return wakeup;
  1317. }
  1318. static int qca_regulator_init(struct hci_uart *hu)
  1319. {
  1320. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1321. struct qca_serdev *qcadev;
  1322. int ret;
  1323. bool sw_ctrl_state;
  1324. /* Check for vregs status, may be hci down has turned
  1325. * off the voltage regulator.
  1326. */
  1327. qcadev = serdev_device_get_drvdata(hu->serdev);
  1328. if (!qcadev->bt_power->vregs_on) {
  1329. serdev_device_close(hu->serdev);
  1330. ret = qca_regulator_enable(qcadev);
  1331. if (ret)
  1332. return ret;
  1333. ret = serdev_device_open(hu->serdev);
  1334. if (ret) {
  1335. bt_dev_err(hu->hdev, "failed to open port");
  1336. return ret;
  1337. }
  1338. }
  1339. if (qca_is_wcn399x(soc_type)) {
  1340. /* Forcefully enable wcn399x to enter in to boot mode. */
  1341. host_set_baudrate(hu, 2400);
  1342. ret = qca_send_power_pulse(hu, false);
  1343. if (ret)
  1344. return ret;
  1345. }
  1346. /* For wcn6750 need to enable gpio bt_en */
  1347. if (qcadev->bt_en) {
  1348. gpiod_set_value_cansleep(qcadev->bt_en, 0);
  1349. msleep(50);
  1350. gpiod_set_value_cansleep(qcadev->bt_en, 1);
  1351. msleep(50);
  1352. if (qcadev->sw_ctrl) {
  1353. sw_ctrl_state = gpiod_get_value_cansleep(qcadev->sw_ctrl);
  1354. bt_dev_dbg(hu->hdev, "SW_CTRL is %d", sw_ctrl_state);
  1355. }
  1356. }
  1357. qca_set_speed(hu, QCA_INIT_SPEED);
  1358. if (qca_is_wcn399x(soc_type)) {
  1359. ret = qca_send_power_pulse(hu, true);
  1360. if (ret)
  1361. return ret;
  1362. }
  1363. /* Now the device is in ready state to communicate with host.
  1364. * To sync host with device we need to reopen port.
  1365. * Without this, we will have RTS and CTS synchronization
  1366. * issues.
  1367. */
  1368. serdev_device_close(hu->serdev);
  1369. ret = serdev_device_open(hu->serdev);
  1370. if (ret) {
  1371. bt_dev_err(hu->hdev, "failed to open port");
  1372. return ret;
  1373. }
  1374. hci_uart_set_flow_control(hu, false);
  1375. return 0;
  1376. }
  1377. static int qca_power_on(struct hci_dev *hdev)
  1378. {
  1379. struct hci_uart *hu = hci_get_drvdata(hdev);
  1380. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1381. struct qca_serdev *qcadev;
  1382. struct qca_data *qca = hu->priv;
  1383. int ret = 0;
  1384. /* Non-serdev device usually is powered by external power
  1385. * and don't need additional action in driver for power on
  1386. */
  1387. if (!hu->serdev)
  1388. return 0;
  1389. if (qca_is_wcn399x(soc_type) ||
  1390. qca_is_wcn6750(soc_type)) {
  1391. ret = qca_regulator_init(hu);
  1392. } else {
  1393. qcadev = serdev_device_get_drvdata(hu->serdev);
  1394. if (qcadev->bt_en) {
  1395. gpiod_set_value_cansleep(qcadev->bt_en, 1);
  1396. /* Controller needs time to bootup. */
  1397. msleep(150);
  1398. }
  1399. }
  1400. clear_bit(QCA_BT_OFF, &qca->flags);
  1401. return ret;
  1402. }
  1403. static int qca_setup(struct hci_uart *hu)
  1404. {
  1405. struct hci_dev *hdev = hu->hdev;
  1406. struct qca_data *qca = hu->priv;
  1407. unsigned int speed, qca_baudrate = QCA_BAUDRATE_115200;
  1408. unsigned int retries = 0;
  1409. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1410. const char *firmware_name = qca_get_firmware_name(hu);
  1411. int ret;
  1412. struct qca_btsoc_version ver;
  1413. ret = qca_check_speeds(hu);
  1414. if (ret)
  1415. return ret;
  1416. clear_bit(QCA_ROM_FW, &qca->flags);
  1417. /* Patch downloading has to be done without IBS mode */
  1418. set_bit(QCA_IBS_DISABLED, &qca->flags);
  1419. /* Enable controller to do both LE scan and BR/EDR inquiry
  1420. * simultaneously.
  1421. */
  1422. set_bit(HCI_QUIRK_SIMULTANEOUS_DISCOVERY, &hdev->quirks);
  1423. bt_dev_info(hdev, "setting up %s",
  1424. qca_is_wcn399x(soc_type) ? "wcn399x" :
  1425. (soc_type == QCA_WCN6750) ? "wcn6750" : "ROME/QCA6390");
  1426. qca->memdump_state = QCA_MEMDUMP_IDLE;
  1427. retry:
  1428. ret = qca_power_on(hdev);
  1429. if (ret)
  1430. goto out;
  1431. clear_bit(QCA_SSR_TRIGGERED, &qca->flags);
  1432. if (qca_is_wcn399x(soc_type) ||
  1433. qca_is_wcn6750(soc_type)) {
  1434. set_bit(HCI_QUIRK_USE_BDADDR_PROPERTY, &hdev->quirks);
  1435. hci_set_aosp_capable(hdev);
  1436. ret = qca_read_soc_version(hdev, &ver, soc_type);
  1437. if (ret)
  1438. goto out;
  1439. } else {
  1440. qca_set_speed(hu, QCA_INIT_SPEED);
  1441. }
  1442. /* Setup user speed if needed */
  1443. speed = qca_get_speed(hu, QCA_OPER_SPEED);
  1444. if (speed) {
  1445. ret = qca_set_speed(hu, QCA_OPER_SPEED);
  1446. if (ret)
  1447. goto out;
  1448. qca_baudrate = qca_get_baudrate_value(speed);
  1449. }
  1450. if (!(qca_is_wcn399x(soc_type) ||
  1451. qca_is_wcn6750(soc_type))) {
  1452. /* Get QCA version information */
  1453. ret = qca_read_soc_version(hdev, &ver, soc_type);
  1454. if (ret)
  1455. goto out;
  1456. }
  1457. /* Setup patch / NVM configurations */
  1458. ret = qca_uart_setup(hdev, qca_baudrate, soc_type, ver,
  1459. firmware_name);
  1460. if (!ret) {
  1461. clear_bit(QCA_IBS_DISABLED, &qca->flags);
  1462. qca_debugfs_init(hdev);
  1463. hu->hdev->hw_error = qca_hw_error;
  1464. hu->hdev->cmd_timeout = qca_cmd_timeout;
  1465. hu->hdev->wakeup = qca_wakeup;
  1466. } else if (ret == -ENOENT) {
  1467. /* No patch/nvm-config found, run with original fw/config */
  1468. set_bit(QCA_ROM_FW, &qca->flags);
  1469. ret = 0;
  1470. } else if (ret == -EAGAIN) {
  1471. /*
  1472. * Userspace firmware loader will return -EAGAIN in case no
  1473. * patch/nvm-config is found, so run with original fw/config.
  1474. */
  1475. set_bit(QCA_ROM_FW, &qca->flags);
  1476. ret = 0;
  1477. }
  1478. out:
  1479. if (ret && retries < MAX_INIT_RETRIES) {
  1480. bt_dev_warn(hdev, "Retry BT power ON:%d", retries);
  1481. qca_power_shutdown(hu);
  1482. if (hu->serdev) {
  1483. serdev_device_close(hu->serdev);
  1484. ret = serdev_device_open(hu->serdev);
  1485. if (ret) {
  1486. bt_dev_err(hdev, "failed to open port");
  1487. return ret;
  1488. }
  1489. }
  1490. retries++;
  1491. goto retry;
  1492. }
  1493. /* Setup bdaddr */
  1494. if (soc_type == QCA_ROME)
  1495. hu->hdev->set_bdaddr = qca_set_bdaddr_rome;
  1496. else
  1497. hu->hdev->set_bdaddr = qca_set_bdaddr;
  1498. return ret;
  1499. }
  1500. static const struct hci_uart_proto qca_proto = {
  1501. .id = HCI_UART_QCA,
  1502. .name = "QCA",
  1503. .manufacturer = 29,
  1504. .init_speed = 115200,
  1505. .oper_speed = 3000000,
  1506. .open = qca_open,
  1507. .close = qca_close,
  1508. .flush = qca_flush,
  1509. .setup = qca_setup,
  1510. .recv = qca_recv,
  1511. .enqueue = qca_enqueue,
  1512. .dequeue = qca_dequeue,
  1513. };
  1514. static const struct qca_device_data qca_soc_data_wcn3990 = {
  1515. .soc_type = QCA_WCN3990,
  1516. .vregs = (struct qca_vreg []) {
  1517. { "vddio", 15000 },
  1518. { "vddxo", 80000 },
  1519. { "vddrf", 300000 },
  1520. { "vddch0", 450000 },
  1521. },
  1522. .num_vregs = 4,
  1523. };
  1524. static const struct qca_device_data qca_soc_data_wcn3991 = {
  1525. .soc_type = QCA_WCN3991,
  1526. .vregs = (struct qca_vreg []) {
  1527. { "vddio", 15000 },
  1528. { "vddxo", 80000 },
  1529. { "vddrf", 300000 },
  1530. { "vddch0", 450000 },
  1531. },
  1532. .num_vregs = 4,
  1533. .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
  1534. };
  1535. static const struct qca_device_data qca_soc_data_wcn3998 = {
  1536. .soc_type = QCA_WCN3998,
  1537. .vregs = (struct qca_vreg []) {
  1538. { "vddio", 10000 },
  1539. { "vddxo", 80000 },
  1540. { "vddrf", 300000 },
  1541. { "vddch0", 450000 },
  1542. },
  1543. .num_vregs = 4,
  1544. };
  1545. static const struct qca_device_data qca_soc_data_qca6390 = {
  1546. .soc_type = QCA_QCA6390,
  1547. .num_vregs = 0,
  1548. };
  1549. static const struct qca_device_data qca_soc_data_wcn6750 = {
  1550. .soc_type = QCA_WCN6750,
  1551. .vregs = (struct qca_vreg []) {
  1552. { "vddio", 5000 },
  1553. { "vddaon", 26000 },
  1554. { "vddbtcxmx", 126000 },
  1555. { "vddrfacmn", 12500 },
  1556. { "vddrfa0p8", 102000 },
  1557. { "vddrfa1p7", 302000 },
  1558. { "vddrfa1p2", 257000 },
  1559. { "vddrfa2p2", 1700000 },
  1560. { "vddasd", 200 },
  1561. },
  1562. .num_vregs = 9,
  1563. .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
  1564. };
  1565. static void qca_power_shutdown(struct hci_uart *hu)
  1566. {
  1567. struct qca_serdev *qcadev;
  1568. struct qca_data *qca = hu->priv;
  1569. unsigned long flags;
  1570. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1571. bool sw_ctrl_state;
  1572. /* From this point we go into power off state. But serial port is
  1573. * still open, stop queueing the IBS data and flush all the buffered
  1574. * data in skb's.
  1575. */
  1576. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  1577. set_bit(QCA_IBS_DISABLED, &qca->flags);
  1578. qca_flush(hu);
  1579. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  1580. /* Non-serdev device usually is powered by external power
  1581. * and don't need additional action in driver for power down
  1582. */
  1583. if (!hu->serdev)
  1584. return;
  1585. qcadev = serdev_device_get_drvdata(hu->serdev);
  1586. if (qca_is_wcn399x(soc_type)) {
  1587. host_set_baudrate(hu, 2400);
  1588. qca_send_power_pulse(hu, false);
  1589. qca_regulator_disable(qcadev);
  1590. } else if (soc_type == QCA_WCN6750) {
  1591. gpiod_set_value_cansleep(qcadev->bt_en, 0);
  1592. msleep(100);
  1593. qca_regulator_disable(qcadev);
  1594. if (qcadev->sw_ctrl) {
  1595. sw_ctrl_state = gpiod_get_value_cansleep(qcadev->sw_ctrl);
  1596. bt_dev_dbg(hu->hdev, "SW_CTRL is %d", sw_ctrl_state);
  1597. }
  1598. } else if (qcadev->bt_en) {
  1599. gpiod_set_value_cansleep(qcadev->bt_en, 0);
  1600. }
  1601. set_bit(QCA_BT_OFF, &qca->flags);
  1602. }
  1603. static int qca_power_off(struct hci_dev *hdev)
  1604. {
  1605. struct hci_uart *hu = hci_get_drvdata(hdev);
  1606. struct qca_data *qca = hu->priv;
  1607. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1608. hu->hdev->hw_error = NULL;
  1609. hu->hdev->cmd_timeout = NULL;
  1610. del_timer_sync(&qca->wake_retrans_timer);
  1611. del_timer_sync(&qca->tx_idle_timer);
  1612. /* Stop sending shutdown command if soc crashes. */
  1613. if (soc_type != QCA_ROME
  1614. && qca->memdump_state == QCA_MEMDUMP_IDLE) {
  1615. qca_send_pre_shutdown_cmd(hdev);
  1616. usleep_range(8000, 10000);
  1617. }
  1618. qca_power_shutdown(hu);
  1619. return 0;
  1620. }
  1621. static int qca_regulator_enable(struct qca_serdev *qcadev)
  1622. {
  1623. struct qca_power *power = qcadev->bt_power;
  1624. int ret;
  1625. /* Already enabled */
  1626. if (power->vregs_on)
  1627. return 0;
  1628. BT_DBG("enabling %d regulators)", power->num_vregs);
  1629. ret = regulator_bulk_enable(power->num_vregs, power->vreg_bulk);
  1630. if (ret)
  1631. return ret;
  1632. power->vregs_on = true;
  1633. ret = clk_prepare_enable(qcadev->susclk);
  1634. if (ret)
  1635. qca_regulator_disable(qcadev);
  1636. return ret;
  1637. }
  1638. static void qca_regulator_disable(struct qca_serdev *qcadev)
  1639. {
  1640. struct qca_power *power;
  1641. if (!qcadev)
  1642. return;
  1643. power = qcadev->bt_power;
  1644. /* Already disabled? */
  1645. if (!power->vregs_on)
  1646. return;
  1647. regulator_bulk_disable(power->num_vregs, power->vreg_bulk);
  1648. power->vregs_on = false;
  1649. clk_disable_unprepare(qcadev->susclk);
  1650. }
  1651. static int qca_init_regulators(struct qca_power *qca,
  1652. const struct qca_vreg *vregs, size_t num_vregs)
  1653. {
  1654. struct regulator_bulk_data *bulk;
  1655. int ret;
  1656. int i;
  1657. bulk = devm_kcalloc(qca->dev, num_vregs, sizeof(*bulk), GFP_KERNEL);
  1658. if (!bulk)
  1659. return -ENOMEM;
  1660. for (i = 0; i < num_vregs; i++)
  1661. bulk[i].supply = vregs[i].name;
  1662. ret = devm_regulator_bulk_get(qca->dev, num_vregs, bulk);
  1663. if (ret < 0)
  1664. return ret;
  1665. for (i = 0; i < num_vregs; i++) {
  1666. ret = regulator_set_load(bulk[i].consumer, vregs[i].load_uA);
  1667. if (ret)
  1668. return ret;
  1669. }
  1670. qca->vreg_bulk = bulk;
  1671. qca->num_vregs = num_vregs;
  1672. return 0;
  1673. }
  1674. static int qca_serdev_probe(struct serdev_device *serdev)
  1675. {
  1676. struct qca_serdev *qcadev;
  1677. struct hci_dev *hdev;
  1678. const struct qca_device_data *data;
  1679. int err;
  1680. bool power_ctrl_enabled = true;
  1681. qcadev = devm_kzalloc(&serdev->dev, sizeof(*qcadev), GFP_KERNEL);
  1682. if (!qcadev)
  1683. return -ENOMEM;
  1684. qcadev->serdev_hu.serdev = serdev;
  1685. data = device_get_match_data(&serdev->dev);
  1686. serdev_device_set_drvdata(serdev, qcadev);
  1687. device_property_read_string(&serdev->dev, "firmware-name",
  1688. &qcadev->firmware_name);
  1689. device_property_read_u32(&serdev->dev, "max-speed",
  1690. &qcadev->oper_speed);
  1691. if (!qcadev->oper_speed)
  1692. BT_DBG("UART will pick default operating speed");
  1693. if (data &&
  1694. (qca_is_wcn399x(data->soc_type) ||
  1695. qca_is_wcn6750(data->soc_type))) {
  1696. qcadev->btsoc_type = data->soc_type;
  1697. qcadev->bt_power = devm_kzalloc(&serdev->dev,
  1698. sizeof(struct qca_power),
  1699. GFP_KERNEL);
  1700. if (!qcadev->bt_power)
  1701. return -ENOMEM;
  1702. qcadev->bt_power->dev = &serdev->dev;
  1703. err = qca_init_regulators(qcadev->bt_power, data->vregs,
  1704. data->num_vregs);
  1705. if (err) {
  1706. BT_ERR("Failed to init regulators:%d", err);
  1707. return err;
  1708. }
  1709. qcadev->bt_power->vregs_on = false;
  1710. qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
  1711. GPIOD_OUT_LOW);
  1712. if (IS_ERR_OR_NULL(qcadev->bt_en) && data->soc_type == QCA_WCN6750) {
  1713. dev_err(&serdev->dev, "failed to acquire BT_EN gpio\n");
  1714. power_ctrl_enabled = false;
  1715. }
  1716. qcadev->sw_ctrl = devm_gpiod_get_optional(&serdev->dev, "swctrl",
  1717. GPIOD_IN);
  1718. if (IS_ERR_OR_NULL(qcadev->sw_ctrl) && data->soc_type == QCA_WCN6750)
  1719. dev_warn(&serdev->dev, "failed to acquire SW_CTRL gpio\n");
  1720. qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL);
  1721. if (IS_ERR(qcadev->susclk)) {
  1722. dev_err(&serdev->dev, "failed to acquire clk\n");
  1723. return PTR_ERR(qcadev->susclk);
  1724. }
  1725. err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto);
  1726. if (err) {
  1727. BT_ERR("wcn3990 serdev registration failed");
  1728. return err;
  1729. }
  1730. } else {
  1731. if (data)
  1732. qcadev->btsoc_type = data->soc_type;
  1733. else
  1734. qcadev->btsoc_type = QCA_ROME;
  1735. qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
  1736. GPIOD_OUT_LOW);
  1737. if (IS_ERR_OR_NULL(qcadev->bt_en)) {
  1738. dev_warn(&serdev->dev, "failed to acquire enable gpio\n");
  1739. power_ctrl_enabled = false;
  1740. }
  1741. qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL);
  1742. if (IS_ERR(qcadev->susclk)) {
  1743. dev_warn(&serdev->dev, "failed to acquire clk\n");
  1744. return PTR_ERR(qcadev->susclk);
  1745. }
  1746. err = clk_set_rate(qcadev->susclk, SUSCLK_RATE_32KHZ);
  1747. if (err)
  1748. return err;
  1749. err = clk_prepare_enable(qcadev->susclk);
  1750. if (err)
  1751. return err;
  1752. err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto);
  1753. if (err) {
  1754. BT_ERR("Rome serdev registration failed");
  1755. clk_disable_unprepare(qcadev->susclk);
  1756. return err;
  1757. }
  1758. }
  1759. hdev = qcadev->serdev_hu.hdev;
  1760. if (power_ctrl_enabled) {
  1761. set_bit(HCI_QUIRK_NON_PERSISTENT_SETUP, &hdev->quirks);
  1762. hdev->shutdown = qca_power_off;
  1763. }
  1764. if (data) {
  1765. /* Wideband speech support must be set per driver since it can't
  1766. * be queried via hci. Same with the valid le states quirk.
  1767. */
  1768. if (data->capabilities & QCA_CAP_WIDEBAND_SPEECH)
  1769. set_bit(HCI_QUIRK_WIDEBAND_SPEECH_SUPPORTED,
  1770. &hdev->quirks);
  1771. if (data->capabilities & QCA_CAP_VALID_LE_STATES)
  1772. set_bit(HCI_QUIRK_VALID_LE_STATES, &hdev->quirks);
  1773. }
  1774. return 0;
  1775. }
  1776. static void qca_serdev_remove(struct serdev_device *serdev)
  1777. {
  1778. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  1779. struct qca_power *power = qcadev->bt_power;
  1780. if ((qca_is_wcn399x(qcadev->btsoc_type) ||
  1781. qca_is_wcn6750(qcadev->btsoc_type)) &&
  1782. power->vregs_on)
  1783. qca_power_shutdown(&qcadev->serdev_hu);
  1784. else if (qcadev->susclk)
  1785. clk_disable_unprepare(qcadev->susclk);
  1786. hci_uart_unregister_device(&qcadev->serdev_hu);
  1787. }
  1788. static void qca_serdev_shutdown(struct device *dev)
  1789. {
  1790. int ret;
  1791. int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS);
  1792. struct serdev_device *serdev = to_serdev_device(dev);
  1793. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  1794. struct hci_uart *hu = &qcadev->serdev_hu;
  1795. struct hci_dev *hdev = hu->hdev;
  1796. struct qca_data *qca = hu->priv;
  1797. const u8 ibs_wake_cmd[] = { 0xFD };
  1798. const u8 edl_reset_soc_cmd[] = { 0x01, 0x00, 0xFC, 0x01, 0x05 };
  1799. if (qcadev->btsoc_type == QCA_QCA6390) {
  1800. if (test_bit(QCA_BT_OFF, &qca->flags) ||
  1801. !test_bit(HCI_RUNNING, &hdev->flags))
  1802. return;
  1803. serdev_device_write_flush(serdev);
  1804. ret = serdev_device_write_buf(serdev, ibs_wake_cmd,
  1805. sizeof(ibs_wake_cmd));
  1806. if (ret < 0) {
  1807. BT_ERR("QCA send IBS_WAKE_IND error: %d", ret);
  1808. return;
  1809. }
  1810. serdev_device_wait_until_sent(serdev, timeout);
  1811. usleep_range(8000, 10000);
  1812. serdev_device_write_flush(serdev);
  1813. ret = serdev_device_write_buf(serdev, edl_reset_soc_cmd,
  1814. sizeof(edl_reset_soc_cmd));
  1815. if (ret < 0) {
  1816. BT_ERR("QCA send EDL_RESET_REQ error: %d", ret);
  1817. return;
  1818. }
  1819. serdev_device_wait_until_sent(serdev, timeout);
  1820. usleep_range(8000, 10000);
  1821. }
  1822. }
  1823. static int __maybe_unused qca_suspend(struct device *dev)
  1824. {
  1825. struct serdev_device *serdev = to_serdev_device(dev);
  1826. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  1827. struct hci_uart *hu = &qcadev->serdev_hu;
  1828. struct qca_data *qca = hu->priv;
  1829. unsigned long flags;
  1830. bool tx_pending = false;
  1831. int ret = 0;
  1832. u8 cmd;
  1833. u32 wait_timeout = 0;
  1834. set_bit(QCA_SUSPENDING, &qca->flags);
  1835. /* if BT SoC is running with default firmware then it does not
  1836. * support in-band sleep
  1837. */
  1838. if (test_bit(QCA_ROM_FW, &qca->flags))
  1839. return 0;
  1840. /* During SSR after memory dump collection, controller will be
  1841. * powered off and then powered on.If controller is powered off
  1842. * during SSR then we should wait until SSR is completed.
  1843. */
  1844. if (test_bit(QCA_BT_OFF, &qca->flags) &&
  1845. !test_bit(QCA_SSR_TRIGGERED, &qca->flags))
  1846. return 0;
  1847. if (test_bit(QCA_IBS_DISABLED, &qca->flags) ||
  1848. test_bit(QCA_SSR_TRIGGERED, &qca->flags)) {
  1849. wait_timeout = test_bit(QCA_SSR_TRIGGERED, &qca->flags) ?
  1850. IBS_DISABLE_SSR_TIMEOUT_MS :
  1851. FW_DOWNLOAD_TIMEOUT_MS;
  1852. /* QCA_IBS_DISABLED flag is set to true, During FW download
  1853. * and during memory dump collection. It is reset to false,
  1854. * After FW download complete.
  1855. */
  1856. wait_on_bit_timeout(&qca->flags, QCA_IBS_DISABLED,
  1857. TASK_UNINTERRUPTIBLE, msecs_to_jiffies(wait_timeout));
  1858. if (test_bit(QCA_IBS_DISABLED, &qca->flags)) {
  1859. bt_dev_err(hu->hdev, "SSR or FW download time out");
  1860. ret = -ETIMEDOUT;
  1861. goto error;
  1862. }
  1863. }
  1864. cancel_work_sync(&qca->ws_awake_device);
  1865. cancel_work_sync(&qca->ws_awake_rx);
  1866. spin_lock_irqsave_nested(&qca->hci_ibs_lock,
  1867. flags, SINGLE_DEPTH_NESTING);
  1868. switch (qca->tx_ibs_state) {
  1869. case HCI_IBS_TX_WAKING:
  1870. del_timer(&qca->wake_retrans_timer);
  1871. fallthrough;
  1872. case HCI_IBS_TX_AWAKE:
  1873. del_timer(&qca->tx_idle_timer);
  1874. serdev_device_write_flush(hu->serdev);
  1875. cmd = HCI_IBS_SLEEP_IND;
  1876. ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd));
  1877. if (ret < 0) {
  1878. BT_ERR("Failed to send SLEEP to device");
  1879. break;
  1880. }
  1881. qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
  1882. qca->ibs_sent_slps++;
  1883. tx_pending = true;
  1884. break;
  1885. case HCI_IBS_TX_ASLEEP:
  1886. break;
  1887. default:
  1888. BT_ERR("Spurious tx state %d", qca->tx_ibs_state);
  1889. ret = -EINVAL;
  1890. break;
  1891. }
  1892. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  1893. if (ret < 0)
  1894. goto error;
  1895. if (tx_pending) {
  1896. serdev_device_wait_until_sent(hu->serdev,
  1897. msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS));
  1898. serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
  1899. }
  1900. /* Wait for HCI_IBS_SLEEP_IND sent by device to indicate its Tx is going
  1901. * to sleep, so that the packet does not wake the system later.
  1902. */
  1903. ret = wait_event_interruptible_timeout(qca->suspend_wait_q,
  1904. qca->rx_ibs_state == HCI_IBS_RX_ASLEEP,
  1905. msecs_to_jiffies(IBS_BTSOC_TX_IDLE_TIMEOUT_MS));
  1906. if (ret == 0) {
  1907. ret = -ETIMEDOUT;
  1908. goto error;
  1909. }
  1910. return 0;
  1911. error:
  1912. clear_bit(QCA_SUSPENDING, &qca->flags);
  1913. return ret;
  1914. }
  1915. static int __maybe_unused qca_resume(struct device *dev)
  1916. {
  1917. struct serdev_device *serdev = to_serdev_device(dev);
  1918. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  1919. struct hci_uart *hu = &qcadev->serdev_hu;
  1920. struct qca_data *qca = hu->priv;
  1921. clear_bit(QCA_SUSPENDING, &qca->flags);
  1922. return 0;
  1923. }
  1924. static SIMPLE_DEV_PM_OPS(qca_pm_ops, qca_suspend, qca_resume);
  1925. #ifdef CONFIG_OF
  1926. static const struct of_device_id qca_bluetooth_of_match[] = {
  1927. { .compatible = "qcom,qca6174-bt" },
  1928. { .compatible = "qcom,qca6390-bt", .data = &qca_soc_data_qca6390},
  1929. { .compatible = "qcom,qca9377-bt" },
  1930. { .compatible = "qcom,wcn3990-bt", .data = &qca_soc_data_wcn3990},
  1931. { .compatible = "qcom,wcn3991-bt", .data = &qca_soc_data_wcn3991},
  1932. { .compatible = "qcom,wcn3998-bt", .data = &qca_soc_data_wcn3998},
  1933. { .compatible = "qcom,wcn6750-bt", .data = &qca_soc_data_wcn6750},
  1934. { /* sentinel */ }
  1935. };
  1936. MODULE_DEVICE_TABLE(of, qca_bluetooth_of_match);
  1937. #endif
  1938. #ifdef CONFIG_ACPI
  1939. static const struct acpi_device_id qca_bluetooth_acpi_match[] = {
  1940. { "QCOM6390", (kernel_ulong_t)&qca_soc_data_qca6390 },
  1941. { "DLA16390", (kernel_ulong_t)&qca_soc_data_qca6390 },
  1942. { "DLB16390", (kernel_ulong_t)&qca_soc_data_qca6390 },
  1943. { "DLB26390", (kernel_ulong_t)&qca_soc_data_qca6390 },
  1944. { },
  1945. };
  1946. MODULE_DEVICE_TABLE(acpi, qca_bluetooth_acpi_match);
  1947. #endif
  1948. static struct serdev_device_driver qca_serdev_driver = {
  1949. .probe = qca_serdev_probe,
  1950. .remove = qca_serdev_remove,
  1951. .driver = {
  1952. .name = "hci_uart_qca",
  1953. .of_match_table = of_match_ptr(qca_bluetooth_of_match),
  1954. .acpi_match_table = ACPI_PTR(qca_bluetooth_acpi_match),
  1955. .shutdown = qca_serdev_shutdown,
  1956. .pm = &qca_pm_ops,
  1957. },
  1958. };
  1959. int __init qca_init(void)
  1960. {
  1961. serdev_device_driver_register(&qca_serdev_driver);
  1962. return hci_uart_register_proto(&qca_proto);
  1963. }
  1964. int __exit qca_deinit(void)
  1965. {
  1966. serdev_device_driver_unregister(&qca_serdev_driver);
  1967. return hci_uart_unregister_proto(&qca_proto);
  1968. }