btmtk.h 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154
  1. /* SPDX-License-Identifier: ISC */
  2. /* Copyright (C) 2021 MediaTek Inc. */
  3. #define FIRMWARE_MT7622 "mediatek/mt7622pr2h.bin"
  4. #define FIRMWARE_MT7663 "mediatek/mt7663pr2h.bin"
  5. #define FIRMWARE_MT7668 "mediatek/mt7668pr2h.bin"
  6. #define FIRMWARE_MT7961 "mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin"
  7. #define HCI_EV_WMT 0xe4
  8. #define HCI_WMT_MAX_EVENT_SIZE 64
  9. #define BTMTK_WMT_REG_WRITE 0x1
  10. #define BTMTK_WMT_REG_READ 0x2
  11. #define MT7921_BTSYS_RST 0x70002610
  12. #define MT7921_BTSYS_RST_WITH_GPIO BIT(7)
  13. #define MT7921_PINMUX_0 0x70005050
  14. #define MT7921_PINMUX_1 0x70005054
  15. #define MT7921_DLSTATUS 0x7c053c10
  16. #define BT_DL_STATE BIT(1)
  17. enum {
  18. BTMTK_WMT_PATCH_DWNLD = 0x1,
  19. BTMTK_WMT_TEST = 0x2,
  20. BTMTK_WMT_WAKEUP = 0x3,
  21. BTMTK_WMT_HIF = 0x4,
  22. BTMTK_WMT_FUNC_CTRL = 0x6,
  23. BTMTK_WMT_RST = 0x7,
  24. BTMTK_WMT_REGISTER = 0x8,
  25. BTMTK_WMT_SEMAPHORE = 0x17,
  26. };
  27. enum {
  28. BTMTK_WMT_INVALID,
  29. BTMTK_WMT_PATCH_UNDONE,
  30. BTMTK_WMT_PATCH_PROGRESS,
  31. BTMTK_WMT_PATCH_DONE,
  32. BTMTK_WMT_ON_UNDONE,
  33. BTMTK_WMT_ON_DONE,
  34. BTMTK_WMT_ON_PROGRESS,
  35. };
  36. struct btmtk_wmt_hdr {
  37. u8 dir;
  38. u8 op;
  39. __le16 dlen;
  40. u8 flag;
  41. } __packed;
  42. struct btmtk_hci_wmt_cmd {
  43. struct btmtk_wmt_hdr hdr;
  44. u8 data[];
  45. } __packed;
  46. struct btmtk_hci_wmt_evt {
  47. struct hci_event_hdr hhdr;
  48. struct btmtk_wmt_hdr whdr;
  49. } __packed;
  50. struct btmtk_hci_wmt_evt_funcc {
  51. struct btmtk_hci_wmt_evt hwhdr;
  52. __be16 status;
  53. } __packed;
  54. struct btmtk_hci_wmt_evt_reg {
  55. struct btmtk_hci_wmt_evt hwhdr;
  56. u8 rsv[2];
  57. u8 num;
  58. __le32 addr;
  59. __le32 val;
  60. } __packed;
  61. struct btmtk_tci_sleep {
  62. u8 mode;
  63. __le16 duration;
  64. __le16 host_duration;
  65. u8 host_wakeup_pin;
  66. u8 time_compensation;
  67. } __packed;
  68. struct btmtk_wakeon {
  69. u8 mode;
  70. u8 gpo;
  71. u8 active_high;
  72. __le16 enable_delay;
  73. __le16 wakeup_delay;
  74. } __packed;
  75. struct btmtk_sco {
  76. u8 clock_config;
  77. u8 transmit_format_config;
  78. u8 channel_format_config;
  79. u8 channel_select_config;
  80. } __packed;
  81. struct reg_read_cmd {
  82. u8 type;
  83. u8 rsv;
  84. u8 num;
  85. __le32 addr;
  86. } __packed;
  87. struct reg_write_cmd {
  88. u8 type;
  89. u8 rsv;
  90. u8 num;
  91. __le32 addr;
  92. __le32 data;
  93. __le32 mask;
  94. } __packed;
  95. struct btmtk_hci_wmt_params {
  96. u8 op;
  97. u8 flag;
  98. u16 dlen;
  99. const void *data;
  100. u32 *status;
  101. };
  102. typedef int (*wmt_cmd_sync_func_t)(struct hci_dev *,
  103. struct btmtk_hci_wmt_params *);
  104. #if IS_ENABLED(CONFIG_BT_MTK)
  105. int btmtk_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr);
  106. int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname,
  107. wmt_cmd_sync_func_t wmt_cmd_sync);
  108. int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname,
  109. wmt_cmd_sync_func_t wmt_cmd_sync);
  110. #else
  111. static inline int btmtk_set_bdaddr(struct hci_dev *hdev,
  112. const bdaddr_t *bdaddr)
  113. {
  114. return -EOPNOTSUPP;
  115. }
  116. static int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname,
  117. wmt_cmd_sync_func_t wmt_cmd_sync)
  118. {
  119. return -EOPNOTSUPP;
  120. }
  121. static int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname,
  122. wmt_cmd_sync_func_t wmt_cmd_sync)
  123. {
  124. return -EOPNOTSUPP;
  125. }
  126. #endif