ps3vram.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ps3vram - Use extra PS3 video ram as block device.
  4. *
  5. * Copyright 2009 Sony Corporation
  6. *
  7. * Based on the MTD ps3vram driver, which is
  8. * Copyright (c) 2007-2008 Jim Paris <[email protected]>
  9. * Added support RSX DMA Vivien Chappelier <[email protected]>
  10. */
  11. #include <linux/blkdev.h>
  12. #include <linux/delay.h>
  13. #include <linux/module.h>
  14. #include <linux/proc_fs.h>
  15. #include <linux/seq_file.h>
  16. #include <linux/slab.h>
  17. #include <asm/cell-regs.h>
  18. #include <asm/firmware.h>
  19. #include <asm/lv1call.h>
  20. #include <asm/ps3.h>
  21. #include <asm/ps3gpu.h>
  22. #define DEVICE_NAME "ps3vram"
  23. #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
  24. #define XDR_IOIF 0x0c000000
  25. #define FIFO_BASE XDR_IOIF
  26. #define FIFO_SIZE (64 * 1024)
  27. #define DMA_PAGE_SIZE (4 * 1024)
  28. #define CACHE_PAGE_SIZE (256 * 1024)
  29. #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
  30. #define CACHE_OFFSET CACHE_PAGE_SIZE
  31. #define FIFO_OFFSET 0
  32. #define CTRL_PUT 0x10
  33. #define CTRL_GET 0x11
  34. #define CTRL_TOP 0x15
  35. #define UPLOAD_SUBCH 1
  36. #define DOWNLOAD_SUBCH 2
  37. #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
  38. #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
  39. #define CACHE_PAGE_PRESENT 1
  40. #define CACHE_PAGE_DIRTY 2
  41. struct ps3vram_tag {
  42. unsigned int address;
  43. unsigned int flags;
  44. };
  45. struct ps3vram_cache {
  46. unsigned int page_count;
  47. unsigned int page_size;
  48. struct ps3vram_tag *tags;
  49. unsigned int hit;
  50. unsigned int miss;
  51. };
  52. struct ps3vram_priv {
  53. struct gendisk *gendisk;
  54. u64 size;
  55. u64 memory_handle;
  56. u64 context_handle;
  57. u32 __iomem *ctrl;
  58. void __iomem *reports;
  59. u8 *xdr_buf;
  60. u32 *fifo_base;
  61. u32 *fifo_ptr;
  62. struct ps3vram_cache cache;
  63. spinlock_t lock; /* protecting list of bios */
  64. struct bio_list list;
  65. };
  66. static int ps3vram_major;
  67. #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
  68. #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
  69. #define DMA_NOTIFIER_SIZE 0x40
  70. #define NOTIFIER 7 /* notifier used for completion report */
  71. static char *size = "256M";
  72. module_param(size, charp, 0);
  73. MODULE_PARM_DESC(size, "memory size");
  74. static u32 __iomem *ps3vram_get_notifier(void __iomem *reports, int notifier)
  75. {
  76. return reports + DMA_NOTIFIER_OFFSET_BASE +
  77. DMA_NOTIFIER_SIZE * notifier;
  78. }
  79. static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev)
  80. {
  81. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  82. u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  83. int i;
  84. for (i = 0; i < 4; i++)
  85. iowrite32be(0xffffffff, notify + i);
  86. }
  87. static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev,
  88. unsigned int timeout_ms)
  89. {
  90. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  91. u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  92. unsigned long timeout;
  93. for (timeout = 20; timeout; timeout--) {
  94. if (!ioread32be(notify + 3))
  95. return 0;
  96. udelay(10);
  97. }
  98. timeout = jiffies + msecs_to_jiffies(timeout_ms);
  99. do {
  100. if (!ioread32be(notify + 3))
  101. return 0;
  102. msleep(1);
  103. } while (time_before(jiffies, timeout));
  104. return -ETIMEDOUT;
  105. }
  106. static void ps3vram_init_ring(struct ps3_system_bus_device *dev)
  107. {
  108. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  109. iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT);
  110. iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_GET);
  111. }
  112. static int ps3vram_wait_ring(struct ps3_system_bus_device *dev,
  113. unsigned int timeout_ms)
  114. {
  115. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  116. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  117. do {
  118. if (ioread32be(priv->ctrl + CTRL_PUT) == ioread32be(priv->ctrl + CTRL_GET))
  119. return 0;
  120. msleep(1);
  121. } while (time_before(jiffies, timeout));
  122. dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n",
  123. ioread32be(priv->ctrl + CTRL_PUT), ioread32be(priv->ctrl + CTRL_GET),
  124. ioread32be(priv->ctrl + CTRL_TOP));
  125. return -ETIMEDOUT;
  126. }
  127. static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data)
  128. {
  129. *(priv->fifo_ptr)++ = data;
  130. }
  131. static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag,
  132. u32 size)
  133. {
  134. ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
  135. }
  136. static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev)
  137. {
  138. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  139. int status;
  140. ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
  141. iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT);
  142. /* asking the HV for a blit will kick the FIFO */
  143. status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
  144. if (status)
  145. dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
  146. __func__, status);
  147. priv->fifo_ptr = priv->fifo_base;
  148. }
  149. static void ps3vram_fire_ring(struct ps3_system_bus_device *dev)
  150. {
  151. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  152. int status;
  153. mutex_lock(&ps3_gpu_mutex);
  154. iowrite32be(FIFO_BASE + FIFO_OFFSET + (priv->fifo_ptr - priv->fifo_base)
  155. * sizeof(u32), priv->ctrl + CTRL_PUT);
  156. /* asking the HV for a blit will kick the FIFO */
  157. status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
  158. if (status)
  159. dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
  160. __func__, status);
  161. if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) >
  162. FIFO_SIZE - 1024) {
  163. dev_dbg(&dev->core, "FIFO full, rewinding\n");
  164. ps3vram_wait_ring(dev, 200);
  165. ps3vram_rewind_ring(dev);
  166. }
  167. mutex_unlock(&ps3_gpu_mutex);
  168. }
  169. static void ps3vram_bind(struct ps3_system_bus_device *dev)
  170. {
  171. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  172. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
  173. ps3vram_out_ring(priv, 0x31337303);
  174. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
  175. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  176. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  177. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  178. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
  179. ps3vram_out_ring(priv, 0x3137c0de);
  180. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
  181. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  182. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  183. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  184. ps3vram_fire_ring(dev);
  185. }
  186. static int ps3vram_upload(struct ps3_system_bus_device *dev,
  187. unsigned int src_offset, unsigned int dst_offset,
  188. int len, int count)
  189. {
  190. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  191. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  192. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  193. ps3vram_out_ring(priv, XDR_IOIF + src_offset);
  194. ps3vram_out_ring(priv, dst_offset);
  195. ps3vram_out_ring(priv, len);
  196. ps3vram_out_ring(priv, len);
  197. ps3vram_out_ring(priv, len);
  198. ps3vram_out_ring(priv, count);
  199. ps3vram_out_ring(priv, (1 << 8) | 1);
  200. ps3vram_out_ring(priv, 0);
  201. ps3vram_notifier_reset(dev);
  202. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  203. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  204. ps3vram_out_ring(priv, 0);
  205. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
  206. ps3vram_out_ring(priv, 0);
  207. ps3vram_fire_ring(dev);
  208. if (ps3vram_notifier_wait(dev, 200) < 0) {
  209. dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
  210. return -1;
  211. }
  212. return 0;
  213. }
  214. static int ps3vram_download(struct ps3_system_bus_device *dev,
  215. unsigned int src_offset, unsigned int dst_offset,
  216. int len, int count)
  217. {
  218. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  219. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  220. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  221. ps3vram_out_ring(priv, src_offset);
  222. ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
  223. ps3vram_out_ring(priv, len);
  224. ps3vram_out_ring(priv, len);
  225. ps3vram_out_ring(priv, len);
  226. ps3vram_out_ring(priv, count);
  227. ps3vram_out_ring(priv, (1 << 8) | 1);
  228. ps3vram_out_ring(priv, 0);
  229. ps3vram_notifier_reset(dev);
  230. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  231. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  232. ps3vram_out_ring(priv, 0);
  233. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
  234. ps3vram_out_ring(priv, 0);
  235. ps3vram_fire_ring(dev);
  236. if (ps3vram_notifier_wait(dev, 200) < 0) {
  237. dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
  238. return -1;
  239. }
  240. return 0;
  241. }
  242. static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry)
  243. {
  244. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  245. struct ps3vram_cache *cache = &priv->cache;
  246. if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY))
  247. return;
  248. dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry,
  249. cache->tags[entry].address);
  250. if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size,
  251. cache->tags[entry].address, DMA_PAGE_SIZE,
  252. cache->page_size / DMA_PAGE_SIZE) < 0) {
  253. dev_err(&dev->core,
  254. "Failed to upload from 0x%x to " "0x%x size 0x%x\n",
  255. entry * cache->page_size, cache->tags[entry].address,
  256. cache->page_size);
  257. }
  258. cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
  259. }
  260. static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry,
  261. unsigned int address)
  262. {
  263. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  264. struct ps3vram_cache *cache = &priv->cache;
  265. dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address);
  266. if (ps3vram_download(dev, address,
  267. CACHE_OFFSET + entry * cache->page_size,
  268. DMA_PAGE_SIZE,
  269. cache->page_size / DMA_PAGE_SIZE) < 0) {
  270. dev_err(&dev->core,
  271. "Failed to download from 0x%x to 0x%x size 0x%x\n",
  272. address, entry * cache->page_size, cache->page_size);
  273. }
  274. cache->tags[entry].address = address;
  275. cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
  276. }
  277. static void ps3vram_cache_flush(struct ps3_system_bus_device *dev)
  278. {
  279. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  280. struct ps3vram_cache *cache = &priv->cache;
  281. int i;
  282. dev_dbg(&dev->core, "FLUSH\n");
  283. for (i = 0; i < cache->page_count; i++) {
  284. ps3vram_cache_evict(dev, i);
  285. cache->tags[i].flags = 0;
  286. }
  287. }
  288. static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev,
  289. loff_t address)
  290. {
  291. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  292. struct ps3vram_cache *cache = &priv->cache;
  293. unsigned int base;
  294. unsigned int offset;
  295. int i;
  296. static int counter;
  297. offset = (unsigned int) (address & (cache->page_size - 1));
  298. base = (unsigned int) (address - offset);
  299. /* fully associative check */
  300. for (i = 0; i < cache->page_count; i++) {
  301. if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
  302. cache->tags[i].address == base) {
  303. cache->hit++;
  304. dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i,
  305. cache->tags[i].address);
  306. return i;
  307. }
  308. }
  309. /* choose a random entry */
  310. i = (jiffies + (counter++)) % cache->page_count;
  311. dev_dbg(&dev->core, "Using entry %d\n", i);
  312. ps3vram_cache_evict(dev, i);
  313. ps3vram_cache_load(dev, i, base);
  314. cache->miss++;
  315. return i;
  316. }
  317. static int ps3vram_cache_init(struct ps3_system_bus_device *dev)
  318. {
  319. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  320. priv->cache.page_count = CACHE_PAGE_COUNT;
  321. priv->cache.page_size = CACHE_PAGE_SIZE;
  322. priv->cache.tags = kcalloc(CACHE_PAGE_COUNT,
  323. sizeof(struct ps3vram_tag),
  324. GFP_KERNEL);
  325. if (!priv->cache.tags)
  326. return -ENOMEM;
  327. dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n",
  328. CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
  329. return 0;
  330. }
  331. static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev)
  332. {
  333. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  334. ps3vram_cache_flush(dev);
  335. kfree(priv->cache.tags);
  336. }
  337. static blk_status_t ps3vram_read(struct ps3_system_bus_device *dev, loff_t from,
  338. size_t len, size_t *retlen, u_char *buf)
  339. {
  340. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  341. unsigned int cached, count;
  342. dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__,
  343. (unsigned int)from, len);
  344. if (from >= priv->size)
  345. return BLK_STS_IOERR;
  346. if (len > priv->size - from)
  347. len = priv->size - from;
  348. /* Copy from vram to buf */
  349. count = len;
  350. while (count) {
  351. unsigned int offset, avail;
  352. unsigned int entry;
  353. offset = (unsigned int) (from & (priv->cache.page_size - 1));
  354. avail = priv->cache.page_size - offset;
  355. entry = ps3vram_cache_match(dev, from);
  356. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  357. dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x "
  358. "avail=%08x count=%08x\n", __func__,
  359. (unsigned int)from, cached, offset, avail, count);
  360. if (avail > count)
  361. avail = count;
  362. memcpy(buf, priv->xdr_buf + cached, avail);
  363. buf += avail;
  364. count -= avail;
  365. from += avail;
  366. }
  367. *retlen = len;
  368. return 0;
  369. }
  370. static blk_status_t ps3vram_write(struct ps3_system_bus_device *dev, loff_t to,
  371. size_t len, size_t *retlen, const u_char *buf)
  372. {
  373. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  374. unsigned int cached, count;
  375. if (to >= priv->size)
  376. return BLK_STS_IOERR;
  377. if (len > priv->size - to)
  378. len = priv->size - to;
  379. /* Copy from buf to vram */
  380. count = len;
  381. while (count) {
  382. unsigned int offset, avail;
  383. unsigned int entry;
  384. offset = (unsigned int) (to & (priv->cache.page_size - 1));
  385. avail = priv->cache.page_size - offset;
  386. entry = ps3vram_cache_match(dev, to);
  387. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  388. dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x "
  389. "avail=%08x count=%08x\n", __func__, (unsigned int)to,
  390. cached, offset, avail, count);
  391. if (avail > count)
  392. avail = count;
  393. memcpy(priv->xdr_buf + cached, buf, avail);
  394. priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
  395. buf += avail;
  396. count -= avail;
  397. to += avail;
  398. }
  399. *retlen = len;
  400. return 0;
  401. }
  402. static int ps3vram_proc_show(struct seq_file *m, void *v)
  403. {
  404. struct ps3vram_priv *priv = m->private;
  405. seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss);
  406. return 0;
  407. }
  408. static void ps3vram_proc_init(struct ps3_system_bus_device *dev)
  409. {
  410. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  411. struct proc_dir_entry *pde;
  412. pde = proc_create_single_data(DEVICE_NAME, 0444, NULL,
  413. ps3vram_proc_show, priv);
  414. if (!pde)
  415. dev_warn(&dev->core, "failed to create /proc entry\n");
  416. }
  417. static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev,
  418. struct bio *bio)
  419. {
  420. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  421. int write = bio_data_dir(bio) == WRITE;
  422. const char *op = write ? "write" : "read";
  423. loff_t offset = bio->bi_iter.bi_sector << 9;
  424. blk_status_t error = 0;
  425. struct bio_vec bvec;
  426. struct bvec_iter iter;
  427. struct bio *next;
  428. bio_for_each_segment(bvec, bio, iter) {
  429. /* PS3 is ppc64, so we don't handle highmem */
  430. char *ptr = bvec_virt(&bvec);
  431. size_t len = bvec.bv_len, retlen;
  432. dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op,
  433. len, offset);
  434. if (write)
  435. error = ps3vram_write(dev, offset, len, &retlen, ptr);
  436. else
  437. error = ps3vram_read(dev, offset, len, &retlen, ptr);
  438. if (error) {
  439. dev_err(&dev->core, "%s failed\n", op);
  440. goto out;
  441. }
  442. if (retlen != len) {
  443. dev_err(&dev->core, "Short %s\n", op);
  444. error = BLK_STS_IOERR;
  445. goto out;
  446. }
  447. offset += len;
  448. }
  449. dev_dbg(&dev->core, "%s completed\n", op);
  450. out:
  451. spin_lock_irq(&priv->lock);
  452. bio_list_pop(&priv->list);
  453. next = bio_list_peek(&priv->list);
  454. spin_unlock_irq(&priv->lock);
  455. bio->bi_status = error;
  456. bio_endio(bio);
  457. return next;
  458. }
  459. static void ps3vram_submit_bio(struct bio *bio)
  460. {
  461. struct ps3_system_bus_device *dev = bio->bi_bdev->bd_disk->private_data;
  462. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  463. int busy;
  464. dev_dbg(&dev->core, "%s\n", __func__);
  465. bio = bio_split_to_limits(bio);
  466. if (!bio)
  467. return;
  468. spin_lock_irq(&priv->lock);
  469. busy = !bio_list_empty(&priv->list);
  470. bio_list_add(&priv->list, bio);
  471. spin_unlock_irq(&priv->lock);
  472. if (busy)
  473. return;
  474. do {
  475. bio = ps3vram_do_bio(dev, bio);
  476. } while (bio);
  477. }
  478. static const struct block_device_operations ps3vram_fops = {
  479. .owner = THIS_MODULE,
  480. .submit_bio = ps3vram_submit_bio,
  481. };
  482. static int ps3vram_probe(struct ps3_system_bus_device *dev)
  483. {
  484. struct ps3vram_priv *priv;
  485. int error, status;
  486. struct gendisk *gendisk;
  487. u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar,
  488. reports_size, xdr_lpar;
  489. char *rest;
  490. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  491. if (!priv) {
  492. error = -ENOMEM;
  493. goto fail;
  494. }
  495. spin_lock_init(&priv->lock);
  496. bio_list_init(&priv->list);
  497. ps3_system_bus_set_drvdata(dev, priv);
  498. /* Allocate XDR buffer (1MiB aligned) */
  499. priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL,
  500. get_order(XDR_BUF_SIZE));
  501. if (priv->xdr_buf == NULL) {
  502. dev_err(&dev->core, "Could not allocate XDR buffer\n");
  503. error = -ENOMEM;
  504. goto fail_free_priv;
  505. }
  506. /* Put FIFO at begginning of XDR buffer */
  507. priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET);
  508. priv->fifo_ptr = priv->fifo_base;
  509. /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
  510. if (ps3_open_hv_device(dev)) {
  511. dev_err(&dev->core, "ps3_open_hv_device failed\n");
  512. error = -EAGAIN;
  513. goto out_free_xdr_buf;
  514. }
  515. /* Request memory */
  516. status = -1;
  517. ddr_size = ALIGN(memparse(size, &rest), 1024*1024);
  518. if (!ddr_size) {
  519. dev_err(&dev->core, "Specified size is too small\n");
  520. error = -EINVAL;
  521. goto out_close_gpu;
  522. }
  523. while (ddr_size > 0) {
  524. status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
  525. &priv->memory_handle,
  526. &ddr_lpar);
  527. if (!status)
  528. break;
  529. ddr_size -= 1024*1024;
  530. }
  531. if (status) {
  532. dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n",
  533. status);
  534. error = -ENOMEM;
  535. goto out_close_gpu;
  536. }
  537. /* Request context */
  538. status = lv1_gpu_context_allocate(priv->memory_handle, 0,
  539. &priv->context_handle, &ctrl_lpar,
  540. &info_lpar, &reports_lpar,
  541. &reports_size);
  542. if (status) {
  543. dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n",
  544. status);
  545. error = -ENOMEM;
  546. goto out_free_memory;
  547. }
  548. /* Map XDR buffer to RSX */
  549. xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf));
  550. status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  551. xdr_lpar, XDR_BUF_SIZE,
  552. CBE_IOPTE_PP_W | CBE_IOPTE_PP_R |
  553. CBE_IOPTE_M);
  554. if (status) {
  555. dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n",
  556. status);
  557. error = -ENOMEM;
  558. goto out_free_context;
  559. }
  560. priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
  561. if (!priv->ctrl) {
  562. dev_err(&dev->core, "ioremap CTRL failed\n");
  563. error = -ENOMEM;
  564. goto out_unmap_context;
  565. }
  566. priv->reports = ioremap(reports_lpar, reports_size);
  567. if (!priv->reports) {
  568. dev_err(&dev->core, "ioremap REPORTS failed\n");
  569. error = -ENOMEM;
  570. goto out_unmap_ctrl;
  571. }
  572. mutex_lock(&ps3_gpu_mutex);
  573. ps3vram_init_ring(dev);
  574. mutex_unlock(&ps3_gpu_mutex);
  575. priv->size = ddr_size;
  576. ps3vram_bind(dev);
  577. mutex_lock(&ps3_gpu_mutex);
  578. error = ps3vram_wait_ring(dev, 100);
  579. mutex_unlock(&ps3_gpu_mutex);
  580. if (error < 0) {
  581. dev_err(&dev->core, "Failed to initialize channels\n");
  582. error = -ETIMEDOUT;
  583. goto out_unmap_reports;
  584. }
  585. error = ps3vram_cache_init(dev);
  586. if (error < 0) {
  587. goto out_unmap_reports;
  588. }
  589. ps3vram_proc_init(dev);
  590. gendisk = blk_alloc_disk(NUMA_NO_NODE);
  591. if (!gendisk) {
  592. dev_err(&dev->core, "blk_alloc_disk failed\n");
  593. error = -ENOMEM;
  594. goto out_cache_cleanup;
  595. }
  596. priv->gendisk = gendisk;
  597. gendisk->major = ps3vram_major;
  598. gendisk->minors = 1;
  599. gendisk->flags |= GENHD_FL_NO_PART;
  600. gendisk->fops = &ps3vram_fops;
  601. gendisk->private_data = dev;
  602. strscpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name));
  603. set_capacity(gendisk, priv->size >> 9);
  604. blk_queue_max_segments(gendisk->queue, BLK_MAX_SEGMENTS);
  605. blk_queue_max_segment_size(gendisk->queue, BLK_MAX_SEGMENT_SIZE);
  606. blk_queue_max_hw_sectors(gendisk->queue, BLK_SAFE_MAX_SECTORS);
  607. dev_info(&dev->core, "%s: Using %llu MiB of GPU memory\n",
  608. gendisk->disk_name, get_capacity(gendisk) >> 11);
  609. error = device_add_disk(&dev->core, gendisk, NULL);
  610. if (error)
  611. goto out_cleanup_disk;
  612. return 0;
  613. out_cleanup_disk:
  614. put_disk(gendisk);
  615. out_cache_cleanup:
  616. remove_proc_entry(DEVICE_NAME, NULL);
  617. ps3vram_cache_cleanup(dev);
  618. out_unmap_reports:
  619. iounmap(priv->reports);
  620. out_unmap_ctrl:
  621. iounmap(priv->ctrl);
  622. out_unmap_context:
  623. lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar,
  624. XDR_BUF_SIZE, CBE_IOPTE_M);
  625. out_free_context:
  626. lv1_gpu_context_free(priv->context_handle);
  627. out_free_memory:
  628. lv1_gpu_memory_free(priv->memory_handle);
  629. out_close_gpu:
  630. ps3_close_hv_device(dev);
  631. out_free_xdr_buf:
  632. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  633. fail_free_priv:
  634. kfree(priv);
  635. ps3_system_bus_set_drvdata(dev, NULL);
  636. fail:
  637. return error;
  638. }
  639. static void ps3vram_remove(struct ps3_system_bus_device *dev)
  640. {
  641. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  642. del_gendisk(priv->gendisk);
  643. put_disk(priv->gendisk);
  644. remove_proc_entry(DEVICE_NAME, NULL);
  645. ps3vram_cache_cleanup(dev);
  646. iounmap(priv->reports);
  647. iounmap(priv->ctrl);
  648. lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  649. ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
  650. XDR_BUF_SIZE, CBE_IOPTE_M);
  651. lv1_gpu_context_free(priv->context_handle);
  652. lv1_gpu_memory_free(priv->memory_handle);
  653. ps3_close_hv_device(dev);
  654. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  655. kfree(priv);
  656. ps3_system_bus_set_drvdata(dev, NULL);
  657. }
  658. static struct ps3_system_bus_driver ps3vram = {
  659. .match_id = PS3_MATCH_ID_GPU,
  660. .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
  661. .core.name = DEVICE_NAME,
  662. .core.owner = THIS_MODULE,
  663. .probe = ps3vram_probe,
  664. .remove = ps3vram_remove,
  665. .shutdown = ps3vram_remove,
  666. };
  667. static int __init ps3vram_init(void)
  668. {
  669. int error;
  670. if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
  671. return -ENODEV;
  672. error = register_blkdev(0, DEVICE_NAME);
  673. if (error <= 0) {
  674. pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error);
  675. return error;
  676. }
  677. ps3vram_major = error;
  678. pr_info("%s: registered block device major %d\n", DEVICE_NAME,
  679. ps3vram_major);
  680. error = ps3_system_bus_driver_register(&ps3vram);
  681. if (error)
  682. unregister_blkdev(ps3vram_major, DEVICE_NAME);
  683. return error;
  684. }
  685. static void __exit ps3vram_exit(void)
  686. {
  687. ps3_system_bus_driver_unregister(&ps3vram);
  688. unregister_blkdev(ps3vram_major, DEVICE_NAME);
  689. }
  690. module_init(ps3vram_init);
  691. module_exit(ps3vram_exit);
  692. MODULE_LICENSE("GPL");
  693. MODULE_DESCRIPTION("PS3 Video RAM Storage Driver");
  694. MODULE_AUTHOR("Sony Corporation");
  695. MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);