pgtable-2level.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _ASM_X86_PGTABLE_2LEVEL_H
  3. #define _ASM_X86_PGTABLE_2LEVEL_H
  4. #define pte_ERROR(e) \
  5. pr_err("%s:%d: bad pte %08lx\n", __FILE__, __LINE__, (e).pte_low)
  6. #define pgd_ERROR(e) \
  7. pr_err("%s:%d: bad pgd %08lx\n", __FILE__, __LINE__, pgd_val(e))
  8. /*
  9. * Certain architectures need to do special things when PTEs
  10. * within a page table are directly modified. Thus, the following
  11. * hook is made available.
  12. */
  13. static inline void native_set_pte(pte_t *ptep , pte_t pte)
  14. {
  15. *ptep = pte;
  16. }
  17. static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
  18. {
  19. *pmdp = pmd;
  20. }
  21. static inline void native_set_pud(pud_t *pudp, pud_t pud)
  22. {
  23. }
  24. static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
  25. {
  26. native_set_pte(ptep, pte);
  27. }
  28. static inline void native_pmd_clear(pmd_t *pmdp)
  29. {
  30. native_set_pmd(pmdp, __pmd(0));
  31. }
  32. static inline void native_pud_clear(pud_t *pudp)
  33. {
  34. }
  35. static inline void native_pte_clear(struct mm_struct *mm,
  36. unsigned long addr, pte_t *xp)
  37. {
  38. *xp = native_make_pte(0);
  39. }
  40. #ifdef CONFIG_SMP
  41. static inline pte_t native_ptep_get_and_clear(pte_t *xp)
  42. {
  43. return __pte(xchg(&xp->pte_low, 0));
  44. }
  45. #else
  46. #define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
  47. #endif
  48. #ifdef CONFIG_SMP
  49. static inline pmd_t native_pmdp_get_and_clear(pmd_t *xp)
  50. {
  51. return __pmd(xchg((pmdval_t *)xp, 0));
  52. }
  53. #else
  54. #define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp)
  55. #endif
  56. #ifdef CONFIG_SMP
  57. static inline pud_t native_pudp_get_and_clear(pud_t *xp)
  58. {
  59. return __pud(xchg((pudval_t *)xp, 0));
  60. }
  61. #else
  62. #define native_pudp_get_and_clear(xp) native_local_pudp_get_and_clear(xp)
  63. #endif
  64. /* Bit manipulation helper on pte/pgoff entry */
  65. static inline unsigned long pte_bitop(unsigned long value, unsigned int rightshift,
  66. unsigned long mask, unsigned int leftshift)
  67. {
  68. return ((value >> rightshift) & mask) << leftshift;
  69. }
  70. /* Encode and de-code a swap entry */
  71. #define SWP_TYPE_BITS 5
  72. #define SWP_OFFSET_SHIFT (_PAGE_BIT_PROTNONE + 1)
  73. #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
  74. #define __swp_type(x) (((x).val >> (_PAGE_BIT_PRESENT + 1)) \
  75. & ((1U << SWP_TYPE_BITS) - 1))
  76. #define __swp_offset(x) ((x).val >> SWP_OFFSET_SHIFT)
  77. #define __swp_entry(type, offset) ((swp_entry_t) { \
  78. ((type) << (_PAGE_BIT_PRESENT + 1)) \
  79. | ((offset) << SWP_OFFSET_SHIFT) })
  80. #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low })
  81. #define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val })
  82. /* No inverted PFNs on 2 level page tables */
  83. static inline u64 protnone_mask(u64 val)
  84. {
  85. return 0;
  86. }
  87. static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask)
  88. {
  89. return val;
  90. }
  91. static inline bool __pte_needs_invert(u64 val)
  92. {
  93. return false;
  94. }
  95. #endif /* _ASM_X86_PGTABLE_2LEVEL_H */