setup-sh770x.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SH3 Setup code for SH7706, SH7707, SH7708, SH7709
  4. *
  5. * Copyright (C) 2007 Magnus Damm
  6. * Copyright (C) 2009 Paul Mundt
  7. *
  8. * Based on setup-sh7709.c
  9. *
  10. * Copyright (C) 2006 Paul Mundt
  11. */
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/irq.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/serial.h>
  17. #include <linux/serial_sci.h>
  18. #include <linux/sh_timer.h>
  19. #include <linux/sh_intc.h>
  20. #include <cpu/serial.h>
  21. #include <asm/platform_early.h>
  22. enum {
  23. UNUSED = 0,
  24. /* interrupt sources */
  25. IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
  26. PINT07, PINT815,
  27. DMAC, SCIF0, SCIF2, SCI, ADC_ADI,
  28. LCDC, PCC0, PCC1,
  29. TMU0, TMU1, TMU2,
  30. RTC, WDT, REF,
  31. };
  32. static struct intc_vect vectors[] __initdata = {
  33. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  34. INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
  35. INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
  36. INTC_VECT(RTC, 0x4c0),
  37. INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
  38. INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
  39. INTC_VECT(WDT, 0x560),
  40. INTC_VECT(REF, 0x580),
  41. INTC_VECT(REF, 0x5a0),
  42. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  43. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  44. defined(CONFIG_CPU_SUBTYPE_SH7709)
  45. /* IRQ0->5 are handled in setup-sh3.c */
  46. INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
  47. INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
  48. INTC_VECT(ADC_ADI, 0x980),
  49. INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
  50. INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),
  51. #endif
  52. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  53. defined(CONFIG_CPU_SUBTYPE_SH7709)
  54. INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
  55. INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
  56. INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
  57. #endif
  58. #if defined(CONFIG_CPU_SUBTYPE_SH7707)
  59. INTC_VECT(LCDC, 0x9a0),
  60. INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
  61. #endif
  62. };
  63. static struct intc_prio_reg prio_registers[] __initdata = {
  64. { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
  65. { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
  66. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  67. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  68. defined(CONFIG_CPU_SUBTYPE_SH7709)
  69. { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
  70. { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
  71. { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
  72. #endif
  73. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  74. defined(CONFIG_CPU_SUBTYPE_SH7709)
  75. { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
  76. { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
  77. #endif
  78. #if defined(CONFIG_CPU_SUBTYPE_SH7707)
  79. { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
  80. #endif
  81. };
  82. static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,
  83. NULL, prio_registers, NULL);
  84. static struct resource rtc_resources[] = {
  85. [0] = {
  86. .start = 0xfffffec0,
  87. .end = 0xfffffec0 + 0x1e,
  88. .flags = IORESOURCE_IO,
  89. },
  90. [1] = {
  91. .start = evt2irq(0x480),
  92. .flags = IORESOURCE_IRQ,
  93. },
  94. };
  95. static struct platform_device rtc_device = {
  96. .name = "sh-rtc",
  97. .id = -1,
  98. .num_resources = ARRAY_SIZE(rtc_resources),
  99. .resource = rtc_resources,
  100. };
  101. static struct plat_sci_port scif0_platform_data = {
  102. .type = PORT_SCI,
  103. .ops = &sh770x_sci_port_ops,
  104. };
  105. static struct resource scif0_resources[] = {
  106. DEFINE_RES_MEM(0xfffffe80, 0x10),
  107. DEFINE_RES_IRQ(evt2irq(0x4e0)),
  108. };
  109. static struct platform_device scif0_device = {
  110. .name = "sh-sci",
  111. .id = 0,
  112. .resource = scif0_resources,
  113. .num_resources = ARRAY_SIZE(scif0_resources),
  114. .dev = {
  115. .platform_data = &scif0_platform_data,
  116. },
  117. };
  118. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  119. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  120. defined(CONFIG_CPU_SUBTYPE_SH7709)
  121. static struct plat_sci_port scif1_platform_data = {
  122. .type = PORT_SCIF,
  123. .ops = &sh770x_sci_port_ops,
  124. .regtype = SCIx_SH3_SCIF_REGTYPE,
  125. };
  126. static struct resource scif1_resources[] = {
  127. DEFINE_RES_MEM(0xa4000150, 0x10),
  128. DEFINE_RES_IRQ(evt2irq(0x900)),
  129. };
  130. static struct platform_device scif1_device = {
  131. .name = "sh-sci",
  132. .id = 1,
  133. .resource = scif1_resources,
  134. .num_resources = ARRAY_SIZE(scif1_resources),
  135. .dev = {
  136. .platform_data = &scif1_platform_data,
  137. },
  138. };
  139. #endif
  140. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  141. defined(CONFIG_CPU_SUBTYPE_SH7709)
  142. static struct plat_sci_port scif2_platform_data = {
  143. .type = PORT_IRDA,
  144. .ops = &sh770x_sci_port_ops,
  145. };
  146. static struct resource scif2_resources[] = {
  147. DEFINE_RES_MEM(0xa4000140, 0x10),
  148. DEFINE_RES_IRQ(evt2irq(0x880)),
  149. };
  150. static struct platform_device scif2_device = {
  151. .name = "sh-sci",
  152. .id = 2,
  153. .resource = scif2_resources,
  154. .num_resources = ARRAY_SIZE(scif2_resources),
  155. .dev = {
  156. .platform_data = &scif2_platform_data,
  157. },
  158. };
  159. #endif
  160. static struct sh_timer_config tmu0_platform_data = {
  161. .channels_mask = 7,
  162. };
  163. static struct resource tmu0_resources[] = {
  164. DEFINE_RES_MEM(0xfffffe90, 0x2c),
  165. DEFINE_RES_IRQ(evt2irq(0x400)),
  166. DEFINE_RES_IRQ(evt2irq(0x420)),
  167. DEFINE_RES_IRQ(evt2irq(0x440)),
  168. };
  169. static struct platform_device tmu0_device = {
  170. .name = "sh-tmu-sh3",
  171. .id = 0,
  172. .dev = {
  173. .platform_data = &tmu0_platform_data,
  174. },
  175. .resource = tmu0_resources,
  176. .num_resources = ARRAY_SIZE(tmu0_resources),
  177. };
  178. static struct platform_device *sh770x_devices[] __initdata = {
  179. &scif0_device,
  180. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  181. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  182. defined(CONFIG_CPU_SUBTYPE_SH7709)
  183. &scif1_device,
  184. #endif
  185. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  186. defined(CONFIG_CPU_SUBTYPE_SH7709)
  187. &scif2_device,
  188. #endif
  189. &tmu0_device,
  190. &rtc_device,
  191. };
  192. static int __init sh770x_devices_setup(void)
  193. {
  194. return platform_add_devices(sh770x_devices,
  195. ARRAY_SIZE(sh770x_devices));
  196. }
  197. arch_initcall(sh770x_devices_setup);
  198. static struct platform_device *sh770x_early_devices[] __initdata = {
  199. &scif0_device,
  200. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  201. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  202. defined(CONFIG_CPU_SUBTYPE_SH7709)
  203. &scif1_device,
  204. #endif
  205. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  206. defined(CONFIG_CPU_SUBTYPE_SH7709)
  207. &scif2_device,
  208. #endif
  209. &tmu0_device,
  210. };
  211. void __init plat_early_device_setup(void)
  212. {
  213. sh_early_platform_add_devices(sh770x_early_devices,
  214. ARRAY_SIZE(sh770x_early_devices));
  215. }
  216. void __init plat_irq_setup(void)
  217. {
  218. register_intc_controller(&intc_desc);
  219. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  220. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  221. defined(CONFIG_CPU_SUBTYPE_SH7709)
  222. plat_irq_setup_sh3();
  223. #endif
  224. }