proc.c 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151
  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/seq_file.h>
  3. #include <linux/kernel.h>
  4. #include <linux/module.h>
  5. #include <asm/machvec.h>
  6. #include <asm/processor.h>
  7. static const char *cpu_name[] = {
  8. [CPU_SH7201] = "SH7201",
  9. [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
  10. [CPU_SH7264] = "SH7264", [CPU_SH7269] = "SH7269",
  11. [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
  12. [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
  13. [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
  14. [CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
  15. [CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720",
  16. [CPU_SH7721] = "SH7721", [CPU_SH7729] = "SH7729",
  17. [CPU_SH7750] = "SH7750", [CPU_SH7750S] = "SH7750S",
  18. [CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751",
  19. [CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760",
  20. [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
  21. [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
  22. [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
  23. [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
  24. [CPU_SH7786] = "SH7786", [CPU_SH7757] = "SH7757",
  25. [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
  26. [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
  27. [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
  28. [CPU_SH7372] = "SH7372", [CPU_SH7734] = "SH7734",
  29. [CPU_J2] = "J2",
  30. [CPU_SH_NONE] = "Unknown"
  31. };
  32. const char *get_cpu_subtype(struct sh_cpuinfo *c)
  33. {
  34. return cpu_name[c->type];
  35. }
  36. EXPORT_SYMBOL(get_cpu_subtype);
  37. #ifdef CONFIG_PROC_FS
  38. /* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
  39. static const char *cpu_flags[] = {
  40. "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
  41. "ptea", "llsc", "l2", "op32", "pteaex", NULL
  42. };
  43. static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
  44. {
  45. unsigned long i;
  46. seq_printf(m, "cpu flags\t:");
  47. if (!c->flags) {
  48. seq_printf(m, " %s\n", cpu_flags[0]);
  49. return;
  50. }
  51. for (i = 0; cpu_flags[i]; i++)
  52. if ((c->flags & (1 << i)))
  53. seq_printf(m, " %s", cpu_flags[i+1]);
  54. seq_printf(m, "\n");
  55. }
  56. static void show_cacheinfo(struct seq_file *m, const char *type,
  57. struct cache_info info)
  58. {
  59. unsigned int cache_size;
  60. cache_size = info.ways * info.sets * info.linesz;
  61. seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
  62. type, cache_size >> 10, info.ways);
  63. }
  64. /*
  65. * Get CPU information for use by the procfs.
  66. */
  67. static int show_cpuinfo(struct seq_file *m, void *v)
  68. {
  69. struct sh_cpuinfo *c = v;
  70. unsigned int cpu = c - cpu_data;
  71. if (!cpu_online(cpu))
  72. return 0;
  73. if (cpu == 0)
  74. seq_printf(m, "machine\t\t: %s\n", get_system_type());
  75. else
  76. seq_printf(m, "\n");
  77. seq_printf(m, "processor\t: %d\n", cpu);
  78. seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
  79. seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
  80. if (c->cut_major == -1)
  81. seq_printf(m, "cut\t\t: unknown\n");
  82. else if (c->cut_minor == -1)
  83. seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
  84. else
  85. seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
  86. show_cpuflags(m, c);
  87. seq_printf(m, "cache type\t: ");
  88. /*
  89. * Check for what type of cache we have, we support both the
  90. * unified cache on the SH-2 and SH-3, as well as the harvard
  91. * style cache on the SH-4.
  92. */
  93. if (c->icache.flags & SH_CACHE_COMBINED) {
  94. seq_printf(m, "unified\n");
  95. show_cacheinfo(m, "cache", c->icache);
  96. } else {
  97. seq_printf(m, "split (harvard)\n");
  98. show_cacheinfo(m, "icache", c->icache);
  99. show_cacheinfo(m, "dcache", c->dcache);
  100. }
  101. /* Optional secondary cache */
  102. if (c->flags & CPU_HAS_L2_CACHE)
  103. show_cacheinfo(m, "scache", c->scache);
  104. seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
  105. seq_printf(m, "bogomips\t: %lu.%02lu\n",
  106. c->loops_per_jiffy/(500000/HZ),
  107. (c->loops_per_jiffy/(5000/HZ)) % 100);
  108. return 0;
  109. }
  110. static void *c_start(struct seq_file *m, loff_t *pos)
  111. {
  112. return *pos < NR_CPUS ? cpu_data + *pos : NULL;
  113. }
  114. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  115. {
  116. ++*pos;
  117. return c_start(m, pos);
  118. }
  119. static void c_stop(struct seq_file *m, void *v)
  120. {
  121. }
  122. const struct seq_operations cpuinfo_op = {
  123. .start = c_start,
  124. .next = c_next,
  125. .stop = c_stop,
  126. .show = show_cpuinfo,
  127. };
  128. #endif /* CONFIG_PROC_FS */