fixups-rts7751r2d.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * arch/sh/drivers/pci/fixups-rts7751r2d.c
  4. *
  5. * RTS7751R2D / LBOXRE2 PCI fixups
  6. *
  7. * Copyright (C) 2003 Lineo uSolutions, Inc.
  8. * Copyright (C) 2004 Paul Mundt
  9. * Copyright (C) 2007 Nobuhiro Iwamatsu
  10. */
  11. #include <linux/pci.h>
  12. #include <mach/lboxre2.h>
  13. #include <mach/r2d.h>
  14. #include "pci-sh4.h"
  15. #include <generated/machtypes.h>
  16. #define PCIMCR_MRSET_OFF 0xBFFFFFFF
  17. #define PCIMCR_RFSH_OFF 0xFFFFFFFB
  18. static u8 rts7751r2d_irq_tab[] = {
  19. IRQ_PCI_INTA,
  20. IRQ_PCI_INTB,
  21. IRQ_PCI_INTC,
  22. IRQ_PCI_INTD,
  23. };
  24. static char lboxre2_irq_tab[] = {
  25. IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
  26. };
  27. int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
  28. {
  29. if (mach_is_lboxre2())
  30. return lboxre2_irq_tab[slot];
  31. else
  32. return rts7751r2d_irq_tab[slot];
  33. }
  34. int pci_fixup_pcic(struct pci_channel *chan)
  35. {
  36. unsigned long bcr1, mcr;
  37. bcr1 = __raw_readl(SH7751_BCR1);
  38. bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
  39. pci_write_reg(chan, bcr1, SH4_PCIBCR1);
  40. /* Enable all interrupts, so we known what to fix */
  41. pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
  42. pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
  43. pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
  44. pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
  45. mcr = __raw_readl(SH7751_MCR);
  46. mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
  47. pci_write_reg(chan, mcr, SH4_PCIMCR);
  48. pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
  49. pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
  50. pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
  51. pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
  52. return 0;
  53. }