irq.c 1.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/sh/boards/se/7780/irq.c
  4. *
  5. * Copyright (C) 2006,2007 Nobuhiro Iwamatsu
  6. *
  7. * Hitachi UL SolutionEngine 7780 Support.
  8. */
  9. #include <linux/init.h>
  10. #include <linux/irq.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <mach-se/mach/se7780.h>
  14. #define INTC_BASE 0xffd00000
  15. #define INTC_ICR1 (INTC_BASE+0x1c)
  16. /*
  17. * Initialize IRQ setting
  18. */
  19. void __init init_se7780_IRQ(void)
  20. {
  21. /* enable all interrupt at FPGA */
  22. __raw_writew(0, FPGA_INTMSK1);
  23. /* mask SM501 interrupt */
  24. __raw_writew((__raw_readw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
  25. /* enable all interrupt at FPGA */
  26. __raw_writew(0, FPGA_INTMSK2);
  27. /* set FPGA INTSEL register */
  28. /* FPGA + 0x06 */
  29. __raw_writew( ((IRQPIN_SM501 << IRQPOS_SM501) |
  30. (IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1);
  31. /* FPGA + 0x08 */
  32. __raw_writew(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
  33. (IRQPIN_EXTINT3 << IRQPOS_EXTINT3) |
  34. (IRQPIN_EXTINT2 << IRQPOS_EXTINT2) |
  35. (IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2);
  36. /* FPGA + 0x0A */
  37. __raw_writew((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
  38. plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */
  39. /* ICR1: detect low level(for 2ndcut) */
  40. __raw_writel(0xAAAA0000, INTC_ICR1);
  41. /*
  42. * FPGA PCISEL register initialize
  43. *
  44. * CPU || SLOT1 | SLOT2 | S-ATA | USB
  45. * -------------------------------------
  46. * INTA || INTA | INTD | -- | INTB
  47. * -------------------------------------
  48. * INTB || INTB | INTA | -- | INTC
  49. * -------------------------------------
  50. * INTC || INTC | INTB | INTA | --
  51. * -------------------------------------
  52. * INTD || INTD | INTC | -- | INTA
  53. * -------------------------------------
  54. */
  55. __raw_writew(0x0013, FPGA_PCI_INTSEL1);
  56. __raw_writew(0xE402, FPGA_PCI_INTSEL2);
  57. }