setup.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas Technology Europe SDK7786 Support.
  4. *
  5. * Copyright (C) 2010 Matt Fleming
  6. * Copyright (C) 2010 Paul Mundt
  7. */
  8. #include <linux/init.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/io.h>
  11. #include <linux/regulator/fixed.h>
  12. #include <linux/regulator/machine.h>
  13. #include <linux/smsc911x.h>
  14. #include <linux/i2c.h>
  15. #include <linux/irq.h>
  16. #include <linux/clk.h>
  17. #include <linux/clkdev.h>
  18. #include <mach/fpga.h>
  19. #include <mach/irq.h>
  20. #include <asm/machvec.h>
  21. #include <asm/heartbeat.h>
  22. #include <linux/sizes.h>
  23. #include <asm/clock.h>
  24. #include <asm/reboot.h>
  25. #include <asm/smp-ops.h>
  26. static struct resource heartbeat_resource = {
  27. .start = 0x07fff8b0,
  28. .end = 0x07fff8b0 + sizeof(u16) - 1,
  29. .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
  30. };
  31. static struct platform_device heartbeat_device = {
  32. .name = "heartbeat",
  33. .id = -1,
  34. .num_resources = 1,
  35. .resource = &heartbeat_resource,
  36. };
  37. /* Dummy supplies, where voltage doesn't matter */
  38. static struct regulator_consumer_supply dummy_supplies[] = {
  39. REGULATOR_SUPPLY("vddvario", "smsc911x"),
  40. REGULATOR_SUPPLY("vdd33a", "smsc911x"),
  41. };
  42. static struct resource smsc911x_resources[] = {
  43. [0] = {
  44. .name = "smsc911x-memory",
  45. .start = 0x07ffff00,
  46. .end = 0x07ffff00 + SZ_256 - 1,
  47. .flags = IORESOURCE_MEM,
  48. },
  49. [1] = {
  50. .name = "smsc911x-irq",
  51. .start = evt2irq(0x2c0),
  52. .end = evt2irq(0x2c0),
  53. .flags = IORESOURCE_IRQ,
  54. },
  55. };
  56. static struct smsc911x_platform_config smsc911x_config = {
  57. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  58. .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
  59. .flags = SMSC911X_USE_32BIT,
  60. .phy_interface = PHY_INTERFACE_MODE_MII,
  61. };
  62. static struct platform_device smsc911x_device = {
  63. .name = "smsc911x",
  64. .id = -1,
  65. .num_resources = ARRAY_SIZE(smsc911x_resources),
  66. .resource = smsc911x_resources,
  67. .dev = {
  68. .platform_data = &smsc911x_config,
  69. },
  70. };
  71. static struct resource smbus_fpga_resource = {
  72. .start = 0x07fff9e0,
  73. .end = 0x07fff9e0 + SZ_32 - 1,
  74. .flags = IORESOURCE_MEM,
  75. };
  76. static struct platform_device smbus_fpga_device = {
  77. .name = "i2c-sdk7786",
  78. .id = 0,
  79. .num_resources = 1,
  80. .resource = &smbus_fpga_resource,
  81. };
  82. static struct resource smbus_pcie_resource = {
  83. .start = 0x07fffc30,
  84. .end = 0x07fffc30 + SZ_32 - 1,
  85. .flags = IORESOURCE_MEM,
  86. };
  87. static struct platform_device smbus_pcie_device = {
  88. .name = "i2c-sdk7786",
  89. .id = 1,
  90. .num_resources = 1,
  91. .resource = &smbus_pcie_resource,
  92. };
  93. static struct i2c_board_info __initdata sdk7786_i2c_devices[] = {
  94. {
  95. I2C_BOARD_INFO("max6900", 0x68),
  96. },
  97. };
  98. static struct platform_device *sh7786_devices[] __initdata = {
  99. &heartbeat_device,
  100. &smsc911x_device,
  101. &smbus_fpga_device,
  102. &smbus_pcie_device,
  103. };
  104. static int sdk7786_i2c_setup(void)
  105. {
  106. unsigned int tmp;
  107. /*
  108. * Hand over I2C control to the FPGA.
  109. */
  110. tmp = fpga_read_reg(SBCR);
  111. tmp &= ~SCBR_I2CCEN;
  112. tmp |= SCBR_I2CMEN;
  113. fpga_write_reg(tmp, SBCR);
  114. return i2c_register_board_info(0, sdk7786_i2c_devices,
  115. ARRAY_SIZE(sdk7786_i2c_devices));
  116. }
  117. static int __init sdk7786_devices_setup(void)
  118. {
  119. int ret;
  120. ret = platform_add_devices(sh7786_devices, ARRAY_SIZE(sh7786_devices));
  121. if (unlikely(ret != 0))
  122. return ret;
  123. return sdk7786_i2c_setup();
  124. }
  125. device_initcall(sdk7786_devices_setup);
  126. static int sdk7786_mode_pins(void)
  127. {
  128. return fpga_read_reg(MODSWR);
  129. }
  130. /*
  131. * FPGA-driven PCIe clocks
  132. *
  133. * Historically these include the oscillator, clock B (slots 2/3/4) and
  134. * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove
  135. * everything under a single PCIe clocks enable bit that happens to map
  136. * to the same bit position as the oscillator bit for earlier FPGA
  137. * versions.
  138. *
  139. * Given that the legacy clocks have the side-effect of shutting the CPU
  140. * off through the FPGA along with the PCI slots, we simply leave them in
  141. * their initial state and don't bother registering them with the clock
  142. * framework.
  143. */
  144. static int sdk7786_pcie_clk_enable(struct clk *clk)
  145. {
  146. fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR);
  147. return 0;
  148. }
  149. static void sdk7786_pcie_clk_disable(struct clk *clk)
  150. {
  151. fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
  152. }
  153. static struct sh_clk_ops sdk7786_pcie_clk_ops = {
  154. .enable = sdk7786_pcie_clk_enable,
  155. .disable = sdk7786_pcie_clk_disable,
  156. };
  157. static struct clk sdk7786_pcie_clk = {
  158. .ops = &sdk7786_pcie_clk_ops,
  159. };
  160. static struct clk_lookup sdk7786_pcie_cl = {
  161. .con_id = "pcie_plat_clk",
  162. .clk = &sdk7786_pcie_clk,
  163. };
  164. static int sdk7786_clk_init(void)
  165. {
  166. struct clk *clk;
  167. int ret;
  168. /*
  169. * Only handle the EXTAL case, anyone interfacing a crystal
  170. * resonator will need to provide their own input clock.
  171. */
  172. if (test_mode_pin(MODE_PIN9))
  173. return -EINVAL;
  174. clk = clk_get(NULL, "extal");
  175. if (IS_ERR(clk))
  176. return PTR_ERR(clk);
  177. ret = clk_set_rate(clk, 33333333);
  178. clk_put(clk);
  179. /*
  180. * Setup the FPGA clocks.
  181. */
  182. ret = clk_register(&sdk7786_pcie_clk);
  183. if (unlikely(ret)) {
  184. pr_err("FPGA clock registration failed\n");
  185. return ret;
  186. }
  187. clkdev_add(&sdk7786_pcie_cl);
  188. return 0;
  189. }
  190. static void sdk7786_restart(char *cmd)
  191. {
  192. fpga_write_reg(0xa5a5, SRSTR);
  193. }
  194. static void sdk7786_power_off(void)
  195. {
  196. fpga_write_reg(fpga_read_reg(PWRCR) | PWRCR_PDWNREQ, PWRCR);
  197. /*
  198. * It can take up to 20us for the R8C to do its job, back off and
  199. * wait a bit until we've been shut off. Even though newer FPGA
  200. * versions don't set the ACK bit, the latency issue remains.
  201. */
  202. while ((fpga_read_reg(PWRCR) & PWRCR_PDWNACK) == 0)
  203. cpu_sleep();
  204. }
  205. /* Initialize the board */
  206. static void __init sdk7786_setup(char **cmdline_p)
  207. {
  208. pr_info("Renesas Technology Europe SDK7786 support:\n");
  209. regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
  210. sdk7786_fpga_init();
  211. sdk7786_nmi_init();
  212. pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
  213. machine_ops.restart = sdk7786_restart;
  214. pm_power_off = sdk7786_power_off;
  215. register_smp_ops(&shx3_smp_ops);
  216. }
  217. /*
  218. * The Machine Vector
  219. */
  220. static struct sh_machine_vector mv_sdk7786 __initmv = {
  221. .mv_name = "SDK7786",
  222. .mv_setup = sdk7786_setup,
  223. .mv_mode_pins = sdk7786_mode_pins,
  224. .mv_clk_init = sdk7786_clk_init,
  225. .mv_init_irq = sdk7786_init_irq,
  226. };