vcpu_sbi_v01.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2021 Western Digital Corporation or its affiliates.
  4. *
  5. * Authors:
  6. * Atish Patra <[email protected]>
  7. */
  8. #include <linux/errno.h>
  9. #include <linux/err.h>
  10. #include <linux/kvm_host.h>
  11. #include <asm/csr.h>
  12. #include <asm/sbi.h>
  13. #include <asm/kvm_vcpu_timer.h>
  14. #include <asm/kvm_vcpu_sbi.h>
  15. static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
  16. unsigned long *out_val,
  17. struct kvm_cpu_trap *utrap,
  18. bool *exit)
  19. {
  20. ulong hmask;
  21. int i, ret = 0;
  22. u64 next_cycle;
  23. struct kvm_vcpu *rvcpu;
  24. struct kvm *kvm = vcpu->kvm;
  25. struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
  26. switch (cp->a7) {
  27. case SBI_EXT_0_1_CONSOLE_GETCHAR:
  28. case SBI_EXT_0_1_CONSOLE_PUTCHAR:
  29. /*
  30. * The CONSOLE_GETCHAR/CONSOLE_PUTCHAR SBI calls cannot be
  31. * handled in kernel so we forward these to user-space
  32. */
  33. kvm_riscv_vcpu_sbi_forward(vcpu, run);
  34. *exit = true;
  35. break;
  36. case SBI_EXT_0_1_SET_TIMER:
  37. #if __riscv_xlen == 32
  38. next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0;
  39. #else
  40. next_cycle = (u64)cp->a0;
  41. #endif
  42. ret = kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle);
  43. break;
  44. case SBI_EXT_0_1_CLEAR_IPI:
  45. ret = kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_SOFT);
  46. break;
  47. case SBI_EXT_0_1_SEND_IPI:
  48. if (cp->a0)
  49. hmask = kvm_riscv_vcpu_unpriv_read(vcpu, false, cp->a0,
  50. utrap);
  51. else
  52. hmask = (1UL << atomic_read(&kvm->online_vcpus)) - 1;
  53. if (utrap->scause)
  54. break;
  55. for_each_set_bit(i, &hmask, BITS_PER_LONG) {
  56. rvcpu = kvm_get_vcpu_by_id(vcpu->kvm, i);
  57. ret = kvm_riscv_vcpu_set_interrupt(rvcpu, IRQ_VS_SOFT);
  58. if (ret < 0)
  59. break;
  60. }
  61. break;
  62. case SBI_EXT_0_1_SHUTDOWN:
  63. kvm_riscv_vcpu_sbi_system_reset(vcpu, run,
  64. KVM_SYSTEM_EVENT_SHUTDOWN, 0);
  65. *exit = true;
  66. break;
  67. case SBI_EXT_0_1_REMOTE_FENCE_I:
  68. case SBI_EXT_0_1_REMOTE_SFENCE_VMA:
  69. case SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID:
  70. if (cp->a0)
  71. hmask = kvm_riscv_vcpu_unpriv_read(vcpu, false, cp->a0,
  72. utrap);
  73. else
  74. hmask = (1UL << atomic_read(&kvm->online_vcpus)) - 1;
  75. if (utrap->scause)
  76. break;
  77. if (cp->a7 == SBI_EXT_0_1_REMOTE_FENCE_I)
  78. kvm_riscv_fence_i(vcpu->kvm, 0, hmask);
  79. else if (cp->a7 == SBI_EXT_0_1_REMOTE_SFENCE_VMA) {
  80. if (cp->a1 == 0 && cp->a2 == 0)
  81. kvm_riscv_hfence_vvma_all(vcpu->kvm,
  82. 0, hmask);
  83. else
  84. kvm_riscv_hfence_vvma_gva(vcpu->kvm,
  85. 0, hmask,
  86. cp->a1, cp->a2,
  87. PAGE_SHIFT);
  88. } else {
  89. if (cp->a1 == 0 && cp->a2 == 0)
  90. kvm_riscv_hfence_vvma_asid_all(vcpu->kvm,
  91. 0, hmask,
  92. cp->a3);
  93. else
  94. kvm_riscv_hfence_vvma_asid_gva(vcpu->kvm,
  95. 0, hmask,
  96. cp->a1, cp->a2,
  97. PAGE_SHIFT,
  98. cp->a3);
  99. }
  100. break;
  101. default:
  102. ret = -EINVAL;
  103. break;
  104. }
  105. return ret;
  106. }
  107. const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 = {
  108. .extid_start = SBI_EXT_0_1_SET_TIMER,
  109. .extid_end = SBI_EXT_0_1_SHUTDOWN,
  110. .handler = kvm_sbi_ext_v01_handler,
  111. };