mpfs-sev-kit.dts 2.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2022 Microchip Technology Inc */
  3. /dts-v1/;
  4. #include "mpfs.dtsi"
  5. #include "mpfs-sev-kit-fabric.dtsi"
  6. /* Clock frequency (in Hz) of the rtcclk */
  7. #define MTIMER_FREQ 1000000
  8. / {
  9. #address-cells = <2>;
  10. #size-cells = <2>;
  11. model = "Microchip PolarFire-SoC SEV Kit";
  12. compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
  13. aliases {
  14. ethernet0 = &mac1;
  15. serial0 = &mmuart0;
  16. serial1 = &mmuart1;
  17. serial2 = &mmuart2;
  18. serial3 = &mmuart3;
  19. serial4 = &mmuart4;
  20. };
  21. chosen {
  22. stdout-path = "serial1:115200n8";
  23. };
  24. cpus {
  25. timebase-frequency = <MTIMER_FREQ>;
  26. };
  27. reserved-memory {
  28. #address-cells = <2>;
  29. #size-cells = <2>;
  30. ranges;
  31. fabricbuf0ddrc: buffer@80000000 {
  32. compatible = "shared-dma-pool";
  33. reg = <0x0 0x80000000 0x0 0x2000000>;
  34. };
  35. fabricbuf1ddrnc: buffer@c4000000 {
  36. compatible = "shared-dma-pool";
  37. reg = <0x0 0xc4000000 0x0 0x4000000>;
  38. };
  39. fabricbuf2ddrncwcb: buffer@d4000000 {
  40. compatible = "shared-dma-pool";
  41. reg = <0x0 0xd4000000 0x0 0x4000000>;
  42. };
  43. };
  44. ddrc_cache: memory@1000000000 {
  45. device_type = "memory";
  46. reg = <0x10 0x0 0x0 0x76000000>;
  47. };
  48. };
  49. &i2c0 {
  50. status = "okay";
  51. };
  52. &gpio2 {
  53. interrupts = <53>, <53>, <53>, <53>,
  54. <53>, <53>, <53>, <53>,
  55. <53>, <53>, <53>, <53>,
  56. <53>, <53>, <53>, <53>,
  57. <53>, <53>, <53>, <53>,
  58. <53>, <53>, <53>, <53>,
  59. <53>, <53>, <53>, <53>,
  60. <53>, <53>, <53>, <53>;
  61. status = "okay";
  62. };
  63. &mac0 {
  64. status = "okay";
  65. phy-mode = "sgmii";
  66. phy-handle = <&phy0>;
  67. phy1: ethernet-phy@9 {
  68. reg = <9>;
  69. };
  70. phy0: ethernet-phy@8 {
  71. reg = <8>;
  72. };
  73. };
  74. &mac1 {
  75. status = "okay";
  76. phy-mode = "sgmii";
  77. phy-handle = <&phy1>;
  78. };
  79. &mbox {
  80. status = "okay";
  81. };
  82. &mmc {
  83. status = "okay";
  84. bus-width = <4>;
  85. disable-wp;
  86. cap-sd-highspeed;
  87. cap-mmc-highspeed;
  88. mmc-ddr-1_8v;
  89. mmc-hs200-1_8v;
  90. sd-uhs-sdr12;
  91. sd-uhs-sdr25;
  92. sd-uhs-sdr50;
  93. sd-uhs-sdr104;
  94. };
  95. &mmuart1 {
  96. status = "okay";
  97. };
  98. &mmuart2 {
  99. status = "okay";
  100. };
  101. &mmuart3 {
  102. status = "okay";
  103. };
  104. &mmuart4 {
  105. status = "okay";
  106. };
  107. &refclk {
  108. clock-frequency = <125000000>;
  109. };
  110. &rtc {
  111. status = "okay";
  112. };
  113. &syscontroller {
  114. status = "okay";
  115. };
  116. &usb {
  117. status = "okay";
  118. dr_mode = "otg";
  119. };