mpfs-m100pfsevp.dts 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Original all-in-one devicetree:
  4. * Copyright (C) 2021-2022 - Wolfgang Grandegger <[email protected]>
  5. * Rewritten to use includes:
  6. * Copyright (C) 2022 - Conor Dooley <[email protected]>
  7. */
  8. /dts-v1/;
  9. #include "mpfs.dtsi"
  10. #include "mpfs-m100pfs-fabric.dtsi"
  11. /* Clock frequency (in Hz) of the rtcclk */
  12. #define MTIMER_FREQ 1000000
  13. / {
  14. model = "Aries Embedded M100PFEVPS";
  15. compatible = "aries,m100pfsevp", "microchip,mpfs";
  16. aliases {
  17. ethernet0 = &mac0;
  18. ethernet1 = &mac1;
  19. serial0 = &mmuart0;
  20. serial1 = &mmuart1;
  21. serial2 = &mmuart2;
  22. serial3 = &mmuart3;
  23. serial4 = &mmuart4;
  24. gpio0 = &gpio0;
  25. gpio1 = &gpio2;
  26. };
  27. chosen {
  28. stdout-path = "serial1:115200n8";
  29. };
  30. cpus {
  31. timebase-frequency = <MTIMER_FREQ>;
  32. };
  33. ddrc_cache_lo: memory@80000000 {
  34. device_type = "memory";
  35. reg = <0x0 0x80000000 0x0 0x40000000>;
  36. };
  37. ddrc_cache_hi: memory@1040000000 {
  38. device_type = "memory";
  39. reg = <0x10 0x40000000 0x0 0x40000000>;
  40. };
  41. };
  42. &can0 {
  43. status = "okay";
  44. };
  45. &i2c0 {
  46. status = "okay";
  47. };
  48. &i2c1 {
  49. status = "okay";
  50. };
  51. &gpio0 {
  52. interrupts = <13>, <14>, <15>, <16>,
  53. <17>, <18>, <19>, <20>,
  54. <21>, <22>, <23>, <24>,
  55. <25>, <26>;
  56. ngpios = <14>;
  57. status = "okay";
  58. pmic-irq-hog {
  59. gpio-hog;
  60. gpios = <13 0>;
  61. input;
  62. };
  63. /* Set to low for eMMC, high for SD-card */
  64. mmc-sel-hog {
  65. gpio-hog;
  66. gpios = <12 0>;
  67. output-high;
  68. };
  69. };
  70. &gpio2 {
  71. interrupts = <13>, <14>, <15>, <16>,
  72. <17>, <18>, <19>, <20>,
  73. <21>, <22>, <23>, <24>,
  74. <25>, <26>, <27>, <28>,
  75. <29>, <30>, <31>, <32>,
  76. <33>, <34>, <35>, <36>,
  77. <37>, <38>, <39>, <40>,
  78. <41>, <42>, <43>, <44>;
  79. status = "okay";
  80. };
  81. &mac0 {
  82. status = "okay";
  83. phy-mode = "gmii";
  84. phy-handle = <&phy0>;
  85. phy0: ethernet-phy@0 {
  86. reg = <0>;
  87. };
  88. };
  89. &mac1 {
  90. status = "okay";
  91. phy-mode = "gmii";
  92. phy-handle = <&phy1>;
  93. phy1: ethernet-phy@0 {
  94. reg = <0>;
  95. };
  96. };
  97. &mbox {
  98. status = "okay";
  99. };
  100. &mmc {
  101. max-frequency = <50000000>;
  102. bus-width = <4>;
  103. cap-mmc-highspeed;
  104. cap-sd-highspeed;
  105. no-1-8-v;
  106. sd-uhs-sdr12;
  107. sd-uhs-sdr25;
  108. sd-uhs-sdr50;
  109. sd-uhs-sdr104;
  110. disable-wp;
  111. status = "okay";
  112. };
  113. &mmuart1 {
  114. status = "okay";
  115. };
  116. &mmuart2 {
  117. status = "okay";
  118. };
  119. &mmuart3 {
  120. status = "okay";
  121. };
  122. &mmuart4 {
  123. status = "okay";
  124. };
  125. &pcie {
  126. status = "okay";
  127. };
  128. &qspi {
  129. status = "okay";
  130. };
  131. &refclk {
  132. clock-frequency = <125000000>;
  133. };
  134. &rtc {
  135. status = "okay";
  136. };
  137. &spi0 {
  138. status = "okay";
  139. };
  140. &spi1 {
  141. status = "okay";
  142. };
  143. &syscontroller {
  144. status = "okay";
  145. };
  146. &usb {
  147. status = "okay";
  148. dr_mode = "host";
  149. };