mpfs-m100pfs-fabric.dtsi 1.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2022 Microchip Technology Inc */
  3. / {
  4. fabric_clk3: fabric-clk3 {
  5. compatible = "fixed-clock";
  6. #clock-cells = <0>;
  7. clock-frequency = <62500000>;
  8. };
  9. fabric_clk1: fabric-clk1 {
  10. compatible = "fixed-clock";
  11. #clock-cells = <0>;
  12. clock-frequency = <125000000>;
  13. };
  14. pcie: pcie@2000000000 {
  15. compatible = "microchip,pcie-host-1.0";
  16. #address-cells = <0x3>;
  17. #interrupt-cells = <0x1>;
  18. #size-cells = <0x2>;
  19. device_type = "pci";
  20. reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
  21. reg-names = "cfg", "apb";
  22. bus-range = <0x0 0x7f>;
  23. interrupt-parent = <&plic>;
  24. interrupts = <119>;
  25. interrupt-map = <0 0 0 1 &pcie_intc 0>,
  26. <0 0 0 2 &pcie_intc 1>,
  27. <0 0 0 3 &pcie_intc 2>,
  28. <0 0 0 4 &pcie_intc 3>;
  29. interrupt-map-mask = <0 0 0 7>;
  30. clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
  31. clock-names = "fic0", "fic1", "fic3";
  32. ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
  33. msi-parent = <&pcie>;
  34. msi-controller;
  35. status = "disabled";
  36. pcie_intc: interrupt-controller {
  37. #address-cells = <0>;
  38. #interrupt-cells = <1>;
  39. interrupt-controller;
  40. };
  41. };
  42. };