mpfs-icicle-kit.dts 2.3 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2020-2021 Microchip Technology Inc */
  3. /dts-v1/;
  4. #include "mpfs.dtsi"
  5. #include "mpfs-icicle-kit-fabric.dtsi"
  6. /* Clock frequency (in Hz) of the rtcclk */
  7. #define RTCCLK_FREQ 1000000
  8. / {
  9. model = "Microchip PolarFire-SoC Icicle Kit";
  10. compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
  11. "microchip,mpfs";
  12. aliases {
  13. ethernet0 = &mac1;
  14. serial0 = &mmuart0;
  15. serial1 = &mmuart1;
  16. serial2 = &mmuart2;
  17. serial3 = &mmuart3;
  18. serial4 = &mmuart4;
  19. };
  20. chosen {
  21. stdout-path = "serial1:115200n8";
  22. };
  23. cpus {
  24. timebase-frequency = <RTCCLK_FREQ>;
  25. };
  26. ddrc_cache_lo: memory@80000000 {
  27. device_type = "memory";
  28. reg = <0x0 0x80000000 0x0 0x40000000>;
  29. status = "okay";
  30. };
  31. ddrc_cache_hi: memory@1040000000 {
  32. device_type = "memory";
  33. reg = <0x10 0x40000000 0x0 0x40000000>;
  34. status = "okay";
  35. };
  36. reserved-memory {
  37. #address-cells = <2>;
  38. #size-cells = <2>;
  39. ranges;
  40. hss_payload: region@BFC00000 {
  41. reg = <0x0 0xBFC00000 0x0 0x400000>;
  42. no-map;
  43. };
  44. };
  45. };
  46. &core_pwm0 {
  47. status = "okay";
  48. };
  49. &gpio2 {
  50. interrupts = <53>, <53>, <53>, <53>,
  51. <53>, <53>, <53>, <53>,
  52. <53>, <53>, <53>, <53>,
  53. <53>, <53>, <53>, <53>,
  54. <53>, <53>, <53>, <53>,
  55. <53>, <53>, <53>, <53>,
  56. <53>, <53>, <53>, <53>,
  57. <53>, <53>, <53>, <53>;
  58. status = "okay";
  59. };
  60. &i2c0 {
  61. status = "okay";
  62. };
  63. &i2c1 {
  64. status = "okay";
  65. };
  66. &i2c2 {
  67. status = "okay";
  68. };
  69. &mac0 {
  70. phy-mode = "sgmii";
  71. phy-handle = <&phy0>;
  72. status = "okay";
  73. };
  74. &mac1 {
  75. phy-mode = "sgmii";
  76. phy-handle = <&phy1>;
  77. status = "okay";
  78. phy1: ethernet-phy@9 {
  79. reg = <9>;
  80. };
  81. phy0: ethernet-phy@8 {
  82. reg = <8>;
  83. };
  84. };
  85. &mbox {
  86. status = "okay";
  87. };
  88. &mmc {
  89. bus-width = <4>;
  90. disable-wp;
  91. cap-sd-highspeed;
  92. cap-mmc-highspeed;
  93. mmc-ddr-1_8v;
  94. mmc-hs200-1_8v;
  95. sd-uhs-sdr12;
  96. sd-uhs-sdr25;
  97. sd-uhs-sdr50;
  98. sd-uhs-sdr104;
  99. status = "okay";
  100. };
  101. &mmuart1 {
  102. status = "okay";
  103. };
  104. &mmuart2 {
  105. status = "okay";
  106. };
  107. &mmuart3 {
  108. status = "okay";
  109. };
  110. &mmuart4 {
  111. status = "okay";
  112. };
  113. &pcie {
  114. status = "okay";
  115. };
  116. &qspi {
  117. status = "okay";
  118. };
  119. &refclk {
  120. clock-frequency = <125000000>;
  121. };
  122. &rtc {
  123. status = "okay";
  124. };
  125. &spi0 {
  126. status = "okay";
  127. };
  128. &spi1 {
  129. status = "okay";
  130. };
  131. &syscontroller {
  132. status = "okay";
  133. };
  134. &usb {
  135. status = "okay";
  136. dr_mode = "host";
  137. };