Kconfig.erratas 2.0 KB

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  1. menu "CPU errata selection"
  2. config ERRATA_SIFIVE
  3. bool "SiFive errata"
  4. depends on !XIP_KERNEL
  5. select RISCV_ALTERNATIVE
  6. help
  7. All SiFive errata Kconfig depend on this Kconfig. Disabling
  8. this Kconfig will disable all SiFive errata. Please say "Y"
  9. here if your platform uses SiFive CPU cores.
  10. Otherwise, please say "N" here to avoid unnecessary overhead.
  11. config ERRATA_SIFIVE_CIP_453
  12. bool "Apply SiFive errata CIP-453"
  13. depends on ERRATA_SIFIVE && 64BIT
  14. default y
  15. help
  16. This will apply the SiFive CIP-453 errata to add sign extension
  17. to the $badaddr when exception type is instruction page fault
  18. and instruction access fault.
  19. If you don't know what to do here, say "Y".
  20. config ERRATA_SIFIVE_CIP_1200
  21. bool "Apply SiFive errata CIP-1200"
  22. depends on ERRATA_SIFIVE && 64BIT
  23. default y
  24. help
  25. This will apply the SiFive CIP-1200 errata to repalce all
  26. "sfence.vma addr" with "sfence.vma" to ensure that the addr
  27. has been flushed from TLB.
  28. If you don't know what to do here, say "Y".
  29. config ERRATA_THEAD
  30. bool "T-HEAD errata"
  31. depends on !XIP_KERNEL
  32. select RISCV_ALTERNATIVE
  33. help
  34. All T-HEAD errata Kconfig depend on this Kconfig. Disabling
  35. this Kconfig will disable all T-HEAD errata. Please say "Y"
  36. here if your platform uses T-HEAD CPU cores.
  37. Otherwise, please say "N" here to avoid unnecessary overhead.
  38. config ERRATA_THEAD_PBMT
  39. bool "Apply T-Head memory type errata"
  40. depends on ERRATA_THEAD && 64BIT && MMU
  41. select RISCV_ALTERNATIVE_EARLY
  42. default y
  43. help
  44. This will apply the memory type errata to handle the non-standard
  45. memory type bits in page-table-entries on T-Head SoCs.
  46. If you don't know what to do here, say "Y".
  47. config ERRATA_THEAD_CMO
  48. bool "Apply T-Head cache management errata"
  49. depends on ERRATA_THEAD && MMU
  50. select RISCV_DMA_NONCOHERENT
  51. default y
  52. help
  53. This will apply the cache management errata to handle the
  54. non-standard handling on non-coherent operations on T-Head SoCs.
  55. If you don't know what to do here, say "Y".
  56. endmenu # "CPU errata selection"