km83xx.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2008-2011 DENX Software Engineering GmbH
  4. * Author: Heiko Schocher <[email protected]>
  5. *
  6. * Description:
  7. * Keymile 83xx platform specific routines.
  8. */
  9. #include <linux/stddef.h>
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/errno.h>
  13. #include <linux/reboot.h>
  14. #include <linux/pci.h>
  15. #include <linux/kdev_t.h>
  16. #include <linux/major.h>
  17. #include <linux/console.h>
  18. #include <linux/delay.h>
  19. #include <linux/seq_file.h>
  20. #include <linux/root_dev.h>
  21. #include <linux/initrd.h>
  22. #include <linux/of_platform.h>
  23. #include <linux/of_device.h>
  24. #include <linux/atomic.h>
  25. #include <linux/time.h>
  26. #include <linux/io.h>
  27. #include <asm/machdep.h>
  28. #include <asm/ipic.h>
  29. #include <asm/irq.h>
  30. #include <asm/udbg.h>
  31. #include <sysdev/fsl_soc.h>
  32. #include <sysdev/fsl_pci.h>
  33. #include <soc/fsl/qe/qe.h>
  34. #include "mpc83xx.h"
  35. #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
  36. static void __init quirk_mpc8360e_qe_enet10(void)
  37. {
  38. /*
  39. * handle mpc8360E Erratum QE_ENET10:
  40. * RGMII AC values do not meet the specification
  41. */
  42. uint svid = mfspr(SPRN_SVR);
  43. struct device_node *np_par;
  44. struct resource res;
  45. void __iomem *base;
  46. int ret;
  47. np_par = of_find_node_by_name(NULL, "par_io");
  48. if (np_par == NULL) {
  49. pr_warn("%s couldn't find par_io node\n", __func__);
  50. return;
  51. }
  52. /* Map Parallel I/O ports registers */
  53. ret = of_address_to_resource(np_par, 0, &res);
  54. if (ret) {
  55. pr_warn("%s couldn't map par_io registers\n", __func__);
  56. goto out;
  57. }
  58. base = ioremap(res.start, resource_size(&res));
  59. if (!base)
  60. goto out;
  61. /*
  62. * set output delay adjustments to default values according
  63. * table 5 in Errata Rev. 5, 9/2011:
  64. *
  65. * write 0b01 to UCC1 bits 18:19
  66. * write 0b01 to UCC2 option 1 bits 4:5
  67. * write 0b01 to UCC2 option 2 bits 16:17
  68. */
  69. clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
  70. /*
  71. * set output delay adjustments to default values according
  72. * table 3-13 in Reference Manual Rev.3 05/2010:
  73. *
  74. * write 0b01 to UCC2 option 2 bits 16:17
  75. * write 0b0101 to UCC1 bits 20:23
  76. * write 0b0101 to UCC2 option 1 bits 24:27
  77. */
  78. clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
  79. if (SVR_REV(svid) == 0x0021) {
  80. /*
  81. * UCC2 option 1: write 0b1010 to bits 24:27
  82. * at address IMMRBAR+0x14AC
  83. */
  84. clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
  85. } else if (SVR_REV(svid) == 0x0020) {
  86. /*
  87. * UCC1: write 0b11 to bits 18:19
  88. * at address IMMRBAR+0x14A8
  89. */
  90. setbits32((base + 0xa8), 0x00003000);
  91. /*
  92. * UCC2 option 1: write 0b11 to bits 4:5
  93. * at address IMMRBAR+0x14A8
  94. */
  95. setbits32((base + 0xa8), 0x0c000000);
  96. /*
  97. * UCC2 option 2: write 0b11 to bits 16:17
  98. * at address IMMRBAR+0x14AC
  99. */
  100. setbits32((base + 0xac), 0x0000c000);
  101. }
  102. iounmap(base);
  103. out:
  104. of_node_put(np_par);
  105. }
  106. /* ************************************************************************
  107. *
  108. * Setup the architecture
  109. *
  110. */
  111. static void __init mpc83xx_km_setup_arch(void)
  112. {
  113. #ifdef CONFIG_QUICC_ENGINE
  114. struct device_node *np;
  115. #endif
  116. mpc83xx_setup_arch();
  117. #ifdef CONFIG_QUICC_ENGINE
  118. np = of_find_node_by_name(NULL, "par_io");
  119. if (np != NULL) {
  120. par_io_init(np);
  121. of_node_put(np);
  122. for_each_node_by_name(np, "spi")
  123. par_io_of_config(np);
  124. for_each_node_by_name(np, "ucc")
  125. par_io_of_config(np);
  126. /* Only apply this quirk when par_io is available */
  127. np = of_find_compatible_node(NULL, "network", "ucc_geth");
  128. if (np != NULL) {
  129. quirk_mpc8360e_qe_enet10();
  130. of_node_put(np);
  131. }
  132. }
  133. #endif /* CONFIG_QUICC_ENGINE */
  134. }
  135. machine_device_initcall(mpc83xx_km, mpc83xx_declare_of_platform_devices);
  136. /* list of the supported boards */
  137. static char *board[] __initdata = {
  138. "Keymile,KMETER1",
  139. "Keymile,kmpbec8321",
  140. NULL
  141. };
  142. /*
  143. * Called very early, MMU is off, device-tree isn't unflattened
  144. */
  145. static int __init mpc83xx_km_probe(void)
  146. {
  147. int i = 0;
  148. while (board[i]) {
  149. if (of_machine_is_compatible(board[i]))
  150. break;
  151. i++;
  152. }
  153. return (board[i] != NULL);
  154. }
  155. define_machine(mpc83xx_km) {
  156. .name = "mpc83xx-km-platform",
  157. .probe = mpc83xx_km_probe,
  158. .setup_arch = mpc83xx_km_setup_arch,
  159. .discover_phbs = mpc83xx_setup_pci,
  160. .init_IRQ = mpc83xx_ipic_init_IRQ,
  161. .get_irq = ipic_get_irq,
  162. .restart = mpc83xx_restart,
  163. .time_init = mpc83xx_time_init,
  164. .calibrate_decr = generic_calibrate_decr,
  165. .progress = udbg_progress,
  166. };