perf_event.h 1.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Performance event support - hardware-specific disambiguation
  4. *
  5. * For now this is a compile-time decision, but eventually it should be
  6. * runtime. This would allow multiplatform perf event support for e300 (fsl
  7. * embedded perf counters) plus server/classic, and would accommodate
  8. * devices other than the core which provide their own performance counters.
  9. *
  10. * Copyright 2010 Freescale Semiconductor, Inc.
  11. */
  12. #ifdef CONFIG_PPC_PERF_CTRS
  13. #include <asm/perf_event_server.h>
  14. #else
  15. static inline bool is_sier_available(void) { return false; }
  16. static inline unsigned long get_pmcs_ext_regs(int idx) { return 0; }
  17. #endif
  18. #ifdef CONFIG_FSL_EMB_PERF_EVENT
  19. #include <asm/perf_event_fsl_emb.h>
  20. #endif
  21. #ifdef CONFIG_PERF_EVENTS
  22. #include <asm/ptrace.h>
  23. #include <asm/reg.h>
  24. #define perf_arch_bpf_user_pt_regs(regs) &regs->user_regs
  25. /*
  26. * Overload regs->result to specify whether we should use the MSR (result
  27. * is zero) or the SIAR (result is non zero).
  28. */
  29. #define perf_arch_fetch_caller_regs(regs, __ip) \
  30. do { \
  31. (regs)->result = 0; \
  32. (regs)->nip = __ip; \
  33. (regs)->gpr[1] = current_stack_frame(); \
  34. asm volatile("mfmsr %0" : "=r" ((regs)->msr)); \
  35. } while (0)
  36. /* To support perf_regs sier update */
  37. extern bool is_sier_available(void);
  38. extern unsigned long get_pmcs_ext_regs(int idx);
  39. /* To define perf extended regs mask value */
  40. extern u64 PERF_REG_EXTENDED_MASK;
  41. #define PERF_REG_EXTENDED_MASK PERF_REG_EXTENDED_MASK
  42. #endif